Key words: ZVT, Synchronous buck converter, soft switching, Losses, Efficiency.

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Volume 3, Issue 5, May 2013 ISSN: 2277 128X Iteratioal Joural of Advaced Research i Computer Sciece ad Software Egieerig Research Paper Available olie at: www.ijarcsse.

Abstract: Power electroic coverters play a importat role i may electroic circuits used i portable applicatio.

1 Volume 3, Issue 5, May 2013 ISSN: X Iteratioal Joural of Advaced Research i Computer Sciece ad Software Egieerig Research Paper Available olie at: Implemetatio of modified sychroous buck coverter for portable applicatio Divya Navamai.J* 1 Assistat professor, EEE dept, SRM uiversity Idia. A.Lavaya 2 Assistat professor, EEE dept, SRM uiversity Idia. Abstract: Power electroic coverters play a importat role i may electroic circuits used i portable applicatio. I this work two zero-voltage-trasitio (ZVT) pulse width modulated (PWM) sychroous buck coverters are proposed, oe with passive compoet ad the other with active compoet. These are desiged especially for low power device applicatios such as chargig mobile phoe batteries ad laptop batteries. The operatio priciples, switchig ad coductio losses of the ZVT-PWM sychroous coverters are preseted. I additio, the proposed coverter circuits are cheaper, more reliable ad have a higher performace / cost ratio. The proposed system is simulated i the MATLAB-Simulik eviromet. Key words: ZVT, Sychroous buck coverter, soft switchig, Losses, Efficiecy. I. INTRODUCTION The role played by power covertig circuits is extremely importat to almost ay electroic system built today. The growig demad of computers i medical istrumets, aircraft, defiace, space market, idustrial automatio ad commercial applicatios impede the geeral power quality solutios, but sparked the eed of precise solutios. With the icreasig demad of uiterrupted ad high quality power for critical loads, power coverter should be properly desig to match the ature of the load, the type of power distributio, the quality of local power ad the required reliability. Recet advaces i power coverter edorses high efficiecy, high power desity. Lower operatig voltages, icreased curret requiremets ad the dyamic characteristics of microprocessor based or microcotroller based system create ew demads o power distributio ad maagemet [2]. The issues such as achievig high efficiecy, high power desity, ad proper voltage regulatio etc., [22] become critical if buck coverters are cosidered for low operatig voltage [3]. Circuits that use coverters of ay type deped o power that is cosistet i form ad reliable i order to properly fuctio. I additio, today s demads require more efficiet use of eergy, from large statioary systems such as power plats all the way dow to small mobile devices such as laptops ad cell phoes. This places a eed to reduce ay losses to a miimum. The power coversio circuitry i a system is a very good place to reduce a large amout of uecessary loss. This ca be doe usig circuit topologies that are low loss i ature. For low loss ad high performace, soft switchig topologies have offered solutios i some cases. Attaiig high performace ad low power cosumptio i MP3 players, persoal media players, digital cameras ad other portable cosumer applicatios has log bee a challege for desigers. Naturally, battery life is of prime importace i hadheld battery-powered products, makig their success directly related to the efficiecy of the power system. A key compoet of such systems is the step dow dc-dc switchig regulator, which is also commoly referred to as a step dow dc-dc coverter or buck coverter with low efficiecy of switchig coverters [3]. However small size requiremets ecoutered i computer systems ad portable devices call for icreased switchig frequecies. As the switchig frequecy is icreased, the beefit of the low MOSFET o resistace (Rdso,) is dimiished by the icrease i the switchig losses, the gate drive loss, ad the body diode loss [3] [4]. Supply voltage scalig is a essetial step i the techology scalig process. Two primary reasos for scalig the supply voltage are to maitai the power desity of a itegrated circuit below a limit dictated by available cost effective coolig techiques ad to guaratee the log term reliability of maufactured devices. Microprocessors, with icreased power cosumptio ad reduced supply voltages, demad greater amouts of curret from exteral power supplies, creatig a icreasigly sigificat power geeratio ad distributio problem (both o chip ad off-chip) with each ew techology geeratio [2-4]. Eergy efficiet, low oise power delivery has become icreasigly challegig with the advacemet of itegrated circuit techologies [5]. The paper is orgaized as follows: Sectio II gives the basic operatio of sychroous buck coverter. Sectio III presets differet losses i coverters. Sectio IV ad V briefs the basic features of ZVT techiques. Sectio VI gives simulatio results. Sectio VII icludes efficiecy compariso. II. SYNCHRONOUS BUCK CONVERTER I the sychroous buck coverter topology, a power MOSFET replaces the traditioal buck coverter outputstage commutatig diode. This improvemet reduces the typical 0.5-V-to-1-V diode drop to about 0.3 V or less, resultig i typical circuit efficiecy improvemets of aroud 5% ad higher. The basic sychroous buck coverter 2013, IJARCSSE All Rights Reserved Page 246

2 Divya et al., Iteratioal Joural of Advaced Research i Computer Sciece ad Software Egieerig 3(5), circuit icludes a pair of MOSFETs, a output filter, ad a cotroller that provides the sychroous switchig fuctio [6] [7]. Figure 1 shows the simplified schematic diagram of a typical sychroous buck coverter. Fig. 1: Basic Sychroous buck coverter III LOSSES IN CONVERTER MOSFETs are very popularly used i most coverters so it makes the most sice to use them i the descriptio of switchig elemet loss. The switch losses ca be divided ito to geeral forms of loss, coductio losses ad switchig losses. These losses are described i detail below [8]. The calculatios used are approximatios sice the iteral losses of every device caot be measured durig operatio. This is a umerical method based o certai device characteristics with the sychroous buck coverter i mid. A. CONDUCTION LOSSES Coductio losses are defied as losses that are sustaied due to the equivalet resistace of the MOSFET chael after the chael is completely ehaced. This resistace is the Eds (o) value for the trasistor [9]. Estimatio of this loss ca be made usig the followig equatios for the high ad low side devices. 2 P I R D (1) CONDHS DS ( ON ) P CONDHS 2 I R (1 D) (2) DS ( ON ) B. SWITCHING LOSS Switchig Losses occur durig switchig trasitios as spikes i power are created due to risig voltage ad fallig curret overlaps ad vice versa depedig o the trasitio occurrig. I geeral these losses occur due to device parasitic capacitaces. A good part of the switchig losses sustaied are due to the chargig ad dischargig of these capacitaces through larger resistace the are see durig device coductio. The equatios used for estimatio of these losses the below. P t t. out SW( HS ). FSW. s( L Vi I ts( LH ) ts( H L) (3) 2 QG( SW) H ) (4) I PRIVER ( LH ) Q G( SW) s( H L) (5) I PRIVER ( H L) VF I.1.1. RPS ( IN ) PSW ( LS) t2. VF t3.. I. FSW 2 (6) t 2R K2R. RDRIVER RGATE. CISS (7) Note for the low side that equatio 6 is used twice to calculate the risig ad fallig edge losses. Diode losses durig dead space are icluded as switchig losses as well with equatio1, these losses are ofte lumped with the low side switchig losses sice it typically is the low side MOSFET s body diode coductig. These are additioal losses, due to the gate drive that are typically isigificat uless the switchig frequecy becomes extremely high, that ot stated here [8]. Fig. 2: Simulatio of Sychroous Buck Coverter 2013, IJARCSSE All Rights Reserved Page 247

Divya et al., Iteratioal Joural of Advaced Research i Computer Sciece ad Software Egieerig 3(5), Fig. 3: simulated output of Sychroous Buck Coverter IV.

3 Divya et al., Iteratioal Joural of Advaced Research i Computer Sciece ad Software Egieerig 3(5), Fig. 3: simulated output of Sychroous Buck Coverter IV. ZVS, ZCS, & ZVT Uderstadig how soft switchig is accomplished is importat i uderstadig how to use the topologies that achieve this goal. Soft switchig topologies make use of additioal circuit elemets passive or active i order to limit di/dt or dv/dt durig switchig ad miimize curret ad voltage overlap to reduce switchig losses [9-12]. Essetially, i the switchig device at the switchig iterval, either the curret or the voltage must be drive to zero to brig the product of the two as close to zero as possible. This leads to the cocepts of zero voltage switchig (ZVS) ad zero curret switchig (ZCS)[24-27]. Just as i the ame either the voltage or curret is drive to zero durig switchig. There are may topologies that use ZVS, ZCS, or both to reduce overall switchig losses. Coverters such as the oes termed as quasi-resoat ca be used to achieve ZVS or ZCS [28]. However, coverters such as these ca cause additioal problems that offset soft switchig beefits, such as additioal voltage or curret stress o the mai switch [30]. Coverters that have soft switchig but reduce or elimiate this stress are more highly desirable. For this reaso, what are kow as zero voltage trasitio (ZVT) coverters have become very popular ad as stated previously, the umber of ZVT topologies that have bee itroduced is large [16-18]. ZVT coverters accomplish soft switchig while VDRIVE VDRIVE K 2 R (8) VDRIVE VSP VDRIVE VTH t K. R R. C (9) DRIVER GATE ISS 2R 3R Miimizig additioal stresses associated with other previous topologies [28-29]. Fig. 4: Soft switchig coverter with Active compoet V. SOFT SWITCHING There are may types of ZVT coverters. This class of coverters has bee categorized more thoroughly ito various types i [30]. However, i geeral there are two types of ZVT coverters, oes that use passive auxiliary circuit elemets oly such as i [15] ad oes that use active elemets i the auxiliary circuit [19]21][23]. Active types will be the oly oes discussed to follow. Although there are may differet topologies that use ZVT the basic cocept ca explaied by usig the buck topology from [21]. This family of topologies is typically cosidered to be the covetioal ZVT topologies. I this sectio ZVT will be explaied usig a example with this covetioal ZVT buck coverter. Below is simulatio of this topology i MATLAB ad its correspodig waveforms. VDRIVE VDRIVE K 3 R (10) VDRIVE 0.9. VSPEC VDRIVE VSP 2013, IJARCSSE All Rights Reserved Page 248

DIODE Divya et al., Iteratioal Joural of Advaced Research i Computer Sciece ad Software Egieerig 3(5), t. F. V I (11) P. DEADTIME SW F Fig. 5: Soft switchig coverter with Passive compoet VI.

The coverter has ot exceeded the voltage limits; however the curret stress is slightly higher for a very short period of time. The mai switch also switches off uder ZVS.

4 DIODE Divya et al., Iteratioal Joural of Advaced Research i Computer Sciece ad Software Egieerig 3(5), t. F. V I (11) P. DEADTIME SW F Fig. 5: Soft switchig coverter with Passive compoet VI.SIMULATION RESULTS It is oted from that the mai switch S is tured o uder ZVS, whe voltage across Cs is zero. The coverter has ot exceeded the voltage limits; however the curret stress is slightly higher for a very short period of time. The mai switch also switches off uder ZVS. The curret ad voltage waveforms obtaied through simulatio ad experimetal ivestigatios are i close agreemet with the theoretical aalysis. It is oted that auxiliary switch S 1 also operates with soft switchig. The switch S 1 is tured o uder ZCS because of the iductor L r ad turs off uder ZCS whe resoat curret through L r ad C r falls to zero. Its body diode also turs o as soo as S 1 is off at zero curret ad turs off whe the resoat curret is zero. The auxiliary switch is active oly for a short period of time, which is verified by its coductio period ad it is too small. Also, the curret ad voltage stresses are well withi the operatig limits. Fig. 6: Mai switch Curret ad voltage Fig. 7: Sychroous switch curret ad voltage VII.COMPARISON CURVE The efficiecy of covetioal sychroous buck coverter is compared with the Zero Voltage Trasitio Sychroous coverter It ca be observed that the efficiecy values of the soft switchig coverter are relatively high with respect to those of the hard switchig coverter. The efficiecy values towards the miimum output power decrease aturally because the coverter is desiged for the maximum output curret. At 50% output power, the overall efficiecy of the proposed coverter icreases to about 95% from the value of 85% i its couterpart hard switchig coverter. The high efficiecy cocludes the correctess of the desig values. 2013, IJARCSSE All Rights Reserved Page 249

5 Divya et al., Iteratioal Joural of Advaced Research i Computer Sciece ad Software Egieerig 3(5), sychroous buck coverter Modified sychroous buck coverter Fig. 8: Compariso of efficiecy (Syc Buck Vs ZVT Syc Buck) VIII CONCLUSION Soft switchig ca be used to improve coverter performace. However several factors come ito play that ca ifluece the beefits of soft switchig. Examples of these factors are power semicoductor techology, switchig frequecy, ad power rage. Based o the data obtaied it seems that for the give compoets, switchig frequecy, load rage, ad other operatig characteristics that the beefits of ZVT are outweighed by the additioal losses iduced. By operatig at a fairly low switchig frequecy ad usig switchig compoets that have iheretly low switchig losses, ZVT s beefits might be overshadowed at this load rage. Aother factor that could be cotributig to the discrepacy i the efficiecy data could be the legth of the resoace period used i this desig. The resoace period legth could be reduced leadig to smaller coductio losses ad perhaps higher efficiecies. REFERENCES [1] Djekic O., Brkovic M., ad Roy A., - High frequecy sychroous buck coverter for low voltage applicatios, i proceedigs of IEEE PESC 98, vol.2, pp [2] Kursu V., Naredra S.G., De V.K., ad Friedma E.G., - Aalysis of buck coverters for o-chip itegratio with a dual supply voltage microprocessor, i IEEE Trasactios o Very Large Scale Itegratio (VLSI) Systems, Jue 2003, vol.11, o.3, pp [3] Batarseh: Power Electroic Circuits, Joh Wiley & sos, New York, [4] Paov Y. ad Jovaovic M.M., - Desig ad performace evaluatio of low-voltage / high-curret DC/DC oboard modules, i IEEE Trasactios o Power Electios, Jauary 2001, vol.16(10, pp [5] Moticelli D.M., - Takig a system approach to eergy maagemet, i proceedigs of the 29th Europea Solid-State Circuits Coferece, ESSCIRC 03, Sep.2003, pp [6] R.J.Baker: CMOS circuit desig, layout, ad simulatio, revised secod editio, Joh Wiley & Sos, Hoboke, New Jersey, [7] R.F.Pierret: Semicoductor Device Fudametals, Addiso-Wesley, [8] Jo Klei, Sychroous buck MOSFET loss calculatios with excel model, Product ad techical iformatio / desig resources Jauary 4, [9] B.Jayat Baliga, Treds i Power Semicoductor Devices, IEEE Trasactios o Electro Devices, Vol.43, No.10, October [10] Paov Y., ad Jovaovic M.M., - Desig cosideratios for 12-V/1.5-V, 50-A voltage regulator modules, i IEEE Trasactios o Power Electroics, Nov 2001 vol.16(6), pp [11] Yao K., Qiu Y., Xu M., ad Lee F.C., - A ovel widig coupled buck coverter for high-frequecy, high-step-dow DC-DC coversio, i IEEE Trasactios o Power Electroics, September 2005, vol.20(5), pp [12] Lima F., Satos M., ad Barata J. Dead-Time cotrol system for a sychroous Buck dc-dc coverter, i POWERENG [13] G.Hua, C. S.Leu, Y.Jiag, F.C.T. Lee, Novel Zero-Voltage Trasitio PWM coverters, IEEE trasactios o Power Electroics, vol.9, No.2, March , IJARCSSE All Rights Reserved Page 250

6 Divya et al., Iteratioal Joural of Advaced Research i Computer Sciece ad Software Egieerig 3(5), [14] K.H. Liu, F.C.Y. Lee, Zero-voltage switchig techique i DC/DC coverters, IEEE trasactios o power electroics, vol.5, No.3, July [15] W.Huag, X.Gao, S.Bassa, G.Moschopoulos, Novel dual auxiliary circuits for ZVT-PWM coverters, Ca.J.Elect. Comput. Eg., Vol.33, No.3/4, summer / fall [16] E.Adib,H. Farzaehfard, Family of isolated zero-voltage trasistio PWM coverters, IET power electro, 2008, vol.1, No.1, pp [17] E.Adib, H.Farzaehfard, Zero voltage Trasistio PWM coverters with sychroous rectifier, IEEE trasactios o power electroics, vol.25, No.1, Jauary [18] E Adib,H. Farzaehfard, New zero voltage trasistio PWM coverters ICIT2006, IEEE Iteratioal coferece o, Idustrial techology, 2006, pp [19] S.Pattaik, A.K. Pada, K.K.Mahapatra, Efficiecy improvemet of sychroous buck coverter by New passive auxiliary circuit, TENCON 2008 Regio 10 cofeece, 2008, pp.1-6. [20] L.Shi, L.Che, C. Yi A ovel PWM soft switchig DC-DC coverter, INTELEC 06, 28th Aual iteratioal, telecommuicatios eergy cof., 2006,pp ] M.L.Martis, H.Piheiro, J.R.Piheiro, H.A. Grudig, H.L. Hey, Family of improved ZVT PWM coverters usig a self-commutated auxiliary etwork, IEE Proc-Electr. Power Appl. Vol.150, No.6, November [22] J.Wibbe, R.Harjai, A high-efficiecy DC-DC coverter usig 2 H itegrated iductors, IEEE joural of solid state circuits, Vol.43, No.4, April [23] M.Alimadadi, S.Sheikhaei, G.Lemieux, S.Mirabbasi, W.G.Duford, P.R. Palmer, A fully itegrated 660 MHz low-swig eergy-recyclig DC-DC Coverter, IEEE trasactios o power electroic, vol.24, No.6, Jue [24] W.R.Liou, M.L.Yeh, Y.L.Kuo, A high efficiecy dual-mode buck coverter IC for portable applicatios, IEEE trasactios o power electroics, vol.23, No.2, March [25] N.Wag, T.O Doell, R.Meere, F.M.Rhe, S.Roy, S.C.O Mathua, Thi-Film-Itegrated Power Iductor o Si ad Its Performace i a 8-Mhz Buck Coverter, IEEE Trasactios o Magetics, Vol.44, No11, November [26] Y.C.Chuag, Y.L.Ke, High-Efficiecy ad Low-Stress ZVT-PWM DC-to-DC Coverter for Battery Charger, IEEE Trasactios o Idustrial Electroics, Vol.55, No.8, August [27] Kim T.W., Kim H.S., ad Ah H.W., - H.W. A improved ZVT PWM boost coverter, i proceedigs of IEEE PESC 2000, pp [28] M.L.Martis, J.L. Russi, H.L.Hey Zero-voltage trasitio PWM coverters: a classificatio methodology, IEE Proc-Electr. Power Appl. Vol.152, No.2, March [29] T.Dyer, J.McGity, A.Stracha, C.Bulucea, Moolithic Itegratio of Trech vertical DMOS (VDMOS) Power trasistors ito a BCD process, Proc. ISPSD 05, The 17th Iteratioal symposium o, power semicoductor devices ad IC s, 2005, pp [30] P.T. Krei: Elemets of Power Electroics, Oxford Uiversity Press, New York, NY, J. Divya Navamai received her B.E degree i Electrical ad Electroics Egieerig from Madras Uiversity i 2001 ad M.E i Power Electroics ad Idustrial drives i 2005 ad curretly workig as Assistat Professor/EEE, SRM Uiversity. Her research iterests are dc-dc coverter i battery maagemet system. A. Lavaya obtaied her B.E degree i Electrical ad Electroics Egieerig from Madras Uiversity i 2001 ad M.E i Power Electroics ad Idustrial drives i 2005 ad curretly workig as Assistat Professor/EEE, SRM Uiversity. Her research iterests are No liearity i power electroics ad Dyamic systems. 2013, IJARCSSE All Rights Reserved Page 251

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doi: info:doi/ /ifeec doi: ifo:doi/1.119/ifeec.17.799153 Trasformer Desig Difficulties of Curret Resoat Coverter for High Power Desity ad Wide Iput ltage Rage Toshiyuki Zaitsu Embedded System Research Ceter Omro Corporatio