Reduction of Harmonic in a Multilevel Inverter Using Optimized Selective Harmonic Elimination Approach

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1 ISSN (Olie) : ISSN (Prit) : Iteratioal Joural of Iovative Research i Sciece, Egieerig ad Techology Volume 3, Special Issue 3, March Iteratioal Coferece o Iovatios i Egieerig ad Techology (ICIET 14) O 21 st & 22 d March Orgaized by K.L.N. College of Egieerig, Madurai, Tamil Nadu, Idia Reductio of Harmoic i a Multilevel Iverter Usig Optimized Selective Harmoic Elimiatio Approach Prof S.Parthasarathy #1, R.Siva *2 #1 Departmet of Electrical ad Electroics Egieerig, K.L.N College of Egieerig, Madurai, Idia *2 Departmet of Electrical ad Electroics Egieerig, K.L.N College of Egieerig, Madurai, Idia ABSTRACT This paper adopts the Geetic Algorithm (GA) optimizatio techique for harmoic elimiatio i cascaded H-Bridge Multilevel iverter. The objective of the proposed work is to elimiate the lower order harmoics by decipherig o-liear equatios correspodig to SHE. I this proposed work switchig agles for power electroics switches preset i the Multilevel Iverter are geerated. The geerated switchig agle is optimized usig GA for improvig the accuracy of results. The results obtaied shows the effectives of proposed work of it was verified usig MATLAB software. KEYWORDS Power quality, Total Harmoic Distortio, Multilevel iverter, Cascaded iverter, Selective Harmoic Elimiatio, Geetic Algorithm. levels usig cascaded coectio of several sigle phase iverters at low voltage level with better harmoic spectrum of output voltage. The CMLI topology is sigificat advatages, it requires least umber of compoet compared to the DCMLI ad FCMLI topology. The desired output of Multilevel Iverter cotai o harmoic compoets as per IEEE , IEC stadards i the power systems [5]. To cotrol the output voltage ad to elimiate certai lower order harmoics i a multilevel ierter with equal dc sources, various cotrol techiques are ivestigated such as Selective Harmoic Elimiatio (SHE), Siusoidal Pulse Width Modulatio (SPWM), Space Vector Modulatio (SVM) [7]. However the PWM techique could ot elimiate specific lower order harmoics such as 3 rd to15 th I. INTRODUCTION problem is used to fid the switchig agles. I this method switchig agles are solved by o-liear Power Quality has bee give cosideratio due to trascedetal equatios which cotai trigoometric wide applicatio of multilevel iverter for cotrollig ad terms. This set of trascedetal equatios ca be solved covertig ac power ad to feed electrical loads. These by usig iterative methods such as Newto-Raphsa (Niverters are used at differet power levels, ragig from R) method [8]. The N-R method iitial values are must large adjustable speed drives to low power household be iitialized. Therefore N-R method will ot able to appliaces. The huge amout of power pollutio produced solve the SHE problem for a large umber of switchig from this o-liear load has caused a voltage distortio. agles. I recet year multilevel iverter are applied i idustrial Geetic Algorithm (GA) has bee proposed to solve applicatio such as power supplies, static VAR the trascedetal equatios, [8]-[12]. Therefore i this compesator, drive systems, etc. The multilevel iverter proposed work by usig a optimizig method like GA, has several advatage compared to the two level Iverters a attempt is made to solve SHE equatio whole rage of such as lower commo mode voltage, less dv/dt, lower modulatio idex ad Total Harmoic Distortio (THD). harmoics i output voltage ad reduced lower switchig I this proposed work sigle phase cascaded H-bridge devices [1]-[4]. five level iverter is chose for aalysis. The Multilevel iverter is geerally divided ito three differet categories: Diode Clamped Multilevel Iverter II. CMLI WITH SEPREATE DC SOURCE (DCMLI), Flyig Capacitor Multilevel Iverter (FCMLI) ad Cascaded Multilevel Iverter (CMLI) [3]. Amog all topologies cascade multilevel iverters are capable of A Iverter structure, CMLI with separate DC source reachig medium voltage ad high power applicatios is familiarized here. This iverter avoids extra clampig Copyright to IJIRSET 98 [6]. Multilevel iverter

2 diodes ad a voltage balacig capacitor as a sigle phase structure. The AC termial voltages of differet voltage level iverters are coected i series. The basic structure of cascaded H-bridge iverter with separate dc source, show i Fig. 1. The sythesized output voltage waveform of five level cascaded iverter is show i Fig.2. The phase output voltage is sythesized by the summig the of iverter output, i.e. ( Va V V ). Each cell ca geerate a1 a2 three level of output +V dc, 0, -V dc. Each cell of iverter cosist of four switches S 1, S 2, S 3 ad S 4 usig the first cell as example, turig o S 1 ad S 4 yield V 1 = +V dc. Turig o S 2 ad S 3 yield V 1 = -V dc. Turig off all switches yield V 1 = 0. Correspodigly, the ac output voltage at each level ca be obtaied i the same maer. Miimum harmoic distortio ca be attaied by adjustig the switchig agles of the iverter. S 1 S 2 S 3 S 4 S 5 S 6 Vdc t 0 si (4) (5) dc b cos3 3 1 (6) dc b 5 cos5 1 (7) : : dc 1 cos d vab dc b 1 1 cos (8) V dc - voltage of a level, b - amplitude of the harmoics order, Ɵ - Switchig agles. M S 7 S 8 Vdc 2 +V dc1 +V dc2 Fig. 1 CMLI with Separate DC Source 2π 0 π III. SELECTIVE HARMONIC ELIMINATION SWITCHING TECHNIQUE A five level iverter output voltage waveforms show i Fig. 2 has two variables Ɵ 1, Ɵ 2. Cosiderig equal amplitude of all DC sources V dc1 ad V dc2, the Fourier series expasio of output waveform writte as, V ab t a0 a cos t si t 1 (1) The Fourier series for odd fuctios cotai oly sie terms: a 0 =0 ad a =0. The sie fuctio is odd 2 2 si for odd (2) 0 Vab tca be retur as, t t V ab odd si (3) Copyright to IJIRSET V dc2 -V dc1 Ɵ1 Ɵ2 Ɵ3 Ɵ4 Ɵ5 Ɵ6 Ɵ7 Ɵ8 Fig. 2 The Sythesized Phase Voltage Waveform of Five level Cascaded 00000Iverter. It ca be see from the output voltage waveform of fudametal as well as order of harmoic compoets. That the compoets of the output voltage ca be divided ito three parts, amely fudametal harmoic compoet, triple odd harmoic compoet (=3, 9, 15...), o-triple odd harmoic compoet (=3, 5, 7, 9, 11, 13, ad 15). Which is dissipated i eq (1). I order to miimize the THDv o output side umber of maximum possible o-triple odd harmoic compoet has to be elimiated. The domiatig order of harmoics i the propose iverter is 3 rd to 15 th order. They are elimiated by usig the SHE techique. I this

3 proposed work switchig agles for five level CMLI has bee calculated by elimiatig o-triple odd harmoic compoets. The fudametal output voltage usig SHE is give i eq (5). IV. OPTIMIZED SHE ALGORITHM The workig ability of GA is based o Darwi s theory of survival of the fittest. GA cotais chromosome, gees, set of populatio, fitess, fitess fuctio, breedig, mutatio ad selectio. GA begis with a set of solutios represeted by chromosomes is called populatio. Solutios from oe populatio are take ad used to form a ew populatio, which is motivated by the possibility that the ew populatio will be better tha the old oe. Additioal, solutios are selected accordig to their fitess to form ew solutios. The above process is repeated util termiatio coditio is satisfied. GA is used for solvig both costraied ad ucostraied optimizatio problem based o atural selectio. By the process of optimizatio the iput of a CMLI is modified, mathematical process to obtai miimum or maximum of the output. The iput of the optimizatio process is the objective fuctio ad the output is the switchig agle of the CMLI % THD v b X100 3 (9) b 1 Subject to: 0< Ɵ 1< Ɵ 2< (10) fitess values are used to determie a ew offsprig s. These offsprig uder goes crossover ad mutatio. To create a ew populatio. For each chromosome a five level output voltage are geerated usig the switchig agles show i Table 1 ad harmoic magitude are calculated usig Fast Fourier Trasformatio aalysis (FFT). = 4i ± 1 (i = 1, 2, 3 ) I order to solve the SHE equatio, GA is used to geeratig switchig agles Ɵ 1, Ɵ 2 for a five level CMLI by varyig modulatio idex from 0 to 1is subjected to elimiatio of lower of order harmoic compoets. Eq (9) is selected as a objective fuctio for the proposed Fig. 3 Simulatio model for five level CMLT usig SHE techique optimizatio techique. The algorithm of proposed is follows, 1. Select floatig poit strig. 2. Fid the umber of variables (umber of switchig agle is two). 3. Set a populatio size ad iitialize the populatio. Whe the populatio size is higher, icrease the rate of covergece ad also icrease the executio time. The populatio is iitialized betwee 0 degree ad 180 degree takig ito cosideratio of the full wave symmetry of output voltages. 4. Evaluate of fitess for each chromosome is the most importat part of GA. The objective Fig. 4 Output waveform of five level CMLT usig SHE Techique fuctio is to miimize the specific lower order harmoics. I the proposed work, 3 rd to 15 th The proposed work is simulated usig odd MATLAB/SIMULINK to check it validatio. The harmoics at the output side of a five level parameters for simulatio are as follows, voltage of each cascaded iverter are to be miimized. bridge (V dc = 50v), frequecy of the output voltage (f = 5. Set the iteratio cout (100 iteratio) to fid the 50Hz). The simulated waveform of the output voltage switchig agles. Subsequetly the first iteratio, Copyright to IJIRSET V. RESULT AND DISCUSSION A sigle phase five level CMLI usig SHE techique ad variatio of switchig agles are simulated usig MATLAB/Simulik. A five level iverter requires two bridges for simulatio. IGBT s are used as power switches. Fig. 3 shows the simulated circuit of five level CMLI usig SHE techique.

4 usig SHE techique is show i Fig. 4 from Fig. 5 the harmoic spectra of the output voltage ca be viewed for further calculatios. I GA s, the calculated switchig agles are simulated through the five level CMLI. The results are preseted i this sectio. The output voltage waveform of the proposed work at M=0.55 is show i Fig. 6. I order to clarify the amplitude of miimized harmoic spectra of the output voltage is show i Fig. 7 i this case 3 rd to 15 th harmoic are miimized. Fig. 5 Harmoic spectrum of Five level CMLI usig N -R method. Fig. 7 Harmoic spectrum of Five level CMLI usig GA From the Fig. 5 ad Fig. 7 is obvious that the harmoics are reduced effectively by computig the switchig agles by GA as compared to the N-R method. The proposed simulatio studies have bee coducted o Itel(R) core (TM) Duo 2, CPU 2.00 GHZ processor uder MATLAB 2012b eviromet. Switchig agles TABLE I SWITCHING ANGLE COMPARISON OF CMLI Covetioal Techique (SHE) rad/sec GA rad/sec Ɵ Ɵ Fig. 6 Output waveform of Five Level Iverter For each chromosome a five level output voltage is geerated usig the switchig agles obtaied from the proposed work as show i Table 1 ad required harmoic magitude are calculated usig FFT aalysis. The Fig. 5 Depicts the harmoic profile of the output voltage is simulated with switchig agles calculated from SHE techique by N-R method ad Fig. 8 harmoic spectrum aalysis it is iferred that the THDv whe calculated usig i GA was is 30.78% ad that for N-R is 80.88%. TABLE II COMPARISON OF MINIMIZATION OF THD V WITH ORDER OF HARMONICS Order of Harmoics Covetioal Techique (SHE) (%) GA (%) THDv = THDv = rd th th th th th th VI. CONCLUSION I this paper GA optimizatio techique is applied to fid the appropriated switchig agles for the CMLI to elimiate harmoics. Selected order of harmoic are reduced ad the fudametal output voltage is maitaied at desired level, thus resultig i the miimum THDv. The proposed method reduces the Copyright to IJIRSET 101

5 harmoics compoet tha ay other covetioal techique such as N-R method. The effectiveess of the proposed method has bee verified through simulatio ad the results were preseted. The results show that the proposed method effectively miimizes the domiatig 3 rd order harmoic. REFERENCES [1] M.H.J. Bolle, What is power quality?, Electric Power Systems Research, Vol.66(2003),pp [2] Partha S. Bhowmik ad S.Segupta, Electric Power Quality i a Deregulated Power System: A Review, Iteratioal Coferece o Power Systems, ICPS (2004), pp [3] J. Rodr guez, J. Lai, ad F. Z. Peg, Multilevel iverters: A survey of topologies, cotrols ad applicatios, IEEE Tras. Id. Electro., vol. 49, o. 4, pp , Aug [4] J. S. Lai ad F. Z. Peg, Multilevel coverters A ew breed of power coverters, IEEE Tras. Id. Appl., vol. 32, o. 3, pp , May/Ju [5] Duffey, C.K.; Stratford, R.P., "Update of harmoic stadard IEEE-519-IEEE Recommeded Practices ad Requiremets for Harmoic Cotrol i Electric Power Systems," Idustry Applicatios Society Aual Meetig, 1989., Coferece Record of the 1989 IEEE, vol., o., pp.1618,1624 vol.2, 1-5 Oct [6] Wami Fei; Xiaoli Du; Bi Wu, "A Geeralized Half-Wave Symmetry SHE-PWM Formulatio for Multilevel Voltage Iverters," IEEE Tras. Id. Appl., vol.57, o.9, pp.3030,3038, Sept [7] Krismadiata, Nasrudi ABD Rahim, Hew Wooi Pig, Jeyaral Selvaraj," Elimiatio of Harmoics i Photovoltaic Seve-level iverter with Newto-Raphso optimizatio", "procedia eviromet Scieces 17(2013) ". [8] Ozpieci, J. O. P. Pito, ad L. M. Tolbert, Pulse-width optimizatio i a pulse desity modulated high frequecy AC-AC coverter usig geetic algorithms, i Proc. IEEE It. Cof. Systems, Ma, ad Cyberetics,2001, pp [9] I. Maswood, S.Wei, ad M. A. Rahma, A flexible way to geerate PWM-SHE switchig patters usig geetic algorithms, i Proc. IEEE Applied Power Electroics Cof. Expo., 2001, pp [10] Houck, J.Joies, ad M.Kay. The Geetic Algorithm Optimizatio Toolbox (GAOT) for MATLAB 5. [olie]. Available: [11] Padi, P.M.; Devaraja, N., "Optimizatio of power quality i cascaded multilevel iverter-geetic algorithm approach," Iteratioal Coferece o Computig, Commuicatio ad Networkig Techologies.,vol., o., pp.1,7, July [12] Ramkumar, S.; Kamaraj, V.; Thamizharasa, S., "GA based optimizatio ad critical evaluatio SHE methods for three-level iverter," Iteratioal Coferece o, Electrical Eergy Systems (ICEES), 201.,vol., o., pp.115,121, 3-5 Ja Copyright to IJIRSET 102