Analysis and Software Implementation of a Robust Synchronizing Circuit PLL Circuit

Transcription

1 Aalysis ad Software Implemetatio of a Robust Sychroizig Circuit PLL Circuit Diogo R. COSTA, Jr., Luís G. B. ROLIM, ad Maurício AREDES 3,,3 COPPE, UFRJ, Cidade Uiversitária, Rio de Jaeiro, Brazil, ( diogo, rolim, aredes 3 )@coe.ufrj.br Abstract This paper presets the aalysis ad software implemetatio of a robust sychroizig circuit PLL circuit desiged for usig i the cotroller of active power lie coditioers. The basic problem cosists i desigig a PLL circuit that ca track accurately ad cotiuously the positivesequece compoet at the fudametal frequecy ad its phase agle, eve whe the system voltage of the bus, to which the active power lie coditioer is coected, is distorted ad/or ubalaced. The fudamets of the PLL circuit are discussed. It is show that the PLL ca fail i trackig the system voltage durig the startup, uder some adverse coditios. Moreover, it is show that oscillatios caused by the presece of sub-harmoics ca be very critical ad ca pull the stable poit of operatio sychroized to that subharmoic frequecy. Oscillatios at the referece iput are also discussed, ad the solutio of this problem is preseted. Fially, experimetal ad simulatio results are show ad compared. Idex Terms Phase-Locked Loop (PLL). I. INTRODUCTION referece iput u (t) VCO output u (t) phase detector (PD) phase u d (t) cotrolled oscillator (VCO) Fig. Block diagram of basic PLL structure loop filter (LF) VCO iput u f (t) Most applicatios of static coverters coected to the utility power grid require sychroizatio betwee the grid voltage ad the voltage or curret sythesized by the coverter. As examples of such applicatios ca be poited out: coverters that iject eergy comig from alterative supplies ito the grid; Active Power Lie Coditioers, FACTS ad Custom Power devices (e.g. DVR, STATCOM, active filters []-[3]). I may cases, the referece sigal obtaied from the grid voltage is cotamiated by harmoics, which may have bee produced by the power coverter itself or geerated elsewhere. Additioally, the voltages i a three-phase system may cotai ubalaces from egative- ad/or zerosequece compoets, which could cause improper sychroizatio betwee coverter ad grid. The most widely accepted solutio to provide sychroizatio betwee time-varyig sigals is the use of a phaselocked-loop (PLL) system that ca be described by the basic structure show i block diagram form i Fig.. This simplified PLL structure comprises a phase detector (PD), a loop filter (LF) ad a cotrolled oscillator (VCO), each of which ca be implemeted i several differet forms. If the sigal to be tracked (referece iput) is a aalog sigal, the the most suitable type of PD to be used is the product-type oe. The use of a product-type PD plus a liear LF causes the PLL to behave liearly for small variatios o iput, yieldig a liear PLL. II. FUNDAMENTALS OF THE LINEAR PLL CIRCUIT I this work, the referece iput is represeted by a space vector, as well as the VCO output: jwt j t u ( t) Ue ad u ( t) U w e () I statioary () referece frame, both sigals ca be writte i the form u(t) = u + ju. Three-phase iput sigals ca be easily coverted to this form through the Clarke Trasformatio. Alteratively, these sigals ca be represeted i a sychroously rotatig referece frame (through the Park Trasformatio) as show i [5], with similar results. The agular frequecy of the VCO output sigal is related to its iput u f (t) by: = + u f (t), () where is called the ceter frequecy. The phase detector operates o the product of both space vectors u (t) ad u (t). For this reaso it is ofte called a vector-product phase detector (VP-PD). Its output ca thus be writte as u d (t) = Im{u (t). u (t)}, which yields: u d (t) = U U.si( - ), (3) for = = (PLL i the locked state at the ceter frequecy). For small phase deviatios, this relatioship ca be approximated liearly by: u d (t) K d. e (t), (4) where K d = U U ad e (t) = (t) (t). If the amplitudes U ad U are both ormalized to uity, the (4) further simplifies to u d (t) e (t). As a result, the liearized behavior of the PLL ca be described by the simplified block diagram show i Fig.. I the block diagram show i Fig., the ceter frequecy appears as a term added to the output of the PI loop /3/$7. 3 IEEE 9

2 (t) filter. This produces the same effect as a o-zero iitial coditio at the itegrator s output. For a proportioal plus itegral (PI-type) loop filter as the oe show i Fig., the liearized loop trasfer fuctio betwee (t) ad (t) is give by: ( s) K Ps Ki H ( s). (5) ( s) s K Ps Ki H(s) ca be rewritte i the form: s (6) H ( s) s s where (t) + - e (t) u f KP + (t) K i Ki s loop filter Fig. Small-sigal block diagram. K P ad. K Well-desiged PLL systems should meet the followig desig criteria:.7 for optimum trasiet respose (ITAE sese); arrow badwith (low ) for improved oise rejectio, i order to produce a purely siusoidal output sigal eve i the presece of iput harmoics. The PLL lock rage is defied as the maximum iitial frequecy deviatio betwee referece iput ad VCO output, which will still cause the PLL to get locked i a sigle beat. It ca be show to be approximately equal to the atural frequecy : L. (7) Thus, a arrow-badwith PLL may fail to lock at some i s VCO desired frequecy durig the start-up trasiet, if followig coditios are met: the iput sigal cotais harmoic compoets; the iitial PI output is more distat from the desired frequecy tha the lock rage; the iitial PI output (or the ceter frequecy) is close to some harmoic. It is however very difficult to predict the behavior of the PLL uder the above coditios, because it depeds o the relative amplitude of the harmoic compoets. Subharmoic oscillatios at the referece iput ca cause the PLL to lock at the lower sub-harmoic frequecy, eve if the relative magitude is very low. This fact is illustrated by the simulatio results preseted i Fig. 3a ad Fig. 3b. For both simulatios, the frequecy of iterest is 6Hz (with ormalized amplitude of p.u.) ad a disturbace at Hz has bee added. The iitial coditio at the PI loop filter output is zero, what meas that the VCO starts from zero frequecy or DC coditios. If the disturbace is slightly icreased beyod 7% of the mai compoet, the PLL fails to lock at the desired ceter frequecy of 6Hz. Fig. 3a shows a critical situatio where 7% of disturbace at Hz is itroduced ad the PLL still locks at the ceter frequecy (6Hz). However, it locks at Hz istead, as show i Fig. 3b, if the disturbace is icreased to % at Hz. As the frequecy of iterest for grid-coected applicatios is essetially costat (5Hz or 6Hz), a obvious solutio to the above problem would be tuig the PLL by adjustig its ceter frequecy to the omial grid frequecy. However, a eve safer solutio is the itroductio of limits to the PI output, so that the VCO frequecy variatio is cofied to the ceter frequecy (chose equal to the grid frequecy) plus or mius the lock rage. A potetial risk itroduced by this approach is the chace of occurrig so-called reset widup problems i the cotroller [6], which ca lead to udesired oscillatios, umerical overflow problems ad eve to istability. To avoid these difficulties, some ati widup strategy should be used for implemetatio of the cotrol algorithms. This solutio has f(hz) 8 7 f(hz) Fig. 3 results for sub-harmoic disturbaces at Hz: 7% i magitude ad % i magitude

3 bee implemeted by software i a TMS3LF47 DSP. Some implemetatio details are give i the ext sectio. i si(t) III. IMPLEMENTATION DETAILS The proposed PLL system was implemeted with fixedpoit arithmetic i the TMS3LF47 DSP, usig a khz samplig frequecy. The algorithm is executed as a iterrupt service routie (ISR), which is triggered by oe of the geeral-purpose timer circuits available o-chip. The same timer also triggers the acquisitio of iput sigals, simultaeously with the iterrupts. As the o-chip A/D coverters are fast (approximately 5s coversio time), iput data is made available at the begiig of the ISR with egligible time delay. A simplified block-diagram represetatio of the implemeted algorithm is show i Fig. 6. The lie voltages v ab ad v bc are coverted to the referece frame through the Clarke Trasformatio, immediately after A/D coversio. The feedback sigals correspodig to VCO output (labeled i ad i i Fig. 6) are geerated i real time by table iterpolatios, which give the sie ad the cosie of the output agle t for i ad i respectively. The vector product betwee the referece iput sigals ad VCO outputs (v + j v ad i + j i respectively) is calculated as the sum of products of the idividual compoets. The resultig quatity ca be also iterpreted as the real power, accordig to Akagi s pq theory ([7],[8]), ad it is take as the sigal iput to the PI-Cotroller. For this reaso, this implemetatio is ofte called p-pll. Alteratively, sigals i ad i could be exchaged, yieldig the socalled q-pll. Differetly from eq. (3), it ca be show that the output of the VP-PD i this p-pll implemetatio, which was called p 3, ca also be writte as: p 3 = 3.V.I.cos( - ), (8) for PLL i the locked state at the ceter frequecy, uder balaced coditios. V ad I correspod to the three-phase system s phase voltage ad phase curret, respectively. Hece, the VCO outputs (i + j i ) must be leadig by 9 the referece iput sigal (v + jv ) i steady state, to produce ull iput to the PI filter. This fudametal characteristic should be remided whe this PLL circuit is applied. IV. EXPERIMENTAL RESULTS The experimetal results obtaied by the PLL algorithm, which has bee implemeted with fixed poit arithmetic i the TMS3LF47 DSP, were compared with simulatios carried out i MATLAB. The iput sigals used i the simulatios were the same oes acquired durig the experimetal tests. The samplig frequecy used i the simulatios was also khz. v ab v bc A. Ubalaced iput sigals I this case, i all experimetal tests, as well as i the simulatios, the PI output values were limited to a miimum of.5 ad a maximum of.5, sice the ceter frequecy was ormalized to p.u. Six test cases were accomplished with differet iitial coditio at the PI s output ad differet iput sigals (balaced ad with egative-sequece ubalace). I the first test case, it was admitted balaced iput sigals ad the iitial value for the PI s output equal to oe. I the secod test, it was admitted ubalaced iput sigals by.5% of egative-sequece compoet at the fudametal frequecy, ad the iitial value for the PI s output equal to v X - Trasf. v X Fig. 4 ad simulatio results for sigal balaced ad the iitial value for the PI s output equal to : PI output i p 3 PI Cotroller cos(t) Fig. 5 ad simulatio results for sigal ubalaced ad the iitial value for the PI s output equal to : PI output t s Fig. 6 Block-diagram represetatio of the implemeted algorithm 94

4 B. Sub-harmoics Four tests have bee carried out to verify the perform Fig. 7 ad simulatio results for sigal balaced ad the iitial value for the PI s output equal to.5: PI output Fig. 8 ad simulatio results for sigal ubalaced ad the iitial value for the PI s output equal to.5: PI output oe. The results of these cases are show i Fig. 4 ad Fig. 5 respectively, where the dyamic of PLL circuit ca be see. I both cases, where the PI s output was iitialized to., the PLL circuit locks to the desired frequecy i approximately 7ms. I the secod test, the output frequecy presets ripple smaller tha two percet. The third test case comprises balaced iput sigals ad the PI iitial value is equal to.5. The results are show i Fig. 7. I the ext test case, it was admitted iput sigals ubalaced by.5% of egative-sequece compoet at the fudametal frequecy ad the iitial value for the PI s output equal to.5. The results of this test case are show i Fig. 8. I these cases, where the PI s output is iitialized to.5, the PLL takes more time to lock i to the desired frequecy (~5ms for balaced sigals ad ~43ms for ubalaced sigals) tha the previous oes. The ripple preset i the output frequecy i the fourth test is smaller tha three percet. The fifth test case has balaced iput sigals ad the iitial value for the PI s output equal to.5. The results are show i Fig. 9. I the sixth test, it was admitted iput sigals ubalaced by.5% of egative-sequece compoet at the fudametal frequecy ad the iitial value for the Fig. 9 ad simulatio results for sigal balaced ad the iitial value for the PI s output equal to.5: PI output PI s output equal to.5. The results of this test are show i Fig.. For the PI s output iitialized to.5, the time that the PLL takes to lock i desired frequecy is approximated the same oes as i the case where the PI s output is iitialized to.5. The ripple of frequecy preset i the sixth test is smaller tha two percet. I all of the above tests, the PLL algorithm has successfully locked to the desired frequecy, eve i the presece of strog egative-sequece ubalaces i the iput voltages. With more tha % of egative-sequece ubalace, the frequecy jitter caused by this same ubalace remais aroud %. Based o the results obtaied from the tests preseted above, it ca be said that the implemeted PLL algorithm is very robust agaist egative-sequece ubalaces comig from the three-phase iput sigals, up to a amout of.5% at least. The resultig VCO output sigal will the always lock to the positive-sequece compoet of the iput sigals, thus idicatig that this very algorithm ca be used as a positive-sequece voltage or curret detector. Fig. ad simulatio results for sigal ubalaced ad the iitial value for the PI s output equal to.5: PI output 95

5 Fig. ad simulatio results for 7% of sub-harmoic disturbace at Hz ad the iitial value for the PI s output equal to zero: PI output Fig. 3 ad simulatio results for % of sub-harmoic disturbace at Hz ad the iitial value for the PI s output equal to zero: PI output Fig. ad simulatio results for 7% of sub-harmoic disturbace at Hz ad the PI s output is limited: PI output Fig. 4 ad simulatio results for % of sub-harmoic disturbace at Hz ad the PI s output is limited: PI output ace of the PLL cotrol software i the presece of subharmoic oscillatios at very low frequecy (Hz), uder differet iitial coditios ad limitig or ot the PI cotroller s output. The results of these tests are show from Fig. to Fig. 4, which exhibit good agreemet betwee simulated ad experimetal results. Fig. ad Fig. show the results of the tests, which have used 7% of sub-harmoic disturbace at Hz. I Fig., the system starts from zero iitial coditio ad the PI s output is ot limited. I Fig., the PI s output is limited ad the iitial value is withi the limits. ad experimets show that the PLL locks to the desired frequecy i both cases, but the settlig time is very log (more tha.5s) whe the PI output is ot limited. For the test results preseted i Fig. 3 ad Fig. 4, the sub-harmoic disturbace was % at Hz. I Fig. 3 the iitial value for PI s output is zero ad the output is ot limited. I this case, the PLL fails to lock. This problem ca be corrected if limits are itroduced to the PI s output, as show i Fig. 4. The PLL output frequecy the locks to the desired frequecy i approximately te cycles of the iput frequecy, with oly a few percet of frequecy ripple. C. Harmoics This test was accomplished to verify the performace of the PLL circuit i the presece of harmoic distortio. I this case, the lie voltage sigals were acquired from a bus where a three-phase, full-bridge rectifier was also coected. These sigals were cotamiated with approximately % of harmoic of fifth order ad 5% of harmoic of eleveth order. The THD is of approximately 5% ad the waveform of this voltage ca also be see i Fig. 6, with the label v ab,ref. Fig. 5 shows the simulatio ad the experimetal results obtaied from the test described above. I this case, the PI s output is limited ad the iitial value for its output is equal to.. The experimetal results agree very well to the simulatio results. 96

6 v ab,ref v ab,ge Fig. 5 ad simulatio results for harmoic disturbace ad the PI s output is limited: PI output The applicatio of this PLL circuit i the cotrol of power electroics equipmet has prove to be very effective i this test, with the correct switchig of a PWM iverter supplyig eergy to a resistive load. I Fig. 6, the distorted sigal labeled v ab,ref is the referece sigal for the PLL circuit ad the voltage labeled v ab,ge is the filtered lie voltage geerated by PWM switchig of the iverter. The PLL circuit has successfully locked, ad the iverter is sychroized with the sigal of fudametal compoet of lie voltage. V. CONCLUSIONS This paper describes a robust sychroizig PLL circuit, which has bee aalyzed ad implemet by software. The experimetal results obtaied from several tests have bee compared to MATLAB simulatios, showig good agreemet. Some aspects related to the system s ability to maitai sychroism i the presece of sub-harmoics, harmoics ad egative-sequece ubalaces have bee ivestigated, ad the implemeted algorithm revealed to be robust eve uder such circumstaces. Whe the iput sigals are cotamiated with egative-sequece compoets, the implemeted PLL is able to produce output sigals locked to the positive sequece compoets oly. This makes this PLL circuit suitable for positive-sequece detectio of voltages ad/or currets i power electroics equipmet. Related applicatios will be discussed i future work. VI. REFERENCES [] L.N.Arruda, S.M.Silva ad B.J.C.Filho, PLL structure for utility coected systems, Coferece Record of the Thirty-Sixth IEEE- IAS Aual Meetig (), Volume 4, Page(s): [] C.Zha, C.Fitzer, V.K.Ramachadaramurthy, A.Arulampalam, M.Bares ad N.Jekis, Software phase-locked loop applied to dyamic voltage restore (DVR), IEEE Power Egieerig Society Witer Meetig,, Volume 3, Page(s): [3] S.Chug, A phase trackig system for three phase utility iterface iverters, IEEE Trasactios o Power Electroics, Volume 5 Issue 3, May Page(s): [4] R.E.Best, Phase Locked Loops Theory, Desig ad Applicatios, ISBN , McGraw-Hill, 984. Fig. 6 results for harmoic disturbace of the switchig of a iverter PWM [5] V.Kaura ad V.Blasko, Operatio of a phase locked loop system uder distorted utility coditios, IEEE Trasactios o Idustry Applicatios, Volume 33 Issue, Ja.-Feb. 997 Page(s): [6] K.J. Åström ad B. Wittemark, Computer-Cotrolled Systems Theory ad Desig, 3 rd Editio, ISBN , Pretice- Hall, 984 [7] H. Akagi, Y. Kaagawa e A. Nabae, Istataeous Reactive Power Compesator Comprisig Switchig Devices Without Eergy Storage Compoets, IEEE Tras. Idustry Applicatios, vol. IA-, May-Jue, 984. [8] E. H. Wataabe, R. M. Stepha e M. Aredes, New Cocepts of Istataeous Active ad Reactive Powers i Electrical Systems with Geeric Loads, IEEE Tras. Power Delivery, vol. 8, No., April 993, pp VII. BIOGRAPHIES Diogo Rodrigues da Costa Juior was bor i Rio de Jaeiro State, Brazil, o Jue, 98. He received the B.Sc. degree from Federal Uiversity of Rio de Jaeiro, i 3. He is ivolved i research projects of the Power Electroic Laboratory from the COPPE/UFRJ, sice. He is erolled i M.Sc. at COPPE/UFRJ i Power Electroics ad, with Dr. Rolim ad Dr. Aredes, is developig the digital cotrol of a prototype of a Dyamic Voltage Restorer. Luís Guilherme Barbosa Rolim was bor i Niterói, Brazil, i 966. He received the B.S. ad M.S. degrees from the Federal Uiversity of Rio de Jaeiro (UFRJ), Rio de Jaeiro, Brazil, ad the Dr.-Ig. degree from the Techical Uiversity Berli, Berli, Germay, i 989, 993, ad 997, respectively, all i electrical egieerig. Sice 99, he has bee a Faculty Member of the Electrical Egieerig Departmet, Escola Politécica, UFRJ, where he teaches ad coducts research o power electroics, drives, ad microprocessor cotrol. He is a member of the Power Electroics Research Group at COPPE/UFRJ ad has authored more tha papers published i brazilia ad iteratioal coferece proceedigs ad techical jourals. Maurício Aredes (S 94, M 97) was bor i São Paulo State, Brazil, o August 4, 96. He received the B.Sc. degree from Flumiese Federal Uiversity, Rio de Jaeiro State i 984, the M.Sc. degree i Electrical Egieerig from Federal Uiversity of Rio de Jaeiro i 99, ad the Dr.-Ig. Degree (maga cum laude) from Techische Uiversität Berli i 996. From 985 to 988 he worked at the Itaipu HVDC Trasmissio System ad from 988 to 99 i the SCADA Project of Itaipu Power Plat. From 996 to 997 he worked withi CEPEL Cetro de Pesquisas de Eergia Elétrica, Rio de Jaeiro, as R&D Egieer. I 997, he became a Associate Professor at the Federal Uiversity of Rio de Jaeiro, where he teaches Power Electroics. His mai research area icludes HVDC ad FACTS systems, active filters, Custom Power ad Power Quality Issues. Dr. Aredes is a member of the Brazilia Society for Automatic Cotrol ad the Brazilia Power Electroics Society. 97