Multilevel Inverter with Dual Reference Modulation Technique for Grid-Connected PV System

Transcription

1 Multilevel Iverter with Dual Referece Modulatio Techique f Grid-Coected PV System N. A. Rahim, Sei Member, IEEE, J. Selvaraj Abstract This paper presets a sigle-phase five-level gridcoected PV iverter with a ovel dual referece modulatio techique. Two referece sigals idetical to each other with a offset equivalet to the amplitude of the triagular carrier sigal were used to geerate PWM sigals. The iverter cosists of a full-bridge iverter ad a auxiliary circuit comprisig four diodes ad a switch. The iverter produces output voltage i five levels: zero, +/V dc, V dc, -/V dc ad V dc. A digital PI curret cotrol algithm is implemeted i DSP TMS3F8 to keep the curret ijected ito the grid siusoidal ad to have high dyamic perfmace with low THD. The validity of the proposed iverter is verified through simulatio ad implemeted i a prototype. The experimetal results are compared with covetioal sigle-phase three-level gridcoected PWM iverter i terms of THD. Dual referece modulatio techique is itroduced to geerate switchig sigals f the switches ad to produce five output voltage levels: zero, +/V dc, V dc, -/V dc ad V dc (assumig V dc is the supply voltage). The modulatig techique uses two referece sigals istead of oe to geerate PWM sigals f the switches. Both the referece sigals V ref ad V ref are idetical to each other except f a offset value equivalet to the amplitude of the carrier sigal V carrier as show i Fig.. Auxiliary Circuit Full-Bridge Iverter Idex Terms PWM iverter, photovoltaic (PV), PI curret cotrol, DSP TMS3F8, grid-coected, multi-strig. A I. INTRODUCTION s the wld is cocered with fossil fuel exhaustio ad evirometal problems caused by the covetioal power geeratio, reewable eergy sources particularly solar eergy ad wid eergy has become very popular ad demadig. PV sources are used today i may applicatios as they have the advatages of beig maiteace ad pollutio free []. Much of the wld s eergy eeds ca be supplied directly by solar power. Solar power techologies ca be divided ito two groups; oe uses the su to geerate heat ad is called solar thermal techologies, ad the other coverts the su s radiatio directly ito electricity through photoelectric effect. Solar thermal techologies iclude solar cocetrat power systems, flat plate solar collects, ad passive solar heatig. Photoelectric effect uses solar cells called photovoltaic (PV). This paper presets a sigle-phase five-level iverter with a trasfmer f grid-coected applicatio. A five-level cofiguratio is used because it offers great advatages such as improved output wavefms, smaller filter size, lower EMI ad lower THD compared with covetioal three-level PWM iverter []-[8]. To geerate output voltage i five-levels, fullbridge iverter cofiguratio together with a auxiliary circuit as show i Fig. were used. Fig.. Full-bridge iverter cofiguratio together with a auxiliary circuit V carrier -V carrier V ref V ref Fig.. Carrier ad referece sigals II. FIVE-LEVEL INVERTER TOPOLOGY The proposed sigle-phase five-level iverter topology is show i Fig. 3. It cosists of a dc-dc boost coverter coected to two capacits i series, a auxiliary circuit, a full-bridge iverter, a step-up trasfmer ad utility grid. I this paper, the iverter is desiged to wk as a gridcoected system; therefe utility grid is used istead of load. The dc-dc boost coverters are used to track the /9/$5. 9 IEEE

2 maximum power poit (MPP) of the solar arrays as well as to step-up the iverter output voltage V iv to be me tha of the grid voltage V g to esure power flow from the PV arrays ito the grid. As a step-up trasfmer with a ratio of : is used, V iv should be () V V > g iv V V > g iv () A filterig iductace L f is used to filter the curret ijected ito the grid. The ijected curret must be siusoidal with low harmoic disttio [8]. PV Strig DC- DC Boost Coverter L D S DC Bus Auxiliary Circuit Full- Bridge Iverter Vpv/ C Vpv/ C Fig. 3. Sigle-phase five-level iverter topology D S D 3 III. PWM MODULATION AND OPERATIONAL PRINCIPLE Modulatio idex M a f five-level PWM iverter is give as [9] Am M a = (3) A c where A c is the peak-to-peak value of carrier ad A m is the peak value of voltage referece V ref. Sice i this wk two referece sigals idetical to each other are used, equatio (3) ca be expressed i terms of amplitude of carrier sigal V c by replacig A c with V c. ad A = V = V = V. V c m D 4 D5 ref S 3 S 4 ref ref M = (4) V L f I g S 5 S6 ref Viv : Vg V ( ) = A + (A cos θ + B si θ ) o θ = If there are P pulses per quarter period, ad it is a odd umber, the coefficiets B ad A o would be a zero where is a eve umber. Therefe, the equatio (5) ca be rewritte as V o =,3... ( θ) = A cos θ P 4 it ( i/) [ ( ) si( α m+ i )] m= i= (5) (6) Vdc A = (7) π where m is a pulse umber. The Fourier series coefficiets of the covetioal sigle-phase full-bridge iverter by siusoidal PWM is give as P 4Vdc m A = si α (8) π = m [( ) ( )] The mai objective of desigig a grid-coected PV iverter is to iject siusoidal curret ito the utility grid. I der to geerate siusoidal curret with low harmoic disttio, a siusoidal PWM is used sice it is oe of the most effective methods. Siusoidal PWM is obtaied by comparig a high-frequecy carrier with a low-frequecy siusoid, which is the modulatig sigal referece sigal. The carrier has a costat period; therefe the switches have costat switchig frequecy. The switchig istat is determied from the crossig of the carrier ad the modulatig sigal. I this wk, dual referece modulatio techique is icpated ito the siusoidal PWM techique to produce PWM switchig sigals f the full-bridge iverter switches ad auxiliary switch. Two referece sigals V ref ad V ref will take turs to be compared with the carrier sigal at a time. If V ref exceeds the peak amplitude of the carrier sigal V carrier, V ref will be compared with the carrier sigal util it reaches. At this poit owards, V ref takes over the compariso process util it exceeds V carrier. This will lead to a switchig patter as show i Fig. 4. Switches S -S 4 will be switchig at the rate of the carrier sigal frequecy while S 5 ad S 6 will operate at a frequecy equivalet to the fudametal frequecy. Table illustrates the level of V iv durig S -S 6 switch o ad off. m If M>, higher harmoics i the phase wavefm is obtaied. Therefe, M is maitaied betwee ad. If the amplitude of the referece sigal is icreased higher tha the amplitude of the carrier sigal, i.e. M>, this will lead to overmodulatio. Large values of M i siusoidal PWM techiques lead to full overmodulatio []. From the PWM modulatio, the aalysis of harmoic compoets i the proposed iverter ca be prefmed. The output voltage produced by compariso of the two referece sigals ad the carrier sigal ca be expressed as [3]

3 3 S S S 3 S 4 S 5 V ref V ref icreases, variable m also icreases. Therefe it ca be cocluded that, m irradiace of the su The istataeous curret err from the compariso betwee I ref ad I g is fed to a PI cotroller. The itegral term i the PI cotroller improves the trackig by reducig the istataeous err betwee the referece ad the actual curret. The resultig err sigal u which fms the dual referece sigals V ref ad V ref is compared with a triagular carrier sigal ad itersectios are sought to produce PWM sigals f the iverter switches. This is to esure I g to be i phase with grid voltage V g ad always at ear uity power fact. START Fig. 4. Switchig patter f sigle-phase five-level iverter Sese V(k) & I(k) TABLE INVERTER OUTPUT VOLTAGE DURING S -S 6 SWITCH ON AND OFF Yes P(k)-P(k-)= No S S 3 S 4 S 5 S 6 V iv ON OFF OFF OFF ON +V pv / No P(k)-P(k-)> Yes OFF ON OFF OFF ON +V pv OFF OFF (ON) OFF (ON) ON (OFF) ON (OFF) ON OFF OFF ON OFF -V pv / OFF OFF ON ON OFF -V pv Yes Icrease m V(k)-V(k-)> No Decrease m No Icrease m V(k)-V(k-)> Yes Decrease m IV. CONTROL SYSTEM ALGORITHM AND IMPLEMENTATION The proposed iverter is used i a grid-coected PV system. Therefe, a PI curret cotrol scheme is employed to keep the output curret siusoidal ad to have high dyamic perfmace uder rapidly chagig atmospheric coditios ad to maitai the power fact at ear uity. As the irradiace level is icosistet throughout the day, the amout of electric power geerated by the solar modules is always chagig with weather coditios. To overcome this problem, Maximum Power Poit Trackig (MPPT) algithm is used. It tracks the operatig poit of the I-V curve to its maximum value. Therefe, the MPPT algithm will esure maximum power is delivered from the solar modules at ay particular weather coditios. Various MPPT cotrol algithm have bee discussed i detail i []-[3]. I this proposed iverter, Perturb ad Observe (P&O) algithm is used to extract maximum power from the PV modules. The feedback PI curret cotrol seses the curret ijected ito the grid also kow as grid curret I g ad feed back to a comparat which compares it with referece curret I ref. I ref is obtaied by sesig the grid voltage ad covertig it to referece curret ad multiplyig it with variable m. Variable m is derived from the MPPT algithm as illustrated i the flowchart i Fig. 5. The five-level iverter with the cotrol algithm implemeted i DSP TMS3F8 is show i Fig. 6. Sice variable m is depedet o the MPPT algithm, as the irradiace level Fig. 5. MPPT flowchart PV Strig L IPV VPV S X D C C V PV V PV RETURN D D 3 S-S6 Gate Drivers S D 4 D 5 err PPV m Iref + - Ig MPPT X Vg S3 S4 u PI Cotroller L f I g S5 S6 DSP TMS3F8 Fig. 6. Five-level iverter with cotrol algithm implemeted i DSP TMS3F8 V. SIMULATION AND EXPERIMENTAL RESULTS Simulatios were perfmed by usig MATLAB SIMULINK to verify that the proposed iverter ca be practically implemeted i a PV system. It helps to cofirm the PWM switchig strategy f the five-level iverter. The, Vg

4 4 this strategy is implemeted i a real-time eviromet i.e. the DSP to produce PWM switchig sigals f the switches. Fig. 7(a) shows the way the PWM switchig sigals are geerated by usig two referece sigals ad a triagular carrier sigal. The resultig PWM sigals f switches S to S 6 are show i Fig. 7(b)-(f). Note that oe leg of the iverter is operatig at a high switchig rate equivalet to the frequecy of the carrier sigal while the other leg is operatig at the rate of fudametal frequecy (i.e. 5Hz). The switch at the auxiliary circuit S also operates at the rate of the carrier sigal. As metioed earlier, the modulatio idex M will determie the shape of the iverter output voltage V iv ad the grid curret I g. Fig. 8 shows simulatio results of V iv ad I g f differet values of M. Referrig to equatios () ad (), the dc bus voltage is set to V ( > V g /, i this case V g is 4V) to iject curret ito the grid. Fig. 8(a) shows V iv is less tha V g / due to M beig less tha.5. The iverter should ot operate at this coditio because the curret will be ijected from the grid ito the iverter as show i Fig. 8(b). Over modulatio coditio, which happes whe M >., is show i Fig. 8(c). It has a flat top at the peak of the positive ad the egative cycles because both the referece sigals exceed the maximum amplitude of the carrier sigal. This will cause I g to have a flat ptio at the peak of the sie wavefm as show i Fig 8(d). To optimize the power trasferred from the PV arrays to the grid, it is recommeded to operate at.5 M.. V iv ad I g f optimal operatig coditio are show i Fig. 8(e) ad (f). As I g is almost a pure siewave, the total harmoic disttio (THD) ca be reduced compared with that uder other values of M. 4 PWM Sigal Geeratio PWM Switchig Sigal f Switch S 3 V ref.5 Amplitude S.5 - V carrier V ref (a) (b) PWM Switchig Sigal f S3 PWM Switchig Sigal f S4.5.5 S3.5 S (c) (d) PWM Switchig Sigal f S5 PWM Switchig Sigal f S6.5.5 S5.5 S (e) (f) Fig. 7. PWM switchig strategy ad PWM sigal f S -S 6

5 5 5 Iverter Output Voltage (Viv) 3 Grid Curret (Ig) 5 Voltage (V) Curret (A) (a) (b) 5 Iverter Output Voltage (Viv) 5 Grid Curret (Ig) 5 5 Voltage (V) 5-5 Curret (A) (c) Iverter Output Voltage (V) (d) Grid Curret (Ig) Voltage (V) 5-5 Curret (A) (e) (f) Fig. 8. Iverter output voltage (V iv ) ad grid curret (I g ) f differet values of M (a) V iv f M <.5. (b) I g f M <.5. (c) V iv f M >.. (d) I g f M >.. (e) V iv f.5 M.. (f) I g f.5 M.. The simulatio results are verified experimetally by usig a DSP TMS3F8. The proposed iverter is tested with a PV array of 9W peak. Table shows the module s ratigs while Table 3 shows the proposed iverter s specificatios ad its cotroller parameters. To obtai 9W peak power ratig, twelve modules are coected i series which will result i icrease of voltage while the curret maitais. Fig. 9 shows the prototype of the five-level PWM iverter with dual referece modulatio. PWM switchig sigals f the switches geerated by dual referece modulatio techiques is show i Fig.. S -S 6 : IGBT IRG4PC4UDPBF V CE =6, I C =A D -D 5 : RHRP3 V RR =V, I=3A L :.mh L f : 3mH C -C : uf V DC =5V Alumiium Electrolytic K p : K i :.5 Switchig Frequecy : khz Samplig Frequecy : 78kHz TABLE PV MODULE CHARACTERISTICS Model : SIEMENS SP75 Max Power : 75W Sht circuit curret, I SC : 4.8A MPPT curret, I MPPT : 4.4 A Ope Circuit voltage, V OC :.7V MPPT voltage, V MPPT :7.V TABLE 3 PV MULTILEVEL INVERTER SPECIFICATIONS AND CONTROLLER PARAMETERS Fig. 9. Prototype of the five-level iverter with dual referece modulatio techique

6 6 (a) Fig.. Experimet results of Viv ad Ig f Viv > V g / (b) Fig.. Experimet Results of Viv ad Ig f Viv < V g / (c) Fig.. PWM switchig sigals f S-S6, (a) S. (b) S3-S4. (c) S5-S6. Fig. illustrates the experimetal results f Viv ad Ig f coditios Viv > V g / ad M <.. Both the results illustrates that Viv cosists of five levels of output voltage ad Ig has bee filtered to resemble a pure siewave. I the evet of Viv < V g /, curret will be ijected from the grid ito the PV system as show i Fig.. To prove that the proposed five-level iverter has advatages over the covetioal three-level iverter i terms of THD ad power fact, the crespodig measuremets were made o both iverters. FLUKE 43B Power Quality Aalyzer was used f this purpose. The THD ad power fact measuremet f the proposed five-level iverter is show i Fig. 3 ad Fig. 4. The THD f the proposed iverter is 7.5% while the power fact is.99. It is otable that both the grid voltage Vg ad the curret ijected ito the grid Ig are i phase at ear uity power fact. The results from five-level PWM iverter are compared with those from three-level PWM iverter i terms of THD. The oly differece betwee the five-level iverter ad threelevel iverter is the elimiatio of auxiliary circuit ad therefe oly oe dc bus capacit is used. The same curret cotrol techiques were used to cotrol the overall perfmace of the iverter. As show i Fig. 5, the THD measuremet of the three-level iverter is.8%. The result was take at almost the same evirometal coditios to esure Ig to be similar to measuremet made f the five-level

7 7 iverter. By compariso, the THD measuremet f threelevel iverter is much higher whe compared with f fivelevel iverter. This proves that multilevel iverters ca reduce the THD which is a essetial criterio f grid-coected PV systems. Fig. 5. THD result of three-level PV iverter Fig. 3. THD result of five-level PV iverter VI. CONCLUSION This paper preseted a sigle-phase five-level iverter with a dual referece modulatio techique f PV applicatio. The dual referece modulatio techique ivolves comparig two referece sigals idetical to each other except f a offset equivalet to its carrier sigal, with a triagular carrier sigal to geerate PWM switchig sigals f the switches. The circuit topology, cotrol algithm ad operatioal priciple of the proposed iverter were aalyzed i detail. A digital PI curret cotrol algithm is implemeted i DSP TMS3F8 to optimize the perfmace of the iverter. Compariso has bee made betwee the five-level ad threelevel iverter i term of THD. The results show that the THD of the five-level iverter is much less tha that of the covetioal three-level iverter. Furtherme, both the grid voltage ad the grid curret are i phase at ear uity power fact. Fig. 4. Grid Voltage V g ad Grid Curret I g at ear-uity power fact REFERENCES [] N. A. Rahim, Saad Mekhilef, Implemetatio of Three Phase grid Coected Iverter f Photovoltaic Solar Power Geeratio System Proceedigs IEEE. Power Co. Vol, pp , Oct. [] S.. Kouro, J.. Rebolledo, J. Rodriguez, "Reduced Switchig-Frequecy-Modulatio Algithm f High- Power Multilevel Iverters," IEEE Tras. o Idustrial Electroics, vol. 54, o. 5, pp , Oct. 7. [3] S. J. Park, F. S. Kag, M. H. Lee, C. U. Kim, A New Sigle-Phase Five-Level PWM Iverter Employig a Deadbeat Cotrol Scheme, IEEE Tras. Power Electroics., vol. 8, o. 8, pp , May. 3. [4] L. M. Tolbert, T. G. Habetler, Novel Multilevel Iverter Carrier-Based PWM Method, IEEE Tras. Idustry Applicatio., vol. 35, o.5, pp , Sept/Oct 999. [5] M. Calais, L. J. Ble, V. G. Agelidis, Aalysis of Multicarrier PWM Methods f a Sigle-Phase Five-Level Iverter, Power Electroics Specialists Coferece,

8 . PESC. IEEE 3th Aual Volume 3, 7- Jue pp: Vol.3,. [6] N. S. Choi, J. G. Cho, G. H. Cho, A Geeral Circuit Topology of Multilevel Iverter, Power Electroics Specialists Coferece, 99. PESC IEEE th Aual Volume, 4-7 Jue 99 pp [7] G. Carrara, S. Gardella, M. Marchesoi, R. Salutari, G. Sciutto, A New Multilevel PWM method: A Theetical Aalysis, IEEE Tras. Power Electroics., vol. 7, o. 3, pp , July. 99. [8] J. Selvaraj, N. A. Rahim, Multilevel Iverter f Grid- Coected PV System Employig Digital PI Cotroller, IEEE Tras. o Idustrial Electroics, i press. [9] V. G. Agelidis, D. M. Baker, W. B. Lawrace, C. V. Nayar, A Multilevel PWM Iverter Topology f Photovoltaic Applicatio, i Proc. IEEE ISIE 97, Guimaraes, Ptugal, 997, pp [] Muhammad H. Rashid, Power electroics: Circuits, Devices, ad Applicatios, 3 rd ed. Pearso Pretice Hall, 4, pp.67. [] Esram T, Chapma P.L, Compariso of Photovoltaic Array Maximum Power Poit Trackig Techiques, IEEE Tras. Eergy Coversio, vol., o., pp , Jue 7. [] Femia N., Petroe G., Spaguolo G., Vitelli M.: Optimizig duty-cycle perturbatio of P&O MPPT techique Power Electroics Specialists Coferece, 4. PESC 4. 4 IEEE 35th Aual Volume 3,- 5 Jue 4 pp Vol.3 [3] Liu X., Lopes L.A.C.: A improved perturbatio ad observatio maximum power poit trackig algithm f PV arrays Power Electroics Specialists Coferece, 4. PESC 4. 4 IEEE 35th Aual Volume 3, -5 Jue 4 pp. 5 - Vol.3 8