Synchronization of the distributed PWM carrier waves for Modular Multilevel Converters

Transcription

1 Sychroizatio of the distributed PWM carrier waves for Modular Multilevel Coverters Paul Da Burlacu, Laszlo Mathe, IEEE Member ad Remus Teodorescu, IEEE Fellow Member Departmet of Eergy Techology, Aalborg Uiversity Abstract The half-bridge modular multilevel coverter has prove itself to be a suitable solutio for HVDC applicatio. I order to achieve high modularity ad fault tolerace, distributed cotrol strategy is oe possible solutio ad is discussed i this paper. Whe distributed cotrol strategy is used, there is a cetral cotroller ad a local cotroller i each sub-module (SM). A problem appears whe implemetig the modulatio usig this type of cotrol strategy; this is the lack of sychroizatio betwee the iteral clocks of the differet submodules cotrollers of the MMC. This will cause a drift betwee the PWM outputs of each sub-module icreasig the total harmoic distortio of the output voltage. This paper presets a solutio to sychroize the PWM outputs of the MMC submodules usig EtherCAT commuicatio protocol focusig o phase shifted PWM modulatio techique. I. INTRODUCTION High Voltage Direct Curret (HVDC) is typically used as a efficiet solutio for trasmittig electric power over log distaces. HVDC techology starts beig ecoomically attractive whe trasmissio distaces of 500 to 800 km are exceeded, depedig o differet factors. For uderwater cables is ecoomically feasible eve for smaller distaces like 50km [1]. Although lie-commutated coverters are still viable for bulk power trasmissio due to their low losses, i order to fulfill future field systems requiremets, self-commutated coverters or voltage source coverters (VSC) are more suitable [2]. Advatages of VSC are active ad reactive power flow cotrol, high reliability i weak or passive systems, flexible ad compact statio layout, asychroous coectio ad black start [3],[4]. The differet VSC discussed i the literature suitable for high power high voltage trasmissio are the two-level VSC, diode-clamped multi-level coverter, flyig capacitor multilevel coverter ad cascaded H-bridge multilevel coverter. As a alterative to the above metioed coverter types a ew topology has bee proposed, the Modular Multilevel Coverter (MMC). The MMC is composed of a umber of several submodules coected i series. A cofiguratio employig half bridges i each sub-module is show i Fig. 1. I this solutio each sub-module of the MMC has two termials ad cosists of two cotrolled switchig compoets, S1-, each of them equipped with a diode coected i atiparallel, D1-D2 ad a storage capacitor, oted with C [5]. Two protectio devices ca also be icluded i the desig, a relay, R1, paralleled with a Triac, T1. I case the sub-module suffers ay damage these protectio devices will be used to by-pass the sub-module esurig the cotiuous flow of the curret. The Triac T1 is used because of the ability to switch idepedetly of the curret directio ad its fast reactio times. The relay is slower tha the Triac; however it has lower losses whe coductig. I case the sub-module eeds to be bypassed the Triac will be tured o first because of its faster respose. Afterwards, whe the relay is o, the Triac is tured off agai ad the curret will flow oly though the relay miimizig the losses. The termial voltage of the sub-module,, ca be equal to 0 or Vc depedig o the switchig devices states. The value of V C will deped o the umber of sub-modules per phase, N, ad the DC-lik voltage, V C = 2V dc / N. The basic operatio of a sub-module is resumed i TABLE I. Whe talkig about the whole system, each of the phases of a MMC is also called leg. At the same time a leg has two arms, the upper arm ad the lower arm, both composed by sub-modules, where = N / 2. The umber of differet voltage levels at the output of a MMC is equal with N + 1[6]. Curret directio I sm > 0 I sm < 0 S1 state R1 I sm T1 TABLE I SUB-MODULE OPERATION STATES state S1 value D1 D2 Capacitor status C V C Fig. 1. Sketch of the MMC half bridge sub-module circuit. Coductig Device ON OFF V C Chargig D1 OFF ON 0 By-passed ON OFF V C Dischargig S1 OFF ON 0 By-passed D2

2 As all the sub-modules are coected i series, the MMC is easy to adapt to differet power ad voltage levels. I Fig. 2 a three phase MMC with N = 2 sub-modules i each phase is show. The umber of modules is variable, for example Siemes preseted MMC coverter topologies where more tha 200 sub-modules per arm are used [7], [8]. The two iductors are istalled o each arm, with the purpose to limit the circulatig curret ad curret rise i case of a DClik short circuit fault. As the umber of sub-modules is icreased the blockig voltage ratig of the switchig compoets is reduced ad the THD of the output voltage waveform is also reduced. This traslates i a reductio i the size of the ecessary filters [9]. The MMC has proved to be superior to its competitors for HVDC applicatios presetig the followig mai advatages: o eed to coect semicoductor switches i series [10], o eed to employ a bulky capacitor at DC termials, high modularity ca be achieved, redudat modules ca be iserted icreasig this way the reliability, easily scalability to differet power ad voltage levels, low total harmoic distortio, low switchig frequecies which traslates i small filters ad low switchig losses [8]. I this paper the MMC with a focus o distributed cotrol ad a solutio for PWM sychroizatio is preseted. The outlie of this paper is as follows: i sectio II cetralized ad distributed cotrol topologies for MMC are preseted. I sectio III phase shifted PWM ad sychroizatio issues are described. EtherCAT protocol ad Distributed Clocks systems used for distributed cotrol are preseted i sectio IV. Test setup descriptio ad implemetatio method are i sectio V. Results ad coclusios are preseted i sectios VI ad VII respectively. II. MMC CONTROL TOPOLOGIES For HVDC applicatios the umber of sub-modules of the MMC ca go up to a large umber makig the cotrol a very complex task [9]. The cotrol to be carried out for the MMC V dc /2 V dc /2 i dc i p Phase A Vau #2 Vau #2 Vau #2 Val #2 Val #2 Val #2 i i i Phase C Phase B i a i b i c Grid ca be divided ito five differet categories: 1) coverter output curret cotrol i order to cotrol the active ad reactive power, 2) DC lik voltage cotrol, 3) the submodules capacitors voltage levels cotrol, 4) circulatig curret cotrol, 5) the cotrol i case of faults. Takig this ito accout, two differet cotrol strategies have bee discussed i the literature, cetralized cotrol ad distributed cotrol [4]. I case of cetralized cotrol oly oe sigle cotroller is carryig out all the cotrol operatios ad eeded processig. The cotroller eeds to be very powerful give that the processig requiremets are itese ad also a large amout of sigals eed to be available [11], [4]. A simplified diagram of cetralized cotrol applied to a sigle phase MMC with eight sub-modules is show i Fig. 3. As a example of the cotrol sigals eeded, PWM output sigal ad capacitor voltage measuremet iput sigal for each sub-module are show i the figure. This approach hiders the modularizatio ad origiates reliability issues [4]. Whe distributed cotrol cofiguratio is used, each submodule has a idividual cotroller alog with a cetral cotroller. A commuicatio etwork must be established betwee the cetral ad the sub-module cotrollers. The processig load is distributed betwee the cetral ad the idividual cotrollers of each sub-module decreasig the umber of sigal wires ad hece, icreasig the reliability ad the modularizatio of the system [4]. Besides the metioed advatages, costs are icreased whe this cotrol topology is used because of the additioal commuicatio hardware required [4]. For the distributed topology the cetral cotroller will take care of the high level cotrol, which icludes the curret cotrol, DC lik cotrol ad averagig cotrol. The averagig SUB-MODULE 1 SUB-MODULE 2 SUB-MODULE 3 SUB-MODULE 4 SUB-MODULE 5 SUB-MODULE 6 SUB-MODULE 7 SUB-MODULE 8 PWM1 PWM2 PWM3 PWM4 PWM5 PWM6 PWM7 PWM8 Vc5 Vc4 Vc6 Vc7 Vc3 Vc8 Vc1 Vc2 Cetral Cotroller *Curret cotrol *DC lik cotrol *Averagig cotrol *Balacig cotrol *Fault cotrol Fig. 2. Three phase modular multilevel coverter. Fig. 3. Block diagram of the MMC cetralized cotrol strategy.

3 cotrol performs the circulatig curret cotrol ad the overall capacitor voltage level cotrol [12], [9], [11]. Each sub-module will carry out the PWM computatios alog to the fault cotrol ad a idividual capacitor voltage level cotrol, also called balacig cotrol. Furthermore, the measuremets of curret ad voltage will also be performed locally i each sub-module [9]. A geeral diagram with the distributed cotrol structure is show i Fig. 4. Due to the higher modularity ad reliability, the distributed topology has bee chose whe buildig the small scale MMC used for the experimetal tests preseted i this paper. The real time commuicatio protocol chose for its good performaces, sychroizatio ad fault tolerace capabilities is EtherCAT. III. MMC MODULATION AND SYNCHRONIZATION ISSUES Several PWM techiques have bee proposed i the literature for MMC. These techiques are based o the compariso of a referece sigal with differet triagular carrier sigals ad are also kow as multi-carrier PWM techiques. The most commo multi-carrier PWM techiques are Phase Dispositio (PD), Phase Oppositio Dispositio (POD), Alterative Phase Oppositio Dispositio (APOD) ad Phase Shifted (PS) [4], [13]. I this paper the PS techique is used due to its easy usage for distributed cotrol ad its lower harmoic cotet geerated i the output voltage [4]. The phase-shifted PWM techique uses as may carrier sigals as umber of sub-modules, oted with N. Betwee all of the carriers a phase shift of α=360 /N, where 360 correspods to the period of the carrier sigals, should be maitaied. Half of the carriers,, belog to the upper arm ad the other half to the lower arm. The triagular sigals which belog to the same arm will have a phase shift of (2*360 )/N betwee each other. Two referece sigals are also used, oe for the upper arm ad oe for the lower. Both refereces are equal with a phase differece of 180. If the referece sigal is grater that the carrier, S1 is tured ON ad is tured OFF (see Fig. 1). I the same way if the referece sigal is less tha the carrier the S1 is tured OFF ad is tured ON. I Fig. 5 the referece ad carrier sigals, with frequecies of 50HZ fudametal ad 1KHz carrier, are illustrated for a 9 level coverter upper arm. With the distributed cotrol ad phase-shifted PWM practical issues appears at the implemetatio stage, this is a drift or lack of sychroizatio betwee the PWM waves of the differet sub-modules. I distributed cotrol method each of the sub-modules has a local cotroller which will be i charge of performig the modulatio algorithm. The carrier sigal used for PWM is geerated by usig the iteral couter of the cotroller ad will be compared with the referece sigal set by the cetral cotroller. The umber of pulses of the cotroller iteral oscillator will be couted icreasig the couter value. Whe the value correspodig to the carrier period is reached the couter value is set to zero ad the process starts agai. I order to implemet the phase shifted PWM techique, the couters of the differet cotrollers should be perfectly sychroized. They should start the coutig ad cout at the same time. I a real applicatio however, this two coditios R1 I sm T1 SUB-MODULE 1 S1 D1 C V C D2 LOCAL CONTROLLER *Fault cotrol *Balacig cotrol Comuicatio BUS CENTRAL CONTROLLER *Curret cotrol *DC lik cotrol *Averagig cotrol R1 I sm T1 SUB-MODULE N S1 D1 C V C D2 LOCAL CONTROLLER *Fault cotrol *Balacig cotrol Comuicatio BUS Fig. 4. Block diagram of the MMC distributed cotrol strategy. Fig. 5. Carrier waveform ad the puls geeratio fo the SM with PS-PWM techique.

4 will ot be fulfilled without a additioal sychroizatio method, which will be discussed later i the paper. I first place, whe powerig up the cotrollers from the SM there will be differet delays util the couters are started. I secod place, due to maufacturig toleraces, there will be small drifts betwee the iteral oscillators of the cotrollers. These two factors are causig that the coutig will ot occur at the same time. Whe the carrier sigals of each submodule of the MMC are ot sychroized, the output voltage will be distorted icreasig the total harmoic distortio. This pheomeo is ot give i cetralized cotrol topology as oly oe cetral cotroller is used ad hece, the same oscillator gives the time base for the PWM couters. I this paper a method for PWM sychroizatio is proposed. The method is based o the usage of the EtherCAT Distributed Clocks (DC) mechaism. IV. ETHERCAT COMMUNICATION PROTOCOL AND DISTRIBUTED CLOCKS EtherCAT is a ope source protocol based o Etheret which allows full duplex commuicatio ad uses the classical master-slave cofiguratio. Oly the master of the etwork is allowed to sed a EtherCAT frame [14]. Each EtherCAT slave reads ad writes data o the fly. Whe the master seds a telegram it goes to the first slave of the etwork which processes the data ad the seds the telegram further to the ext slave. This process goes o util the last slave of the segmet is reached. The last slave will sed the message back to the master. The telegram will be delayed by the wire propagatio delay ad the processig delay itroduced by the slaves [15]. Distributed Clocks mechaism is a EtherCAT protocol feature used for high precisio clock sychroizatio ad geeratio of sychroous output sigals. Each EtherCAT slave has a iteral clock. Similar to the PWM case commeted above, a differece betwee the slave clocks may exist due to the followig two reasos. First, whe the slaves are tured o the iteral register holdig the curret time is set to zero, however this does ot occur at the same time i all the slaves ad a iitial offset betwee the clocks will be preset. Secod, a small differece betwee the frequecies of the iteral oscillators of the slaves will always exist. Oe of the clocks, usually the clock of the first slave, is used as a referece. The DC algorithm will be i charge of sychroizig the EtherCAT master ad slaves clocks with the referece clock. This will be doe by calculatig ad compesatig the propagatio delay betwee each slave, the iitial time offset ad the local clock drifts [16],[9],[7],[11], [15]. Geeratio of sychroized output sigals is also possible due to DC mechaism. As the iteral clocks are sychroized, all the slaves i a EtherCAT etwork will be able to geerate a sychroized output with a jitter dow to aosecods. This is a key feature for the sychroizatio of the MMC modules as discussed i the ext sectio [14]. Other importat EtherCAT feature is that it allows commuicatio redudacy i the etwork usig a rig cofiguratio as show i Fig. 7. Each EtherCAT device has two ports, A ad B. The master will sed the telegram at the same time through both ports; hece, if the commuicatio cable betwee two sub-modules is broke the MMC ca cotiue ormal operatio as the master is still able to commuicate with all slaves. This provides better reliability to the system. V. TEST SETUP DESCRIPTION AND SYNCHRONIZATION METHOD IMPLEMENTATION For the experimetal tests a small scale MMC with EtherCAT commuicatio bus was built ad it is show i Fig. 6. Followig the distributed cotrol distributio, the BECKHOFF C idustrial PC is used as the cetral cotroller ad master of the etwork. This PC has already built-i EtherCAT hardware with master capabilities ad the differet cofiguratios ad high level cotrol were implemeted i C++ usig TwiCAT 3 software. The EtherCAT slave board used for the sub-modules implemetatio is the BECKHOFF piggyback FB which ca be cotrolled through commuicatio with a exteral cotroller. The piggyback board is the iterface betwee the cetral ad the sub-module local cotrollers. The master commuicates with the piggyback through EtherCAT ad the piggyback will commuicate with the local cotroller through. The sub-module local cotroller is a TMS320F28069 Texas Istrumets. The will perform the low level cotrol ad PWM algorithm. The slave board sigal is also coected to the. is used to sychroize the PWM sigals of the sub-modules. For the sychroizatio test the master alog with four sub-modules were used. A diagram with the geeral cofiguratio is showed i Fig. 7. The PWM sychroizatio method is based o EtherCAT slave capability of geeratig a cyclic sychroizatio output sigal. Each slave will geerate this sigal though the Fig. 6. Picture of the MMC test setup sub-modules.

5 output lie. The lie is coected to the local. The differece betwee the sigals geerated will be of a few s. This has bee tested obtaiig values i the rage of 5 to 15 s. will be ormally at high level but whe a cycle period is completed it will geerate a small duratio low pulse. Whe the sychroizatio output goes from high to a low state the will detect the fallig edge geeratig a exteral iterrupt. Whe the exteral iterrupt is detected the PWM couter register of the is set to 0. For the tests the system was cofigured as follows. The master was set ito cyclic mode with a cycle time of 1ms. Hece, the master will sed a ew referece value ad geerate a sychroizatio sigal every millisecod. The is cofigured to geerate a PWM with period of 1ms. The couter is cofigured i up-cout mode. The referece value set by the master is loaded ito a register. Whe the couter is equal to zero the output is set HIGH, whe the couter is equal or greater tha the referece value the output is set LOW. VI. MEASUREMENT RESULTS I first place, some captures made whe o sychroizatio techique is applied are preseted. All submodules have the same cofiguratio ad the same software is ruig i them. Ideally, all the PWM sigals geerated by the sub-modules should be i phase but as ca be see i Fig. 8, 9 ad 10 a drift exists due to the effects metioed before. The phase differece betwee the sigals is radom ad varies i time. I secod place some PWM waves measured whe the sychroizatio method described i the previous poit are preseted. The method uses the capability of the microcotroller for software forced sychroizatio. Whe the exteral iterrupt is detected the software forced sychroizatio bit is set to 1 ad hece the value of the iteral couter is set to 0. The measuremet results obtaied whe usig this method are preseted i Fig 11, 12 ad 13. For clarity oly three PWM are show. As it ca be observed the sychroizatio betwee the PWM sigals is successfully obtaied. SUB-MODULE 1 *Fault cotrol *Balacig cotrol SUB-MODULE 2 EtherCAT comuicatio BUS *Fault cotrol *Balacig cotrol *Fault cotrol *Balacig cotrol SUB-MODULE 3 Port A Port B BECKHOFF C *Curret cotrol *DC lik cotrol *Averagig cotrol Fig. 8. PWM output whe o sychroizatio techique is applied. SUB-MODULE 4 *Fault cotrol *Balacig cotrol Fig. 7. Test setup diagram. Fig. 9. PWM output whe o sychroizatio techique is applied.

6 Fig. 13. PWM output whe sychroizatio techique is applied. Fig. 10. PWM output whe o sychroizatio techique is applied. VII. CONCLUSIONS This paper focuses i distributed cotrol topology usig phase shifted PWM algorithm for MMC. A particular problem of this cotrol topology is the lack of sychroizatio betwee the PWM output sigals of each sub-module. This problem is explaied ad a solutio based o EtherCAT Distributed Clocks mechaism is preseted. The measured results obtaied whe the sychroizatio techique is applied are satisfactory. The PWM sigals of the sub-modules are sychroized with a maximum jitter i the rage of 10 to 15us maitaiig the performace of the MMC. ACKNOWLEDGMENTS The work is fiacially supported by The Daish Coucil for Strategic Research ad EUDP through the ACEMU-project. Fig. 11. PWM output whe sychroizatio techique is applied. Fig. 12. PWM output whe sychroizatio techique is applied. REFERENCES [1] SIEMENS. High Voltage Direct Curret Trasmissio - Prove Techology for Power Exchage [Olie]. available: [2] M. Davies, M. Dommaschk, J. Dor, J. Lag, D. Retzma, D. Soeragr, "HVDC PLUS - basics ad priciples of operatio, SIEMENS," [3] K. Friedrich, "Moder HVDC PLUS applicatio of VSC i Modular Multilevel Coverter topology," i Idustrial Electroics (ISIE), 2010 IEEE Iteratioal Symposium o, 2010, pp [4] Youg-Mi Park, Ha-Seog Yoo, Hyu-Wo Lee, Myug-Gil Jug, Se-Hyu Lee, Choog-Dog Lee, Sag-Bi Lee ad Ji-Yoo Yoo, "A Simple ad Reliable PWM Sychroizatio & Phase-Shift Method for Cascaded H-Bridge Multilevel Iverters based o a Stadard Serial Commuicatio Protocol," i Idustry Applicatios Coferece, st IAS Aual Meetig. Coferece Record of the 2006 IEEE, 2006, pp [5] E. Solas, G. Abad, J.A. Barrea, A. Cárcar ad S. Aurteetxea, "Modulatio of Modular Multilevel Coverter for HVDC applicatio," i Power Electroics ad Motio Cotrol Coferece (EPE/PEMC), th Iteratioal, 2010, pp. T2-84-T2-89. [6] E. Solas, G. Abad, J.A. Barrea, A. Cárcar ad S. Aurteetxea, "Modellig, simulatio ad cotrol of Modular Multilevel

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