Analysis, design and implementation of a residential inductive contactless energy transfer system with multiple mobile clamps

Transcription

1 Aalysis, desig ad implemetatio of a residetial iductive cotactless eergy trasfer system with multiple mobile clamps Arash Momeeh 1, Miguel Castilla 1, Mohammad Moradi Ghahderijai 1, Jaume Miret 1, Luis García de Vicuña 1 1 Departmet of Electroic Egieerig, Techical Uiversity of Cataloia, Avda. Víctor Balaguer s/, Vilaova i la Geltrú, Spai arash.momeeh@upc.edu Abstract: This study presets the aalysis, desig ad implemetatio of a simple ad cost-effective residetial iductive cotactless eergy trasfer system with multiple mobile clamps. The topology is based o the cascaded coectio of a buck coverter ad a high-frequecy resoat iverter loaded by several output passive rectifiers. The proposed system icludes a slidig trasformer to supply the mobile loads, leadig to a safe ad flexible locatio of loads. The theoretical aalysis ad desig of the proposed system is based o a mathematical model derived usig the first harmoic approximatio. Selected experimetal results are icluded to verify the system features. I compariso with covetioal topology, the proposed system sigificatly improves efficiecy, complexity ad cost. 1 Itroductio I recet years, cotactless eergy trasfer (CET) systems have bee developed ad ivestigated widely [1 6]. A CET system is resposible to trasfer eergy from the primary source to the loads without physical coectio. By meas of CET system the distributio cables ca be successfully removed. Hece, with the covetioal eergy delivery method, CET systems are more safe, coveiet ad flexible. Several types of CET systems have bee utilised i idustrial ad commercial applicatios. However, the most commoly used oe is iductive cotactless eergy trasfer (ICET) due to its higher efficiecy [7]. The performace of ICET system has bee extesively studied from differet perspectives such as high efficiecy DC/DC coverter [8, 9], magetic shield [10], aalysig ad modellig of the couplig system [11 16], cotrol method ad proper system desig [17 19], ad high-efficiecy couplig [0]. It should be metioed that these achievemets are applicable oly to the sigle clamp system. I fact, there are may usolved problems to apply these methods to a multiple-clamp system. Feedig multiple loads is oe of the iterestig advatages besides elimiatig the last wire. The practical applicatio sceario cosidered here is a log widig loop with slidig trasformers supplyig power for various electroic devices such as wearable devices, mobile phoes, ad laptops. The characteristics of these devices are ormally differet i size, power requiremet ad chargig coditios. Therefore, to fulfil the aforemetioed situatio several challegeable problems should be solved. Over the past few years, several research studies have bee doe to address such a multiple-clamp system from differet perspectives [1 6]. For example to aalyse a multiple-receivers system, a circuit model has bee preseted i [1]. This model is used for high-power low-frequecy applicatios. The cotrol power capability, cotrollability ad sesitivity are discussed i [1]. However, the load variatio aalysis is ot cosidered. I [], a ew model has bee preseted to desig the circuit parameters. Also, a ew solutio has bee provided to compesate the efficiecy drop by frequecy trackig method ad improve the system performace. Nevertheless, this solutio is a complex method for delivery eergy to the multiple-clamp system. I [3], a power distributio method for two-receiver system has bee discussed. However, the mathematic aalysis for multiple umbers of receivers has ot cosidered. The authors [4] discussed the coupled mode theory to explore the effect of multiple loads o power trasfer efficiecy. Refereces [5, 6] also discussed the optimal load aalysis ad effect of couplig betwee multiple clamps, respectively. Despite of umerous publicatios i the field of ICET systems with multiple clamps, few attempts have bee made to brig this techology ito the residetial area where the distributio system is traditioally based o copper cables ad fixed poit sockets [7 3]. I fact, this distributio system is a very good techical solutio to the supply of fixed ad heavy loads such as refrigerators, washig machies, air coditioig etc. However, for residetial mobile loads such as laptops ad mobile phoes, ICET techology will drastically improve flexibility. Note that these kids of loads iclude iteral post-regulators (they are active loads), so that excellet output voltage regulatio is ot strictly required for ICET systems i this particular case [33, 34]. Besides improvig flexibility, ICET systems prevet electrical shocks due to the iclusio of high-frequecy trasformers which provides a electrical isolatio to esure a higher safety system. This feature is sigificat i wet eviromet, where there is always a risk of electrical shocks. The most challegig aspect for residetial ICET system is the lack of a direct commuicatio lie to iform the resoat coverter about the load cosumptio as a cosequece of log primary widig loop ad mobile loads flexibility. Therefore, as a alterative, a system without commuicatio capability must be applied. As a specific task i these applicatios, the iput curret should be cotrolled i a special way to reach a high efficiecy i all the load coditios. I [7], a fixed referece iput curret has bee applied for multiple mobile clamps, resultig i a high efficiecy for full load ad very low efficiecy for low load coditios. To improve the overall efficiecy, the authors [8] preset a adaptive cotrol scheme that automatically updates the value of the referece iput curret makig use oly of local measures. However, a wrog estimatio of referece iput curret could be obtaied as a cosequece of eglectig the effect of magetisig ad leakage iductaces. I additio, cotrol complexity of this system icreases expoetially whe the umber of clamps rises. A commo feature of previous solutios is the use of active rectifiers i the mobile clamps [1 9]. Note that each active clamp requires a cotrol system icludig sesig circuitry, cotrol circuit ad driver. Therefore, the cost of the system will icrease for the high umber of clamps compared to the topology based o passive rectifiers. As a alterative solutio, the authors [30]

2 Fig. 1 Covetioal approach to supply the ICET system with multiple-receivers (a) Diagram of ICET system with slidig trasformer ad various mobile loads, (b) Schematic of the covetioal DC/DC coverter with multiple mobile clamps preset a simple ad cost-effective topology to supply ICET system with multiple clamps without the eed for a active rectifier. The proposed system operates based o usig frequecy modulatio techique, resultig i fixed output voltage i several load coditios. However, the voltage gai is highly depeds o the resoat elemets values. Therefore, a little chage o the resoat elemets (due to the temperature or exteral effects) has a big impact o the voltage gai. I [31], a ew cost-effective topology to supply a high-power sigle clamp system has bee preseted. The proposed topology has a fix output voltage idepedet to the load coditio. However, the complex mechaism of the clamp coectio ad expesive cotrol system has bee cosidered for this topology. I [3], this topology was exteded ad simplified to supply multiple clamps. However, the theoretical aalysis ad the experimetal validatio of this iterestig topology were ot preseted. The purpose of this paper is to preset the aalysis, desig ad implemetatio of a simple ad cost-effective techique to supply the residetial ICET system with multiple mobile loads. The proposed topology is based o the cascaded coectio of a buck coverter operatig as a costat curret source ad a highfrequecy resoat iverter (RI) operatig i closed loop with oly feedforward term ad loaded by passive rectifiers. The most promisig features of the proposed topology is that the output voltages are early costat for all the load coditios eve usig passive rectifiers at the output side of the proposed ICET system. The drawback of this cofiguratio is the poor trasiet respose. For this reaso, the topology is well suited to supply active DC loads with iteral post-regulators such as laptops, mobile phoes ad other loads takig advatage of a flexible locatio. The aalysis of the proposed topology is carried out with a mathematical model based o the first harmoic approximatio. By usig the derived model, a systematic desig procedure is itroduced to get costat output voltages i all the loads ad also for differet load coditios. Moreover, to validate the performace of the proposed system, selected experimetal results are compared to those obtaied from the covetioal topology. The mai cotributios of this paper are: (i) a simple, efficiet ad cost-effective topology to supply residetial loads with multiple clamps, (ii) a mathematical model derived by usig the first harmoic approximatio which icludes the effect of magetisig ad leakage iductaces ad (iii) a systematic desig procedure for the resoat compoets. This paper is structured as follows: Sectio describes the covetioal topology to supply multiple mobile clamps. Sectio 3 presets the proposed topology ad describes its priciple of operatio. Sectio 4 derives the mathematical model of the proposed system. Sectio 5 itroduces the desig procedure of the proposed system with a umerical example. The predicted theoretical results are verified experimetally i Sectio 6 with measuremets obtaied from a experimetal setup. A compariso with the covetioal topology is also icluded. Fially, the paper is cocluded i Sectio 7 with remarks regardig the results. Covetioal residetial ICET system with multiple mobile clamps This sectio discusses the cofiguratio, cotrol ad efficiecy issues of the covetioal residetial ICET topology to supply a multiple mobile clamp system. Note that, there are several topologies such as series, parallel ad series-parallel resoat coverter for dual active bridge system. However, for this specific applicatio series resoat coverter has bee selected due to higher efficiecy ad good performace [17, 7 9]. Moreover, i series resoat topology, the primary leakage iductace of the slidig trasformers could be absorbed by the large discrete series resoat iductace. So, the effect of these elemets could be reduced i the case of high umber of clamps ad variatio of trasformer air gap. A diagram of the covetioal topology with slidig trasformer ad various mobile loads is show i Fig. 1a. This system cosists of a RI, a primary widig loop, secodary side trasformer ad various mobile clamps. The RI is resposible to geerate a high-frequecy AC voltage to supply the mobile loads through the log primary widig loop of the slidig trasformer. This feature offers the possibility to costruct log ICET systems for mobile clamps. Fig. 1b illustrates the complete electrical represetatio of the covetioal residetial ICET topology. It cosists of a series resoat etwork coected i series with the primary side of slidig trasformers excited by the full-bridge RI. The secodary side of each clamp is formed by a active full-bridge rectifier ad a capacitive filter. The magetisig iductaces of the highfrequecy trasformers are modelled by parallel equivalet iductors (L m1,, L m ). Note that i the primary side, the (small) leakage iductace of the trasformer is absorbed by the large discrete iductace (L r ). The secodary side leakage iductace (L s1 ) is icluded i the schematic. This covetioal topology exhibits excellet output voltage regulatio ad trasiet respose. Also, it has several drawbacks which will be preseted as follows. I this applicatio, as a cosequece of the log primary widig loop ad the mobile load flexibility, the iformatio about the load cosumptio is ot available i the primary side of the full-bridge iverter. This problem ca be solved by usig a wireless commuicatio system. However, this desig will drastically icrease the system cost due to the high badwidth commuicatio required to sed output side data to the primary side cotroller. Therefore, the desig ad implemetatio of the cotrol system that provides a high efficiecy ca be cosidered as a complex tred. O the oe had, several approaches ca be adopted to regulate the iverter curret icludig costat ad variable i ref [7, 8]. By usig costat i ref, high efficiecy ca be oly reached at full load coditios [7]. With variable i ref, the efficiecy is improved for low load coditios, but at the expese of icreasig the complexity of the curret cotrol loop. I [8], the curret referece is olie updated by estimatig the load cosumptio through idirect measures. However, the estimatio depeds o a model that does ot cosider magetisig ad leakage iductaces, thus providig poor results i some circumstaces. These parasitic elemets are importat i this applicatio ad they will be specially take ito cosideratio i this paper. O the other had, the output voltages i the covetioal topology deped o the load

3 Fig. Schematic of the proposed ICET system with multiple mobile clamps Fig. 3 Cotrol diagram of the proposed system (a) Buck coverter curret cotrol, (b) RI cotrol ad (c) Output waveforms of the RI coditios, so that a separated cotrol system is required for each clamp. Although, the output voltage ca be correctly regulated, the cost of the system is drastically icreased i the case of high umber of clamps (because of the sesig circuits, cotrol system ad driver eeded by each active full-bridge rectifier). To sum-up, the covetioal topology is complex ad expesive, especially for a high umber of clamps. I the ext sectio, the proposed system that overcomes the aforemetioed problems will be itroduced. 3 Proposed residetial ICET system with multiple mobile clamps Fig. shows the schematic of the proposed topology to supply mobile clamps. The topology cosists of a buck coverter, RI, resoat elemets, a high-frequecy trasformer, ad diode bridge rectifiers with low-pass filters. I this system, the buck coverter is resposible to iject a costat DC curret (i z ) to the RI. This costat curret is essetial to guaratee fixed output voltages (v o1,, v o ) regardless of the load coditios. I practice, i z is fixed by applyig a covetioal PWM closed-loop curret-mode cotrol to drive the switch S b i accordace with the desired referece curret (I ref ), as show i Fig. 3a. As a cosequece of the costat curret, the voltage v z chages automatically as a fuctio of the load due to the power matchig issue (i.e. the iput power is roughly equal to the total output power supplied to the loads). Therefore, based o the proposed system, the aforemetioed efficiecy problem is improved eve for low load coditios. This property will be validated theoretically i the ext sectios. Note that the value of v z should always be lower tha the buck coverter iput voltage (V b ). Oce this issue is respected, a correct operatio of the buck coverter ca be esured (v z < V b ). O the other had, the iverter operates with the simple zerocrossig detectio (ZCD) modulatio strategy show i Fig. 3b. The resoat curret i r is used to match the switchig frequecy (f s ) with the resoat frequecy (f o ) i a feedforward way by operatig the coverter cotiuously i eergisig mode [9]. This cotrol strategy causes costat amplitude i i r as show i Fig. 3c. By applyig ZCD to the iverter o the oe side ad usig a passive diode rectifier o the other side, the iput eergy is completely trasferred to the load as a uidirectioal flow (from iput side to the output side oly) while i the covetioal topology this curret varies as a fuctio of load followig a amplitude modulatio approach. This priciple of operatio avoids the trasformer saturatio problem by prevetig the flowig of high currets ito the trasformers. Moreover, the voltage ad curret waveforms are perfectly i phase i the output side of the iverter, avoidig reactive power flowig ito the resoat tak. Additioally, a passive diode rectifier is used for each clamp istead of the cotrolled rectifier employed i the covetioal topology. Also, a small parallel secodary side capacitor C pi is icluded i the proposed topology to fix the output voltages. As a cosequece of these chages, the cost ad complexity of the proposed topology are reduced particularly i the case of high umber of mobile clamps. Also, due to the secod-order output filter, the curret flowig through the filter capacitor is low, reducig the coductio losses i ESRs ad cosequetly icreasig the system efficiecy. The proper fuctio of this topology is highly depedet o the performace of the buck coverter i the first stage. The buck coverter is a fudametal elemet to both guaratee a fixed output

4 Fig. 4 Equivalet circuit of the proposed topology voltage ad to icrease efficiecy. This coverter i collaboratio with RI is resposible to produce a fix curret for the secodary side resoat elemets (L m, L s ad C p ). The total impedace of these elemets (Z LC ) is i parallel with load (R o ). Therefore, by proper desig of C p the load effect ca be eglected because of domiat value of Z LC (i.e. Z LC =R o ), resultig i fixed output voltage regardless of the load coditios. The desig process of C p to obtai a fix output voltage will be explaied i Sectio 5. The RI operates i closed-loop with oly a feedforward term to detect the zero-crossig of the resoat curret (Fig. 3c). The siusoidal waveform is the resoat curret i r ad the square waveform is the voltage v p. I steady state, the curret i r ca be expressed as i r = π I ref si ω o t (1) where ω o is the agular resoat frequecy. Note that its amplitude is proportioal to the output curret of the buck coverter. From Fig. 3c, the value of v p ca be expressed as v p = v z sg i r () I the proposed topology, the two waveforms (i r ad v p ) are completely i phase. Therefore, circulatig reactive curret is completely avoided, thus achievig uity power factor operatio. Also, at f s = f o, the switches tur o ad off at zero curret, reducig switchig losses [35]. As a cosequece of both issues, the efficiecy of the proposed topology improves sigificatly. Also, the priciple of operatio of the iverter allows that the voltage v z automatically chages accordig to the required output power while the curret i z is fixed by the buck coverter. Therefore, the proposed system ca regulate the iput power without the eed for a commuicatio system. It is worth metioig that a fixed amplitude curret ca also be obtaied i the resoat curret usig differet approaches, for istace with a feedback cotrol system icludig frequecy or phase modulators. I these approaches, the iput buck coverter ca be elimiated. However, i all these cases, the uity power factor provided by the proposed solutio caot be guarateed, thus forcig the slidig trasformer to operate i a more stressig coditio. Takig ito accout the complex structure of the slidig trasformer (log primary loop ad several mobile secodary sides), the operatio of the RI with oly a sigle feedforward curret term is a iterestig optio to elimiate the flowig of reactive power i the slidig trasformer. 4 Mathematical modellig of the proposed topology This sectio presets a equivalet model for the proposed topology. This model is employed to derive the mai characteristics of the topology. 4.1 Model of the proposed topology The proposed topology ca be represeted by the equivalet circuit model show i Fig. 4. The model cotais a iput curret source, two cotrolled sources, resoat compoets ad equivalet resistors. The curret source I ref represets the operatio of the buck coverter while the cotrolled sources characterise the operatio of the RI. Note that the cotrolled curret source reflects the primary side resoat curret i r to the iverter iput side. Besides, the cotrolled voltage source models the effect of the iput voltage v z o the iverter output side. For simplicity, the magetisig iductace, parallel capacitors ad leakage iductace are assumed equal i all clamps (L mi = L m, C pi = C p ad L si = L s ). Also, a uity turs ratio is assumed for trasformers ( t = 1). Moreover, the effect of dissipative ature of the loads is modelled by the equivalet AC resistors (R ac1,, R ac ). The value of R aci uder steady-state coditio ca be expressed as [36] R aci = π 8 R oi, i = 1,,. (3) where R oi is the output resistor ad stads for the umber of clamps. 4. Agular resoat frequecy The proposed topology operates at ω = ω o, where ω is the agular frequecy. Therefore, to desig ad aalyse the proposed system, a accurate expressio for ω o should be obtaied as a iitial step to calculate the desig parameters. First ω o should be determied by aalysig the total impedace Z i marked i Fig. 4. I fact, the resoat frequecy is defied as the frequecy whe the imagiary part of the total impedace is zero. The total impedace is a fuctio of the series ad parallel compoets which ca be represeted by the followig equatio: Z i = jωl r j + ωc Z pi (4) r i = 1 where L r ad C r are the series compoets ad Z pi stads for the parallel impedaces show i Fig. 4. For the correct operatio of the proposed coverter, it is ecessary that the parallel impedaces are idepedet of the load resistors. This coditio is satisfied whe the parallel capacitor is desiged accordig to (5) C p a = R ac i L m + L s 1 ω L m + L s 1 + Max a, b (5) R aci + L m L m + L s + L m + L s ω R aci L s (6) b = ω L m + L s R aci (7) I this case, the iput impedace ca be represeted as Z i = j ωl r 1 ωc r + ωl m ω L s C p 1 ω C p L m + L s 1 The resoat agular frequecy is obtaied by settig (8) equal to zero (the by defiitio ω = ω o ) ad solvig for ω o. The expressio for ω o is writte as (see (9)) 4.3 Output voltages I Fig. 4, the output voltage v si is a siusoidal sigal operatig at the resoat frequecy. Its amplitude relies o the parallel impedace (Z p ) ad the amplitude of the resoat curret (8)

5 Table 1 Circuit parameters for the proposed desig Parameter Symbol Value Uits iput voltage V b 15 V magetisig iductace L m 50 µh leakage iductace L s.5 µh switchig frequecy f s 110 khz miimum load resistor R oimi 100 Ω output voltage v oi V (1/C p ω o ) V si = Z pi I r L s ω o + (1/C p ω o ) ω o L m ω o L s C p 1 = ω 4 o C p L s L m + L s + ω o C p L m 1 π I ref (10) From Fig., the output voltage v oi is obtaied by rectifyig ad filterig the siusoidal voltage v si. Therefore, v oi ca be expressed as v oi = π v si = ω o L m ω o L s C p 1 ω o 4 C p L s L m + L s + ω o C p L m 1 I ref (11) It must be oticed that the output voltage is idepedet of the load coditios. 4.4 Desig coditios for the referece curret The last step is to determie a desig coditio for I ref. As described above, the voltage v z varies as a fuctio of the load. Oce the iput curret to the resoat coverter I ref is costat, the variatios i the iput power produced by load chages modify the voltage v z. I the worst-case sceario (i.e. R oi = R oimi ), the relatio betwee these variables ca be expressed, assumig a ideal efficiecy (100%) as v z I ref = (1) R oimi i = 1 Moreover, to esure a correct operatio of the buck coverter, its iput voltage V b must be always greater (or equal) tha the output voltage v z. Accordig to this coditio, (1) ca be re-writte as follows: i = 1 v oi v oi From (13), the value for I ref ca be limited as R oimi V b I ref (13) I ref (14) R oimi V b i = 1 I practice, the value of I ref must be slightly over-dimesioed to compesate the ideal assumptio of 100% efficiecy. I the ext sectio, a desig example will be preseted. v oi 5 Desig of the proposed topology The ecessary circuit parameters for startig the desig process are listed i Table 1. Note that these values correspod to a low-power experimetal prototype. The desig process is based o the worstcase sceario (i.e. R oi = R oimi ) ad it is preseted i the followig steps: Step 1: I the first step, the referece curret of the buck coverter is determied based o Table 1 ad (14). From (14), the miimum value of the referece curret is I ref = 0.64 A. This value itroduces the miimum curret for a correct operatio of the buck coverter. Step : The value of the parallel capacitor C p for each clamp ca be obtaied from (11) as C p = 80 F. Accordig to (5), this value esures a costat output voltage idepedet of the load coditio. Step 3: I the fial step, the values for C r ad L r are obtaied. It should be oted that the primary leakage iductace has a small value. Also, this value may experiece some chages durig the operatio of the system. Therefore, to elimiate the effect of this leakage iductace, L r should be chose oticeably higher. I this example, L r is chose equal to 40 µh which is drastically >.5 µh. By solvig (9), C r = 68 F is calculated. By followig these steps, a proper desig for the proposed topology is reached. The theoretical desig is validated experimetally i the ext sectio. 6 Experimetal validatio The predicted theoretical results icludig priciple of operatio ad performace of the proposed approach as well as the proposed desig procedure are verified experimetally i this sectio. Also, a compariso betwee the proposed ad covetioal topologies is icluded. A low-power high-frequecy DC/DC resoat coverter prototype with two clamps has bee built ad tested as show i Fig. 5. The cotrol system show i Fig. 3 was implemeted usig aalogue circuits. The mai circuit parameters are give i Table. Note that the values are chose based o the desig process explaied i the previous sectio. Moreover, some selected results for the covetioal topology will be also preseted for compariso purposes. It should be metioed that a system with amplitude modulatio cotrol techique has bee built ad tested based o [9]. Table 3 lists the mai circuit parameters of the covetioal topology. To have a fair compariso, the values of this table are selected accordig to the desig process preseted i [9] to achieve the same output power, output voltage ad switchig frequecy. 6.1 Compariso betwee the covetioal ad proposed topologies Fig. 6 shows the mai waveforms of the covetioal ad proposed topologies. As show, the covetioal topology has amplitude modulatio i the resoat curret which produces higher peak value i comparig with the proposed topology. I the covetioal topology, the power flow from the iput source to the resoat tak is decided by the closed-loop cotrol system. Whe the amplitude curret icreases, the power is flowig ito the resoat tak; whe the amplitude curret decreases, the iput power is zero ad the stored eergy i the resoat tak is discharged i the loads. This priciple of operatio produces a higher peak curret i all devices (icludig power switches ad diodes). Coversely, i the proposed topology, the power flow is cotiuous ad costat, reducig the stress of the devices. ω o = L m C r + C p + C p L s + C r L r + c C p C r L m L r + L m L s + L r L s c = C p C p L m L m + L s + L m C r L m L r L s + L s C p L s C r L r +C r L m L m + L r + L r (9)

6 Fig. 8 shows the measured efficiecy of the covetioal ad proposed topologies. Note that higher efficiecy is obtaied i the proposed topology. I particular, at 10% of full load, the proposed topology improves the efficiecy i early 5 poits compared with the covetioal topology result. This icrease is a cosequece of the iput voltage v z variatio accordig to the load cosumptio. I the covetioal system, there is o adaptatio to load coditio. The maximum efficiecy for the proposed topology is obtaied at full load, beig 80% i practice. Note that the power losses related to the buck coverter are also icluded i this figure. Fig. 5 Experimetal set-up with two mobile clamps Fig. 7 shows the output waveforms of the RI (voltage v p ad curret i r ) for the proposed topology i two differet load coditios. Note that the curret has a costat peak value idepedet of the load. The voltage is a (early) square wave ad its amplitude depeds o the load coditio. As predicted by (1), this voltage chages accordig to the output power. Table Circuit parameters ad compoets for the proposed topology Parameter Symbol Value Uits iput voltage of buck coverter V b 15 V buck coverter iductor L b 50 µh buck coverter capacitor C b µf series resoat capacitor C r 68 F series resoat iductor L r 40 µh magetisig iductace L m1, L m 50 µh leakage iductace L s.5 µh gap distace G d 0.1 cm trasformer tur-ratio t 1 parallel resoat capacitor C p1, C p 8 F output iductor filter L o1, L o 4 mh output capacitor filter C o1, C o 10 µf miimum resistive load R o1mi, R omi, 100 Ω output voltage v o1, v o V referece curret I ref 0.7 A RI switchig frequecy f s 110 khz buck coverter switchig frequecy f b 50 khz buck coverter diode buck coverter ad RI switches driver diode rectifier 1N5817 MOSFET IRFP50N HIP4081A KBU4M Table 3 Circuit parameters ad compoets for the covetioal topology Parameter Symbol Value Uits iput voltage V b 15 V series resoat capacitor C r 68 F series resoat iductor L r 40 µh magetisig iductace L m1, L m 50 µh leakage iductace L s.5 µh gap distace G d 0.1 cm output capacitor filter C o1, C o 0 µf miimum resistive load R o1mi, R omi, 100 Ω trasformer tur-ratio t 1 switchig frequecy f s 110 khz output voltage v o1, v o V 6. Performace i steady state Fig. 9a shows the experimetal results of output voltage as a fuctio of loads 1 ad for the proposed topology. The measures for both output voltages roughly coicide (v o1 = v o ) ad, therefore, oly the voltage v o1 is depicted i this figure. The results show that the output voltage is approximately costat for all the load coditios whe usig the proposed topology. Fig. 9b illustrates the variatio of output voltage v o1 for differet clamp positio alog the primary widig loop. Note that the legth of the primary widig loop is 10 cm. The experimetal measuremet for v o1 is obtaied alogside the miimum (5 cm) to the maximum (60 cm) clamp distace from the RI. As evidet, the output voltage is early costat i all the clamp positios. This iterestig property is achieved due to the costat curret i r flowig through the primary widig loop. Fig. 9c shows the output voltage as a fuctio of air gap variatio. It should be oticed that the air gap is defied as the distace betwee primary ad secodary widig. From the figure, by icreasig the air gap the output voltage is reduced. As predicted by (11), the output voltage is depedig o the magetisig iductace ad leakage iductace, which varies with the gap distace. Therefore, the mechaism of the clamp coectio to the primary widig loop should be cosidered as a importat issue. I fact, a robust mechaical coectio to the primary widig loop is ecessary to guaratee costat output voltage i the proposed system. 6.3 Performace i trasiet state Fig. 10a shows the output voltage (top) ad output curret (bottom) durig load step chages i covetioal topology. The load is chaged from the full load to 10% full load ad vice versa, respectively. As it ca be see the covetioal system operates correctly ad regulate the output voltage accordig to the desired referece voltage (V oref = 0 V). It should be metioed that this priciple of operatio is achieved as a cosequece of usig the secodary side cotrol system. Although, the output voltage ca be correctly regulated, the cost of the system is drastically icreased i the case of high umber of clamps. Fig. 10b shows the mai waveforms of the proposed topology i trasiet state. Fig. 10b shows the output voltage v o1 ad curret i o1, respectively, durig the step load chages from full load to 10% ad retur to full load. As predicted theoretically, the output voltage i steady state is early idepedet of the load coditios ad has a costat value eve usig passive rectifiers at the output side. As explaied before, the proposed system as a cosequece of usig passive rectifiers istead of active full-bridge rectifiers has a slow trasiet system (for a easy compariso, ote that the scales i Figs. 10a ad b are differet). This allows us to idetify the practical applicatio of the proposed topology for supplyig active DC residetial loads with iteral post-regulators (laptops, mobile phoes, etc) [33, 34]. Fig. 10c illustrates the i r ad v z, respectively, durig step load chages. Accordig to the figure, the iput voltage v z is automatically chaged accordig to the load coditios. Also, as a cosequece of fixed iput curret provided by buck coverter, the amplitude of the resoat curret is fixed i all the load coditios. As it ca be see, the proposed system ca regulate the iput power without the eed for a commuicatio system. Therefore, the

7 Fig. 6 Measured output voltage v oi (Top, 10 V/div) ad resoat curret i r (500 ma, 50 µs/div) (a) Covetioal topology, (b) Proposed topology Fig. 7 Measured resoat curret i r (siusoidal waveform, 00 ma/div, µs/div) ad voltage v p (square waveform, 5 V/div, µs/div) i two load coditios for the proposed topology (a) Full load ad (b) 10% full load Fig. 8 Efficiecy as a fuctio of load. Covetioal topology (grey), proposed topology (black) efficiecy of the proposed topology improves sigificatly i low load coditios. 6.4 Cost compariso Table 4 lists the compoet cout of the covetioal ad proposed topologies. From the poit-of-view of cost, the egative poit of the covetioal topology is the icreasig umber of power switches with the umber of clamps (). I additio, the umber of cotrol systems, icludig voltage ad curret sesors, itegrated cotrol circuits ad drivers also icrease with the umber of clamps. I the case of the proposed topology, oly the umber of power diodes, capacitors ad iductors icrease with the umber of clamps. It is worth metioig that for a low umber of clamps, both topologies have similar cost. However, for a high umber of clamps, the cost of the covetioal topology icreases drastically compared with the cost of the proposed topology. Cosequetly, the proposed topology is a cost-effective solutio whe a system with a high umber of clamps is required. 7 Coclusio I this paper, a ew approach to supply the ICET system with multiple-receivers has bee preseted. It is based o the cascaded coectio of a buck coverter operatig as a costat curret source ad high-frequecy resoat curret workig with oly a feedforward cotrol system. A theoretical tool for the aalysis ad desig of the proposed topology has bee itroduced. The aalysis starts with the developmet of a static model of the resoat coverter based o the first harmoic approximatio. The model is simple, predicts accurately the particular properties of the proposed approach, ad is useful for the derivatio of the desig coditios for the coverter compoets. I additio, a systematic step-bystep procedure has bee proposed to desig the coverter compoets. The theoretical aalysis has bee practically validated by selected experimetal results. The properties of the proposed approach have bee compared with the properties of the covetioal approach, resultig i higher efficiecy ad lower cost. I particular, the cost is more competitive as the umber of mobile receivers of the system icreases. 8 Ackowledgmets This work has bee supported by ELAC014/ESE0034 from the Europea Uio ad its liked Spaish atioal project PCIN We also appreciate the support from the Miistry of Ecoomy ad Competitiveess of Spai uder project ENE C-1-R.

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