Microprocessor Based Signal Processing Techniques for System Identification and Adaptive Control of DC-DC Converters

Transcription

1 Microprocessor Based Sigal Processig Techiques for System Idetificatio ad Adaptive Cotrol of DC-DC Coverters Maher Mohammed Fawzi Saber Algreer B.Sc., M.Sc. A thesis submitted for the degree of Doctor of Philosophy May, 202 School of Electrical, Electroic ad Computer Egieerig Newcastle Uiversity Uited Kigdom

2 ABSTRACT May idustrial ad cosumer devices rely o switch mode power coverters SMPCs to provide a reliable, well regulated, DC power supply. A poorly performig power supply ca potetially compromise the characteristic behaviour, efficiecy, ad operatig rage of the device. To esure accurate regulatio of the SMPC, optimal cotrol of the power coverter output is required. However, SMPC ucertaities such as compoet variatios ad load chages will affect the performace of the cotroller. To compesate for these time varyig problems, there is icreasig iterest i employig real-time adaptive cotrol techiques i SMPC applicatios. It is importat to ote that may adaptive cotrollers costatly tue ad adjust their parameters based upo o-lie system idetificatio. I the area of system idetificatio ad adaptive cotrol, Recursive Least Square RLS method provide promisig results i terms of fast covergece rate, small predictio error, accurate parametric estimatio, ad simple adaptive structure. Despite beig popular, RLS methods ofte have limited applicatio i low cost systems, such as SMPCs, due to the computatioally heavy calculatios demadig sigificat hardware resources which, i tur, may require a high specificatio microprocessor to successfully implemet. For this reaso, this thesis presets research ito lower complexity adaptive sigal processig ad filterig techiques for o-lie system idetificatio ad cotrol of SMPCs systems. The thesis presets the ovel applicatio of a Dichotomous Coordiate Descet DCD algorithm for the system idetificatio of a dc-dc buck coverter. Two uique applicatios of the DCD algorithm are proposed; system idetificatio ad selfcompesatio of a dc-dc SMPC. Firstly, specific attetio is give to the parameter estimatio of dc-dc buck SMPC. It is computatioally efficiet, ad uses a ifiite

3 impulse respose IIR adaptive filter as a plat model. Importatly, the proposed method is able to idetify the parameters quickly ad accurately; thus offerig a efficiet hardware solutio which is well suited to real-time applicatios. Secodly, ew alterative adaptive schemes that do ot deped etirely o estimatig the plat parameters is embedded with DCD algorithm. The proposed techique is based o a simple adaptive filter method ad uses a oe-tap fiite impulse respose FIR predictio error filter PEF. Experimetal ad simulatio results clearly show the DCD techique ca be optimised to achieve comparable performace to classic RLS algorithms. However, it is computatioally superior; thus makig it a ideal cadidate techique for low cost microprocessor based applicatios.

4 IV DEDICATION To my lovig parets ad my wife Israa

5 V ACKNOWLEDGMENTS I would like to ackowledge everyoe for those who made this work possible to complete. First ad foremost, I would like to thak God that gives me the patiece to complete this work, praise to God. I would also like to express my deep sicere gratitude towards all my supervisors Dr. Matthew Armstrog, Dr. Damia Giaouris, ad Dr. Petros Missailidis for their support, patiet guidace ad ecouragemet durig my doctoral research. The successful achievemet of this work would ot be complete without their support. I would like to exted my thaks to Dr. Matthew Armstrog for his amicable ature that he has provided for positive free stress collaboratio ad for sharig his expertise i practical desig. Hoestly, he has a exemplary role that always preseted kids words for ecouragemet. My ackowledgmets also go to my frieds ad colleagues at PEDM Lab, for their collaboratio. My thaks also go to Bassim Jassim for sharig his kowledge o power electroics. I additio, I would like to thak the academic ad techicias staff i EECE for their cooperatio. My thak towards the head of school Prof. Baya Sharif for his collaboratio durig my life i Newcastle city. I thak Mrs Gillia Webber ad Deborah Alexader for help i all the admiistrative work. I am also grateful idebted to Dr. Yuriy Zakharov of the Uiversity of York, for his valuable commets ad advice received from him o the DCD algorithm. I would like to gratefully appreciate the Miistry of Higher Educatio, from my home coutry IRAQ, for the fiacial support durig this research, without their sposorship, I could ot complete this work.

6 VI Fially, my deepest appreciatio to my father ad mother, for their love ad cotiues support they provide me through my etire life. I am always imagiig my paret happiess whe I will be successes i PhD to ecourage myself progressig more. I owe all that I have. I would like to warmly thak all my brothers, my lovely sister Moroj ad my sos Mohib ad Majd, they give me the power to complete this work ad give me edless morale support. Last but most importat, to say thaks to my wife ISRAA, you always ecourage me, give me the stregth ad ethusiasm to complete this research, she always face the same tesio ad frustratio that I had durig my work. This project would ot be complete without her uderstadig ad love.

7 VII TABLE OF CONTENTS ABSTRACT... II DEDICATION... IV ACKNOWLEDGMENTS... V LIST OF FIGURES... XII LIST OF TABLES... XIX LIST OF ACRONYMS... XX LIST OF SYMBOL... XXII Chapter INTRODUCTION AND SCOPE OF THE THESIS.... Itroductio....2 Scope ad Cotributio of the Thesis Publicatios Arisig from this Research Layout of the Thesis Notatios... 8 Chapter 2 DC-DC SWITCH MODE POWER CONVERTERS MODELLING AND CONTROL Itroductio... 9

8 VIII 2.2 DC-DC Circuit Topologies ad Operatio DC-DC Buck Coverter Priciple of Operatio DC-DC Buck Coverter Modellig Model Simulatio Buck State Space Average Model Discrete Time Modellig of Buck SMPC Digital Cotrol Architecture for PWM DC-DC Power Coverters Digital Voltage Mode Cotrol Digital Proportioal-Itegral-Derivative Cotrol Digital Cotrol for Buck SMPC Based o PID Pole-Zero Cacellatio Pole Placemet PID Cotroller for DC-DC Buck SMPC Chapter Summary Chapter 3 SYSTEM IDENTIFICATION, ADAPTIVE CONTROL AND ADAPTIVE FILTER PRINCIPLES -A LITERATURE REVIEW Itroductio Itroductio to System Idetificatio Parametric ad No-Parametric Idetificatio Model Structures for Parametric Idetificatio Parametric Idetificatio Process Adaptive Cotrol ad Adaptive Filter Applicatios Adaptive Cotrol Structures Adaptive Filter Techiques... 49

9 IX 3.9 Literature Review o System Idetificatio ad Adaptive Cotrol for DC-DC Coverters No-Parametric System Idetificatio Techiques ad Adaptive Cotrol for SMPC Parametric Estimatio Techiques ad Adaptive Cotrol for SMPC Idepedet Adaptive Cotrol Techique for SMPC Chapter Summary Chapter 4 SYSTEM IDENTIFICATION OF DC-DC CONVERTER USING A RECURSIVE DCD-IIR ADAPTIVE FILTER Itroductio System Idetificatio of DC-DC Coverter Usig Adaptive IIR DCD-RLS Algorithm Adaptive System Idetificatio Least Square Parameters Estimatio Covetioal RLS Estimatio Normal Equatios Solutio Based O Iterative RLS Approach Expoetially Weighted RLS Algorithm ERLS Coordiate Descet ad Dichotomous Coordiate Descet Algorithms Dichotomous Coordiate Descet Algorithm Pseudo-Radom Biary Sequece ad Persistece Excitatio Discrete Time Modellig of DC-DC Coverter ad Adaptive IIR Filter Equatio Error IIR Adaptive Filter Parameter Estimatio Metrics ad Validatio... 9

10 X 4. Model Example ad Simulatio Results Adaptive Forgettig Strategy Fuzzy RLS Adaptive Method for Variable Forgettig Factor Simulatio Test Chapter Summary... 0 Chapter 5 ADAPTIVE CONTROL OF A DC-DC SWITCH MODE POWER CONVERTER USING A RECURSIVE FIR PREDICTOR Itroductio Self-Compesatio of a DC-DC Coverter Based o Predictive FIR Auto-Regressive / Process Geeratio, Idetificatio Relatioship betwee Forward Predictio Error Filter ad AR Idetifier Oe-Tap Liear FIR Predictor for PD Compesatio Least Mea Square Algorithm Simulatio Results Referece Voltage Feed-Forward Adaptive Cotroller Voltage Cotrol Usig Adaptive PD+I Cotroller Robustess ad Stability Aalysis for the Proposed Adaptive PD+I Cotroller Chapter Summary Chapter 6 MICROPROCESSOR APPLICATION BASED SYNCHRONOUS DC-DC SWITCH MODE POWER CONVERTER-EXPERIMENTAL RESULTS Itroductio... 39

11 XI 6.2 Microprocessor Cotrol Platform Microprocessor Code Developmet System Hardware Descriptio ad Microprocessor Setup System Idetificatio Usig DCD-RLS / Experimetal Validatio Realisatio of the Coverter Model Adaptive Cotroller / Experimetal Validatio Complexity Reductio Chapter Summary Chapter 7 CONCLUSION AND FUTURE WORK Coclusio Future Work APPENDIX A DERIVATION OF RLS ALGORITHM BASED ON MATRIX INVERSION LEMMA APPENDIX B SCHEMATIC CIRCUIT OF THE SYNCHRONOUS BUCK CONVERTER 75 APPENDIX C SIMULINK MODEL OF THE PROPOSED STRUCTURES REFERENCES... 80

12 XII LIST OF FIGURES Fig.. Dual core microprocessor ad digital cotrol architecture for SMPCs... 3 Fig. 2. Most commo dc-dc coverter topologies, a: buck coverter, b: boost coverter, c: buck-boost coverter... 0 Fig. 2.2 Buck coverter circuit cofiguratio, a: O state iterval, b: Off state iterval... 3 Fig. 2.3 Ope loop steady state output voltage... 4 Fig. 2.4 Ope loop steady state iductor curret... 5 Fig. 2.5 Digital voltage mode cotrol architecture of DC-DC SMPC...20 Fig. 2.6 Two-poles / Two-zeros IIR digital cotroller Fig. 2.7 Digital PID compesator Fig. 2.8 Frequecy respose of the compesated ad ucompesated dc-dc buck SMPC Fig. 2.9 Power stage root locus Fig. 2.0 PID compesator root locus Fig. 2. Total loop gais root locus Fig. 2.2 Trasiet respose of the PID cotroller, a: output voltage, b: iductor curret, c: load curret. Load curret chage betwee 0.66 A ad.32 A every 5 ms Fig. 2.3 Closed loop cotrol of the buck SMPC... 3

13 XIII Fig. 2.4 Frequecy respose of the compesated ad ucompesated dc-dc buck SMPC Fig. 2.5 Trasiet respose of the pole-placemet PID cotroller, a: output voltage, b: iductor curret, c: load curret. Load curret chage betwee 0.66 A ad.32 A every 5 ms Fig. 2.6 Loop-gai compariso betwee pole-placemet ad pole-zero PID cotrollers Fig. 2.7 Compariso of trasiet respose results betwee pole-placemet ad pole-zero PID cotrollers. Repetitive load curret chage betwee 0.66 A ad.32 A every 5 ms Fig. 3. Geeral block diagram of parametric idetificatio Fig. 3.2 Geeral liear model trasfer fuctio... 4 Fig. 3.3 Parametric idetificatio model structures Fig. 3.4 Parametric idetificatio flowchart Fig. 3.5 Adaptive model referece structure Fig. 3.6 Self-tuig cotroller block-diagram Fig. 3.7 A adaptive filter structure Fig. 3.8 Adaptive Filter structures, a: system idetificatio, b: sigal predictio, c: iverse modellig, d: oise cacellatio Fig. 4. The proposed closed loop adaptive IIR idetificatio method usig DCD- RLS algorithm Fig. 4.2 Adaptive system idetificatio block diagram Fig. 4.3 Closed loop operatio of covetioal RLS algorithm based matrix iversio lemma... 7 Fig. 4.4 Nie-bits sigle period PRBS... 84

14 XIV Fig. 4.5 Nie-bits shift register with XOR feedback for 5 maximum legth PRBS geeratio Fig. 4.6 Ideal auto-correlatio of a ifiite period of PRBS Fig. 4.7 Sigle period 9-bit auto-correlatio of PRBS Fig. 4.8 System idetificatio based o adaptive IIR filter usig output error block diagram Fig. 4.9 System idetificatio based o adaptive IIR filter usig equatio error block diagram Fig. 4.0 The procedure of system idetificatio Fig. 4. Idetificatio sequece, a: output voltage durig ID, b: voltage model parameters ID, c: voltage error predictio, d. ID eable sigal Fig. 4.2 Tap-weights estimatio for IIR filter usig DCD-RLS ad classical RLS methods; compared with calculated model Fig. 4.3 Predictio error sigals, a: classical RLS, b: DCD-RLS Fig. 4.4 Parameters estimatio error, a: classical RLS, b: DCD-RLS Fig. 4.5 Tap-weights estimatio DCD-RLS at Nu = 4 ad classical RLS Fig. 4.6 Tap-weights estimatio DCD-RLS ad CD algorithms Fig. 4.7 Frequecy resposes for cotrol-to-output trasfer of fuctio; estimated ad calculated model Fig. 4.8 The proposed system idetificatio structure for a dc-dc coverter based o RLS fuzzy AFF Fig. 4.9 Geeral block diagram of the fuzzy logic system Fig Fuzzy logic iput ad output membership fuctios, a: e 2 p, b: Δe 2 p, c: λ... 05

15 XV Fig. 4.2 Parameters estimatio of cotrol-to-output voltage trasfer of a dc-dc coverter at load chages from 5-to- Ω usig DCD-RLS algorithm at a: λ = 0.7, b: λ = 0.99, c: fuzzy AFF Fig Predictio error sigal durig iitial start-up ad at load chage Fig Forgettig factor at iitial start-up ad at load chage Fig. 5. Adaptive PD+I cotroller usig oe tap DCD-RLS PEF... 3 Fig. 5.2 Recostructio of white oise... 4 Fig. 5.3 AR process geerator... 5 Fig. 5.4 AR process idetifier... 6 Fig. 5.5 Oe step ahead forward predictor... 7 Fig. 5.6 Forward predictio error filter... 8 Fig. 5.7 Predictio error filter... 8 Fig. 5.8 AR aalyser, a: matched Iverse MA filter, b: oe tap adaptive PEF, c: two tap adaptive PEF filter. The dotted lie is the estimated output ad the solid lie is the actual iput... 9 Fig. 5.9 Closed loop LMS system block diagram Fig. 5.0 Referece voltage feed-forward: Compariso of trasiet respose betwee LMS ad DCD-RLS. Repetitive load chage betwee 0.66 A ad.32 A every 5 ms Fig. 5. Zoomed adaptatio of gai K d ad tap-weight w i the two stage adaptive liear predictor for differet step-size values Fig. 5.2 Trasiet respose of the proposed adaptive cotroller, a: output voltage, b: iductor curret, c: load curret chage betwee 0.66A ad.32 A every 5 ms. 29 Fig. 5.3 Error sigal behaviour durig adaptatio process, a: loop error e L, b: predictio error e p. Load curret chage betwee 0.66 A ad.32 A every 5 ms 30

16 XVI Fig. 5.4 Trasiet respose of the proposed adaptive PD+I cotroller usig DCD- RLS or LMS. Load curret chage betwee 0.66 A ad.32 A every 5 ms... 3 Fig. 5.5 Trasiet respose of the proposed adaptive cotroller durig load curret chage betwee 0.66 A ad.32 A every 5 ms, a: output capacitace C = 50 μf ad L = 220 μh, b: C = 660 μf ad L = 220 μh, c: output iductor L = 00 μh ad C = 330 μf Fig. 5.6 Compariso of trasiet respose results betwee the proposed adaptive PD+I usig DCD-RLS ad pole-zero PID cotrol. Repetitive load curret chage betwee 0.66 A ad.32 A every 5 ms Fig. 5.7 Frequecy respose of the PD + I compesator ad the compesated / ucompesated ope loop gais Fig. 5.8 Closed loop scheme of voltage mode cotrol for SMPC Fig. 5.9 Sesitivity fuctios of the PD+I cotroller Fig Margis o Nyquist plot Fig. 6. TMS320F28335 ezdsp Architecture [29] Fig. 6.2 Hardware platform setup Fig. 6.3 Block diagram of the sychroous dc-dc buck coverter based o microprocessor Fig. 6.4 a: TMS320F28335 DSP platform, b: the sychroous dc-dc buck coverter circuit Fig. 6.5 PWM waveforms i ope loop circuit test, a: duty ratio 50 %, b: duty ratio 33 % Fig. 6.6 Leadig DCD-RLS algorithm flowchart Fig. 6.7 Experimetal output voltage waveform whe idetificatio eabled. ac coupled... 49

17 XVII Fig. 6.8 Experimetal output voltage ad persistece excitatio sigal duty sigal + PRBS results durig ID, based o sampled data collected from DSP... 5 Fig. 6.9 Experimetal tap-weights estimatio for IIR filter with DCD-RLS ad classical RLS methods; compared with the calculated model Fig. 6.0 Experimetal predictio error results, a: covetioal RLS, b: DCD-RLS Fig. 6. Experimetal parameters estimatio error, a: classical RLS, b: DCD-RLS Fig. 6.2 Experimetal learig curves compariso results of covetioal RLS agaist DCD-RLS at differet iteratio values Fig. 6.3 Experimetal sampled data collected from DSP, a: output voltage, b: cotrol sigal duty sigal + PRBS Fig. 6.4 Model errors compariso betwee third/secod order output error ad equatio error model Fig. 6.5 Trasiet respose of PID cotroller with abrupt load chage betwee 0.66 A ad.32 A. a 4 ms/div: showig two trasiet chages. b 400 µs/div: zoom-i o secod trasiet Fig. 6.6 Trasiet respose of adaptive PD+I DCD-RLS cotroller with abrupt load chage betwee 0.66 A ad.32 A. a 4 ms/div: showig two trasiet chages. b 400 µs/div: zoom-i o secod trasiet Fig. 6.7 Trasiet respose of adaptive PD+I LMS cotroller with abrupt load chage betwee 0.66 A ad.32 A. a 4 ms/div: showig two trasiet chages. b 400 µs/div: zoom-i o secod trasiet... 6 Fig. 6.8 Load trasiet respose at sigificat chage i load curret, with two stage DCD-DCD adaptive cotroller ad hybrid DCD-LMS adaptive cotroller... 63

18 XVIII Fig. 6.9 Trasiet respose of hybrid DCD-RLS:LMS µ = adaptive cotroller with abrupt load chage betwee 0.66 A ad.32 A. a 4 ms/div: showig two trasiet chages. b 400 µs/div: zoom-i o secod trasiet... 64

19 XIX LIST OF TABLES Table 4.Covetioal RLS algorithm based matrix iversio lemma... 7 Table 4.2 Iteratively solvig for auxiliary equatios Table 4.3 ERLS algorithm usig auxiliary equatios Table 4.4 Exact lie search algorithm descriptio Table 4.5 Cyclic CD algorithm descriptio Table 4.6 Leadig CD algorithm descriptio Table 4.7 Cyclic DCD algorithm descriptio Table 4.8 Leadig DCD algorithm descriptio Table 4.9 Bit cell setup for differet MLBS geeratio Table 4.0 Discrete time cotrol-to-output trasfer fuctio idetificatio Table 4. The rule base for the forgettig factor λ Table 5. LMS algorithm operatio Table 6. Prototyped sychroous buck coverter parameters... 44

20 XX LIST OF ACRONYMS AC ADC AR ARMA CCM CCS CD CPU DAC DC DCD DCM DPWM DSP ERLS FFT FIR Alteratig Curret Aalogue -to-digital Coverter Auto-Regressive Auto Regressive Movig Average Model Cotiuous Coductio Mode Code Composer Studio Coordiate Descet Cetral Processig Uit Digital-to-Aalogue Coverter Direct Curret Dichotomous Coordiate Descet Discotiuous Coductio Mode Digital Pulse Width Modulatio Digital Sigal Processor Expoetially Weighted Recursive Least Square Fast Fourier Trasform Fiite Impulse Respose

21 XXI FL FPGA IC IDE IIR LCO LMS LS LTI MA MLBS MOSFET MSE PD PEF PI PID PRBS RLS SI SMPC ZOH Fuzzy logic Field Programmable Gate Array Itegrated Circuit Itegrated Developmet Eviromet Ifiite Impulse Respose Limit Cycle Oscillatio Least Mea Square Least Square Liear Time Ivariat Movig Average Maximum Legth Pseudo Biary Sequece Metal Oxide Semicoductor Field-Effect Trasistor Mea Square Error Proportioal-Derivative Predictio Error Filter Proportioal-Itegral Proportioal-Itegral-Derivative Pseudo Radom Biary Sequece Recursive Least Square System Idetificatio Switch Mode Power Coverter Zero-Order-Hold

22 XXII LIST OF SYMBOL µ Step size C d e p f o f s i L i o K D K I K P L M p Q t r T sw Capacitor Cotrol sigal Predictio error Corer frequecy Samplig frequecy Iductor curret Load curret Derivative gai Itegral gai Proportioal gai Iductor Maximum overshoot Quality Factor Time rise Switchig time

23 XXIII v C V i v L v o V ref ŵ ŷ Δ PRBS θ λ φ Capacitor voltage Iput voltage Iductor voltage Output voltage Referece voltage Estimated filter weight Estimated output PRBS amplitude Parameters vector Forgettig factor Regressio vector

24 Chapter : Itroductio ad Scope of the Thesis Chapter INTRODUCTION AND SCOPE OF THE THESIS. Itroductio May classical cotrol schemes for switch mode power coverters SMPCs suffer from iaccuracies i the desig of the cotroller. This may be due to poor kowledge of the load characteristics, or uexpected exteral disturbaces i the system. I additio, SMPC ucertaities such as compoet toleraces, upredictable load chages, chages i ambiet coditios, ad ageig effects, all affect the performace of the cotroller over time [, 2]. Cosequetly, greater cosideratio should be give to the desig of the cotroller to accommodate these ucertaities i the system. Therefore, a itermediate process is required to explicitly determie the parameters of the power coverter ad to estimate the dyamic characteristics of the SMPC. This process ca be achieved by system idetificatio algorithms. Also, i SMPC applicatios, ofte a classical Proportioal-Itegral-Derivative PID cotroller is employed usig fixed cotroller gais. I such systems, the fixed cotrol loop is uable to cosider parameter chages that may occur durig the ormal operatio of the plat. Ultimately, this limits the stability margis, robustess, ad dyamic performace of the cotrol system [3]. For this reaso, more advaced auto-tuig ad adaptive digital cotrollers are ow playig a icreasigly importat role i SMPC systems. With the advet of developmets i digital cotrol techiques, itelliget ad advaced cotrol algorithms ca ow readily be icorporated ito the digital based systems to sigificatly improve the overall dyamic performace of the process. O-lie

25 Chapter : Itroductio ad Scope of the Thesis 2 idetificatio, system moitorig, adaptive ad self-tuig cotrollers are some of the most attractive features of digital cotrol systems. These itelliget algorithms, which are well suited to SMPC applicatios, allow more optimised cotrol desigs to be realised [2, 4] ad ca rapidly adjust cotroller settigs i respose to system parameter variatio. Clearly, a accurate model is required trasfer fuctio, state space, ad therefore excellet estimatio of plat parameters is essetial. Here, the cotroller tuig is based upo o-lie system idetificatio techiques, ad therefore a discrete time trasfer fuctio of the SMPCs is ecessary for cotrol desig [5, 6]. This is particularly true i most adaptive ad self-tuig cotrollers which require system idetificatio to update the cotrol parameters. The fudametal priciple of system idetificatio ad parameter estimatio is to evaluate the parameters withi a trasfer fuctio which has a aalogous arragemet to the actual plat to be cotrolled. However, system idetificatio ad adaptive cotrollers are ot fully exploited i low cost, low power SMPCs due to the heavy computatioal burde they place upo the microprocessor platform. Complex algorithms ofte require higher performace hardware to implemet ad this is usually cost prohibitive i applicatios such as SMPCs [7]. Therefore, there is a requiremet to further research ad develop cost effective, computatioally light idetificatio ad adaptatio methods which offer accurate estimatio performace. Recet developmets i digital hardware; icludig microprocessors, microcotrollers, digital sigal processors DSP ad field programmable gate arrays FPGA, provide the ability to desig ad implemet a complex system at higher samplig rate, such as adaptive ad self-tuig cotrollers. However, the executio time of adaptive algorithms is depedet upo several factors: processor architectures, memory, data/address bus widths, clock rate, etc. Fortuately, the idustrial electroics compaies have bee attemptig to release adaptive ad self-tuig cotrollers i SMPC applicatios. The scheme of these cotrollers is based upo real time idetificatio ad system moitorig of SMPCs, usig ew microprocessor architecture; icludig multiprocessor cores Fig... As show i Fig.., the digitally cotrolled block-diagram of SMPCs is classified as a mixed sigal system. I this structure two kids of sigals are used: aalogue/digital

26 Chapter : Itroductio ad Scope of the Thesis 3 or discrete sigal. The aalogue system cosists of dc-dc power stage circuit, sesig/sigal coditioig circuit, ad gate drive circuit. The digital system cosists of digital compesator, a digital-pulse-width-modulatio DPWM circuit ad a aalogue-to-digital coverter ADC that provides a iterface betwee the digital ad aalogue domais. Gate Drive g t DC-DC Coverter v o t Aalogue System Sigal Coditioig ad Sesig v sesig t c t DPWM d Core Microprocessor Digital Cotrol e A/D v o V ref + System Bus Self-Tuig ad Adaptive Cotroller/ System Idetificatio No-Liear Compesatio Core 2 Microprocessor Microprocessor uit Cotrol Uit Fig.. Dual core microprocessor ad digital cotrol architecture for SMPCs The ew cofiguratio of Power Electroics Maagemet PEM will icrease the performace of the microprocessor without icreasig the power cosumptio. Here, the tasks are divided betwee the two processor cores. The first microprocessor core is desiged for simple cotrol regulatio such as a covetioal digital PID cotrol. The secod microprocessor core provides advaced cotrol implemetatio, for istace adaptive ad system idetificatio algorithm. I some PEM uits, o-liear cotrol techiques have also bee itroduced i the secod microprocessor core to further improve the trasiet characteristics of the system. As illustrative examples, POWERVATION creates a dual core PEM-IC PV3002. This IC is capable of tuig the cotroller gais at load curret variatios, ad at circuit parameters chage

27 Chapter : Itroductio ad Scope of the Thesis 4 output capacitor/iductor based o cycle-by-cycle output voltage moitorig. The PV3002 icludes several aalogue circuits, DSPs, ad a reduced istructio set computig RISC microprocessor [8, 9]. INTERSIL Zilker Labs desiged a digital adaptive cotroller IC, amely the ZL600. This processor ca compesate the feedback loop automatically to produce optimal cotroller performace durig output load chages. A o-liear cotroller utilises this architecture to further improve the dyamic respose i the evet of abrupt load chage [0]. I aother example from TEXAS INSTRUMENTS TI, the attractive features of system idetificatio have bee used for the purpose of moitorig the performace of SMPCs, ad to update the feedback cotrol loop. I this device UCD9240 o-liear gais have bee augmeted to further improve the dyamic behaviour of the system [, 2]..2 Scope ad Cotributio of the Thesis Recet advaces i microprocessor techology ad cotiual price improvemet ow allows for more advaced sigal processig algorithms to be implemeted i may idustrial ad commercial products, cost ad complexity are clearly a major cocer. For this reaso, the aim of this thesis is to research ew practical solutios for system idetificatio ad adaptive cotrol that ca easily be developed i low complexity systems, whilst maitaiig the performace of covetioal algorithms. Particular attetio is give to parametric estimatio ad self-compesator desig of switch mode dc-dc power coverters. I this thesis, the work is applied to a small sychroous dc-dc buck coverter. However, the proposed techiques are trasferable to other applicatios. I order to quickly ad accurately idetify the system dyamics of a SMPC, a ew adaptive method kow as Dichotomous Coordiate Descet-Recursive-Least-Square DCD-RLS algorithm is proposed. A equatio error IIR adaptive filter scheme is developed alog with the DCD-RLS algorithm for system modellig of dc-dc SMPC. The desig ad implemetatio of the proposed DCD-RLS techique is preseted i detail, ad results are compared ad verified agaist classical techiques RLS. A major coclusio from the work is that the DCD-RLS ca achieve similar estimatio performace to the classic RLS techique, but with a lighter computatioal burde o the microprocessor platform. The proposed scheme has successfully bee preseted

28 Chapter : Itroductio ad Scope of the Thesis 5 by the author i [3]. I additio, a ehacemet o the scheme is suggested by employig a variable forgettig factor based fuzzy logic algorithm for the idetificatio of the SMPC parameters. The cocept of this scheme is preseted i the thesis ad the advatages it delivers are discussed. The simulatio results for the proposed adaptive forgettig factor with fuzzy logic scheme has bee published by the author i [4]. System idetificatio is a first step to developig adaptive ad self-tuig cotrollers. Therefore, the computatio complexity of these structures is typically very high. Furthermore, i order to achieve a good quality, dyamic closed loop cotrol system, the ukow parameters of the plat should be estimated quickly ad accurately. With these issues i mid; this thesis presets a ew alterative adaptive scheme that does ot deped etirely o estimatig the plat parameters. This scheme is based o adaptive sigal processig techiques which are suitable for both predictio/idetificatio ad cotroller adaptatio. Importatly, ad explaied i detail i this thesis, the method the use of a adaptive predictio error filter PEF as a mai cotrol i the feedback loop. A two stage/oe-tap FIR adaptive PEF is placed i parallel with a covetioal itegral cotroller to produce a adaptive Proportioal-Derivative + Itegral PD+I cotroller. The DCD-RLS algorithm is icorporated ito the PD+I cotroller for real time estimatio of the PEF tap-weights ad for reducig the computatioal complexity of the classical RLS algorithms for efficiet hardware implemetatio. Simulatio ad experimets results of the proposed scheme have bee published by the author i [5, 6]. The mathematical aalysis ad cocept of usig a adaptive PEF for adaptive cotrol, ad the relatioship betwee a adaptive PEF ad a Proportioal-Derivative PD cotroller, are clearly described by the author i the thesis ad have bee published i [7]. I summary, the mai objectives ad cotributios of this research are: To propose a ovel method, based o the DCD algorithm, for o-lie system idetificatio of dc-dc coverters. Applicatio of the DCD-RLS algorithm to reduce computatio complexity compared to classical methods RLS.

29 Chapter : Itroductio ad Scope of the Thesis 6 To develop a equatio error IIR adaptive filter for system modellig of dc-dc coverters based upo the DCD-RLS algorithm. To apply a adaptive forgettig factor strategy to track the time varyig parameters of SMPCs usig a fuzzy logic approach. To develop a ew adaptive cotroller for SMPCs based upo a FIR predictio error filter usig DCD-RLS ad LMS adaptive algorithms. To experimetally assess the performace of the proposed adaptive DCD-RLS algorithm usig a Texas Istrumets TMS320F28335 DSP platform ad sychroous dc-dc buck coverter..3 Publicatios Arisig from this Research The research i this thesis has resulted i umber of jourals ad iteratioal coferece publicatios. These articles are listed below: - M. Algreer, M. Armstrog, ad D. Giaouris, Active O-Lie System Idetificatio of Switch Mode DC-DC Power Coverter Based o Efficiet Recursive DCD-IIR Adaptive Filter, IEEE Trasactios o Power Electroics, vol.27, pp , Nov M. Algreer, M. Armstrog, ad D. Giaouris, Adaptive PD+I Cotrol of a Switch Mode DC-DC Power Coverter Usig a Recursive FIR Predictor, IEEE Trasactios o Idustry Applicatios, vol.47, pp ,oct M. Algreer, M. Armstrog, ad D. Giaouris, Predictive PID Cotroller for DC-DC Coverters Usig a Adaptive Predictio Error Filter, i Proc. IET Iteratioal Cof. o Power Electro., Machies ad Drives, PEMD 202, vol. 202, Bristol, Uited Kigdom. 4- M. Algreer, M. Armstrog, ad D. Giaouris, Adaptive Cotrol of a Switch Mode DC-DC Power Coverter Usig a Recursive FIR Predictor, i Proc. IET Iteratioal Cof. o Power Electro., Machies ad Drives, PEMD 200, vol. 200, Brighto, Uited Kigdom.

30 Chapter : Itroductio ad Scope of the Thesis 7 5- M. Algreer, M. Armstrog, ad D. Giaouris, "System Idetificatio of PWM DC-DC Coverters durig Abrupt Load Chages," i Proc. IEEE Idustrial Electro. Cof., IECON'09, 2009, pp , Porto, Portugal..4 Layout of the Thesis The thesis is orgaised ito 7 chapters as follow: Chapter 2 presets the modellig ad cotrol of dc-dc power coverters. This icludes the commo circuit topologies of dc-dc coverters with more emphasis o operatio ad circuit cofiguratio of buck dc-dc switch mode power coverters. It also provides details o derivatio of the cotiuous state space model, followed by details o average ad discrete models of buck dc-dc coverter. A digital voltage mode cotrol structure is itroduced i this chapter; sub-circuit blocks are also explaied. I the digital cotrol sectio, two techiques of digital compesator are discussed icludig the pole-zero cacellatio method ad pole-placemet approach. The modellig ad cotrol i this chapter will be used to evaluate the proposed algorithms. Chapter 3 provides details o the priciples ad techiques used i system idetificatio. Differet commo models of parametric estimatio techiques are also demostrated. I additio, it outlies basic iformatio o adaptive cotrol ad adaptive filter techiques. Recet publicatios o system idetificatio/adaptive cotrol techiques for dc-dc SMPCs are also reviewed i this chapter. Chapter 4 presets details o the derivatio of the classical LS ad RLS algorithms. I additio, it briefly explais the system idetificatio paradigm based adaptive filter techique. The proposed o-lie system idetificatio scheme for SMPC is also described i this chapter. This is followed by i-depth aalyses ad derivatio of the ew DCD-RLS adaptive algorithm alog with equatio error IIR adaptive filter structure. Each sub block i the o-lie system idetificatio structure is explaied. Furthermore, Chapter 4 explores a ew adaptive forgettig factor based fuzzy logic system to detect ad estimate the fast chage i the system via sudde chage i predictio error sigal. The ew idetificatio schemes i this chapter are comprehesively tested ad validate through simulatios.

31 Chapter : Itroductio ad Scope of the Thesis 8 Chapter 5 presets the proposed adaptive cotroller. The first part of this chapter provides details o the priciple of how a adaptive PEF filter ca be employed as a cetral cotroller i the feedback loop of a closed loop system. Followig this, a overview of auto-regressive ad movig average filters is preseted alog with the derivatio of the Least-Mea-Square LMS adaptive algorithm. I additio, Chapter 5 demostrates the effectiveess of the DCD-RLS adaptive algorithm to improve the dyamics performace of the proposed adaptive scheme. Robustess ad stability aalysis of the proposed cotroller is discussed. Extesive simulatio results that compare the proposed adaptive cotrol based upo DCD-RLS with classical LMS are provided i this chapter. Chapter 6 focuses o the experimetal validatio of the developed adaptive algorithms usig a high speed microprocessor board. It provides a overview o the architecture of the selected digital sigal processor platform. I additio, this chapter explais the practical circuit diagram of the costructed dc-dc buck coverter ad the experimetal setup. Importatly, Chapter 6 cocetrates o practical evaluatio of the proposed system idetificatio algorithm ad adaptive cotroller structure. It also provides a compariso betwee the obtaied experimetal results of the proposed scheme usig the DCD-RLS algorithm ad the classical RLS/LMS algorithms, as well as with the covetioal digital PID cotroller. Fially, Chapter 7 presets the coclusio draw for this thesis ad it summarises possible suggestios for future work..5 Notatios I this thesis the matrices ad vectors are represeted by bold upper case ad bold lower case characters respectively. As a illustrative example, R ad r. The elemets of the matrix ad vector are deoted as R i,i ad r i. The i-th colum of R is deoted as R i. Fially, variable is used as a time idex, for istace β is the vector β at time istat.

32 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 9 Chapter 2 DC-DC SWITCH MODE POWER CONVERTERS MODELLING AND CONTROL 2. Itroductio DC-DC SMPCs are extesively used i a wide rage of electrical ad electroic systems, with varyig power levels typically mw-mw applicatios. Some illustrative examples are power supplies i persoal/laptop computers, telecommuicatios devices, motor drives, ad aerospace systems. These applicatios require SMPCs with a high performace voltage regulatio durig static ad dyamic operatios, high efficiecy, low cost, small size/lightweight, ad reliability [8-20]. The mai role of dc-dc coverters is to covert the uregulated DC iput voltage ito a differet regulated level of DC output voltage. I geeral, a dc-dc coverter ca be described as a aalogue power processig device that cotais a umber of passive compoets combied with semicoductor devices diodes ad electroics switches to produce a regulated DC output voltage that has a differet magitude from the DC iput voltage. Some examples refer to the power supply of the microprocessor ad other itegrated circuits that require a low regulated DC voltage betwee 3.3 V ad 5 V. This voltage is resultat from the reductio of the high DC voltage geerated from a AC-to-DC power rectifier [8]. 2.2 DC-DC Circuit Topologies ad Operatio Cofigurig the compoets of dc-dc coverters i differet ways will lead to the formig of various power circuit topologies Fig. 2.. All of the circuit topologies have the same types of compoets icludig capacitor C, iductor L, load resistor

33 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 0 R o, ad the lossless semicoductor compoets. The selectio of the topology is maily depedet o the desired level of regulated voltage, sice the dc-dc coverters are applied to produce a regulated DC voltage with a DC level differet from the iput DC voltage. This level ca be higher or lower tha the DC iput voltage. However, the most widely used SMPCs are kow as: buck coverter, boost coverter ad buck-boost coverter. A dc-dc buck coverter is cofigured to geerate a DC output voltage lower tha the iput voltage, Fig. 2.a. Coversely, a dc-dc boost coverter is utilised to provide a DC output higher tha the applied iput voltage, as show i Fig. 2.b. Fially, a dc-dc buck-boost coverter is able to produce two levels of DC output voltage; these levels ca either be lower or higher tha the DC iput voltage [9]. See Fig. 2.c. V i I i R L L i L R C i C i o v o C R o a V i V i R L L v o v o R C R L RC C R o L C R o b c Fig. 2. Most commo dc-dc coverter topologies, a: buck coverter, b: boost coverter, c: buck-boost coverter

34 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 2.2. DC-DC Buck Coverter Priciple of Operatio The buck coverter is employed to step dow the iput voltage V i ito a lower output voltage V o. This ca be achieved by cotrollig the operatio of the power switches e.g. MOSFET, usually by usig a PWM sigal. Accordigly, the states of the switch O/Off are chaged periodically with a period equal to T sw switchig period ad coversio ratio duty-cycle equal to D. The level of the coverted DC voltage is based o the magitude of the applied iput voltage ad the duty ratio. Durig the steady-state, the duty cycle is calculated by D = V o / V i [9]. The, the L- C low pass filter removes the switchig harmoics from the applied iput sigal. I practice, to deliver a smooth DC voltage to the coected load, the selected corer frequecy of this filter should be much lower tha the switchig frequecy f sw of the buck coverter [8]. This corer frequecy is defied as: f o 2 LC 2. Two switchig states are apparet durig each switch period. The first state is whe the switch is O ad the diode is Off. At this state, the iput voltage will pass eergy to the load through the iductor ad the storage elemets start to charge. The secod state is whe the switch is Off ad the diode is O; the the stored eergy will discharge through the diode. This operatio is kow as a Cotiuous Coductio Mode CCM. I CCM the iductor curret will ot drop to zero durig switchig states, whilst i secod operatio mode which is Discotiuous Coductio Mode DCM, the iductor curret drops to zero before the ed of the switchig iterval. As a result, a third switchig state is itroduced durig the switchig period. I this state, the iductor curret drops ad remais at zeros while both the diode ad switch are Off durig the operatio iterval [9]. 2.3 DC-DC Buck Coverter Modellig I order to desig a appropriate feedback cotroller, it is essetial to defie the model of the system. Accordigly, this sectio presets the details of aalysis ad modellig of the dc-dc coverter. This research focuses o modellig ad cotrol of the sychroous dc-dc buck coverter, as this topology is widely used i idustrial

35 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 2 ad commercial products [0, 2]. I sychroous dc-dc buck coverter the freewheel diode is replaced by aother MOSFET device. A poit of load POL coverter is oe of the applicatios that utilises this kid of topology. As previously metioed, there are two itervals per switchig cycle. The switchig period is defied as the sum of the O ad Off itervals T sw = T o + T off. The ratio of the T o iterval to the switch period is kow as the duty ratio or duty cycle D = T o / T sw. I the steadystate operatio, the output voltage ca be computed i terms of duty cycle. The buck dc-dc coverter produces a lower output voltage compared with the iput voltage 2.2. As expressed i 2.2, the variatio of the output voltage magitude is cotrolled by the T o duratio or duty cycle value. The PWM sigal is used to cotrol the output voltage level [9]. V o T T o sw V i DV i 2.2 Durig the T o duratio, the circuit diagram of the buck coverter ca simply be depicted as i Fig. 2.2a. A set of differetial equatios are derived to describe this period of operatio: di L dt L dv C dt v o C V i C i L L RL RC il vc RCio i o o i L R i i v v R C o o R C dv C dt C v C Geerally, the dc-dc coverter model is defied by state-space matrices [2]: x Ax t BV i 2.6 y C x t E V i Here, A, B, C, ad E are the system matrices/vectors durig the O iterval, y is the output, ad xt is the capacitor voltage ad iductor curret state vector:.

36 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 3 By substitutig equatio 2.4 ito 2.5 ad solvig with respect to the output voltage v o, the output vector ca be writte i state space matrix form as: L C C o C o C o o i v R R R R R R R C x y 2.7 Now, isertig equatios ito 2.6, the O state space matrix A ad vector B ca be expressed as [2]: L R R R R R L L R R R R R R C R R C C o C o L C o o C o o C o 0, A B 2.8 V i L C i o R o i L ic R L R C vc + v o L C i o R o i L ic R L R C vc + v o a b Fig. 2.2 Buck coverter circuit cofiguratio, a: O state iterval, b: Off state iterval I the secod iterval, durig the T off duratio, the system equatios of the buck coverter have the same form with T o iterval. The oly differece betwee the O ad Off duratio is the B vector 2.9. Fig. 2.2b presets the circuit diagram of the buck coverter durig the Off iterval. 0, 0, 0, E E C C B B A A C o C o C o o R R R R R R R L 2.9

37 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 4 Fially, the state space matrices durig Off duratio ca be writte as: x A2x t B2Vi 2.0 y C 2 x t E 2 V i 2.4 Model Simulatio To ivestigate the behaviour of the aforemetioed buck model, the derived differetial equatios preseted i sectio 2.3 have bee simulated usig MATLAB/Simulik. The power load of the desiged dc-dc buck coverter is for 5 W operatios. The followig circuit parameters are used: L = 220 µh, C = 330 µf, R o = 5 Ω, R L = 63 mω, R C = 25 mω, V i = 0 V, ad the switchig frequecy is 20 khz. These parameters are calculated usig desig otes available from Microchip TM [22]. Fig. 2.3 ad Fig. 2.4 shows the ope loop output voltage ad iductor curret at 33% duty-cycle ad V i = 0 V. As displayed i the waveforms of Fig. 2.3 ad Fig. 2.4, the steady state DC output voltage ad the iductor are evidetly cotet periodic ripples that are repeated at each switchig period. Normally, the power stage elemets L, C determie the magitude of the ripple as show i the waveforms Time s Fig. 2.3 Ope loop steady state output voltage

38 Chapter 2: DC-DC SMPCs Modellig ad Cotrol Times Fig. 2.4 Ope loop steady state iductor curret 2.5 Buck State Space Average Model The state space average model is the most commo approach to obtai the liear time ivariat LTI system of SMPC. The strategy starts by averagig the coverter s waveforms iductor curret ad capacitor voltage over oe switchig period to produce the equivalet state space model. I this way, the switchig ripples i the iductor curret ad capacitor voltage waveforms will be removed [23]. As demostrated i the previous sectio, there are two LTI differetial equatios to describe the operatio of buck dc-dc coverter O ad Off itervals. By averagig these two state itervals, the state space average model ca be obtaied. This is achieved by multiplyig the O iterval 2.6 by dt ad the Off iterval 2.0 by Off time duratio [d`t = dt]. This yields the followig state space average model [8]: x y t d t A d t A x t d t B d t d t C d t C x t d t E d t 2 2 B 2 E V i 2 V i 2. where, d deotes the O time legth. Oce the average state space model of the buck coverter is defied, it is possible to apply the Laplace trasform for obtaiig the frequecy domai liear time model.

39 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 6 This model is essetial i the liear feedback cotrol desig, such as the root locus cotrol approach. I voltage mode cotrol of the SMPC, the cotrol-to-output voltage trasfer fuctio 2.2 [24, 25] plays the importat role of describig the locatios of poles/zeros for optimal voltage respose. The cotrol-to-output model ca be computed by applyig the Laplace trasform to the small sigal average model of SMPC i equatio 2. ad the solvig the system with respect to output voltage. This research is primarily focused to utilise this model i the system idetificatio ad the power coverter cotrol desig. 2 L o L o L o C L o C o C i dv R R L R R R R C C R s R R R R LC s s CR V s G 2.2 As expressed i 2.2 the cotrol-to-output trasfer fuctio of the buck SMPC exhibits a geeral form of secod order trasfer fuctio ad geerally it ca be writte as [, 8]: 2 o o zesr o dv w s Qw s w s G s G 2.3 where, the corer frequecy w o of the buck coverter, the quality factor Q, the zero frequecy w zesr, ad the dc gai G o ca be defied as follows [26]: C zesr i o L o L o L o C o C o L o o CR w D Vo V G R R C R R R R L C R w Q R R LC R R w 2.4

40 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 7 From equatio 2.3, it ca be observed that the cotrol-to-output voltage trasfer fuctio of the buck coverter cotais two poles ad oe zero. The locatios of the poles as well as the dyamic behaviour of the dc-dc coverter are maily depedet upo the quality factor Q ad the agular resoat frequecy w o of the coverter. I the time domai, the quality factor gives idicatio of the amout of overshoot that occurs durig a trasiet respose. This factor is iversely related to the dampig ratio ξ of the system [27, 28]: M p / 2Q e 4Q2, Q Here, M P is the maximum peak value. It is worth otig that a o-egligible resistace of the output capacitor R C of the dc-dc coverter itroduces a zero i the cotrol-to-output voltage trasfer fuctio of the SMPC as give i 2.3. The locatio of this zero has a egative impact o the dyamic behaviour of the SMPC. I order to cacel the effect of this zero ad improve the system performace, a costat pole i the cotrol loop may be added. This pole ca be placed at the same value as the ESR zero. 2.6 Discrete Time Modellig of Buck SMPC I order to derive the discrete model of SMPC, the cotiuous time dyamic model i 2.6 ad 2.0 should first be defied. The, by samplig the states of the coverter at each time istat, the cotiuous time differetial equatios are trasformed ito a discrete time model. A discrete time model is ecessary for digital implemetatio of the algorithms. I the literature, differet techiques have bee proposed for discrete time modellig of dc-dc coverters ad for obtaiig the cotrol-to-output trasfer fuctio [2, 29]. However, these techiques icludig the direct trasformatio methods biliear trasformatio, zero-order-hold trasformatio, pole-zero matchig trasformatio, etc. from s-to-z domai are geerally describe the buck SMPC as a secod order IIR filter 2.6, for example the literature that have bee preseted i [, 5, 2, 30-33].

41 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 8 G dv b z z a z b z 2 a 2 2 z 2 b N a z M N z M, N M However, a zero-order-hold ZOH trasformatio approach is preferred for discrete time modellig of the cotrol-to-output trasfer fuctio 2.7. Practically, the sampled data sigals are acquired based o sample ad hold process followed by A/D operatio. I additio, the cotrol sigal remais costat held durig the samplig iterval ad is modified at the begiig of each updated cycle [30]. Therefore, both the cotrol ad output sigals are based o ZOH operatio. Cosequetly, a ZOH trasformatio method is utilised i this work. The authors i [30] ad [3] use the ZOH trasformatio method to model the G dv z ad the to be used i the system idetificatio process. Recetly, system idetificatio techiques have bee extesively used i dc-dc coverters for discrete time modellig of small sigal cotrol-to-output trasfer fuctio. This is typically accomplished by superimposig the duty commad with a small amplitude sigal. The frequecy compoets ad the amplitude are the estimated through differet idetificatio methods. Fially, the frequecy respose cotrol-to-output LTI trasfer fuctio ca be costructed. Other approaches ivolve by directly idetifyig the z-domai trasfer fuctio usig differet parametric idetificatio techiques such as the RLS algorithm. G dv z z Gdv s 2.7 Z s 2.7 Digital Cotrol Architecture for PWM DC-DC Power Coverters Digital cotrollers have bee icreasigly used i differet fields ad have recetly become widely utilised i the cotrol desig of SMPCs. The use of digital cotrollers ca sigificatly improve the performace characteristic of dc-dc coverters for several reasos. Firstly, digital cotrollers provided more flexibility i the desig compared with the aalogue cotrollers. Secodly, they ca be implemeted with a small umber of passive compoets, which reduce the size ad cost of desig. Also, digital cotrollers have low sesitivity o exteral disturbaces ad system parameter

42 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 9 variatios. I additio, digital cotrollers are easy ad fast to desig, as well as to modify or chage the cotrol structures or algorithms. Furthermore, it eables advace cotrol algorithms to be implemeted, such as o-liear cotrol, adaptive cotrol, ad system idetificatio algorithms. Fially, programmability; the algorithms ca easily be chaged ad reprogrammed [34-36]. O the other had, the power processig speed is faster i a aalogue cotroller tha i a digital cotroller; this is due to the limitatios i the microprocessors speeds. Furthermore, the system badwidth is higher i aalogue desig compared with the digital desig. I additio, o quatisatio effects are cosidered i aalogue systems [37, 38]. However, i order to stabilise the output voltage at the desired level, the cotrol sigal must be varied ad accommodate ay chages i the system, such as load chages or the variatios i the iput voltage. This ca be performed by desigig a appropriate feedback cotroller for appropriate cotrol sigal geeratio. There are two commo cotrol structures applied i the closed loop cotrol desig of the dc-dc power coverters: voltage mode cotrol ad curret-mode cotrol. Digital voltage mode cotrollers are mostly used ad preferred i the idustry over curret-mode cotrollers [0-2]. This is because the curret-mode cotrollers require a additioal sigal coditio circuit, cosistig of a high speed curret sesor; i cosequece this will icur extra costs to the system [39]. I additio, a voltage mode cotrol is simple to desig. Therefore, this research will cocetrate o the desig ad implemetatio of the digital voltage mode cotrol for SMPCs.

43 Chapter 2: DC-DC SMPCs Modellig ad Cotrol Digital Voltage Mode Cotrol As illustrated i Fig. 2.5, the digitally cotrolled voltage mode scheme of SMPCs is divided ito six sub circuit blocks. These circuits are categorised ito two parts. The first part defies as a aalogue system, icludig the dc-dc power processor stage, the gate drive, ad the sesig/sigal coditioig circuits. The secod part classifies as the digital system, which is represeted by the digital cotroller, ad DPWM. The ADC block ca be described as a mixed sigal device. Gate Drive g t DC-DC Coverter v o t Aalogue part Sigal Coditioig ad Sesig v sesig t Hs A/D c t DPWM d Digital Cotrol v o e V ref + Digital part \ Microprocessor uit Fig. 2.5 Digital voltage mode cotrol architecture of DC-DC SMPC The output voltage geerated from the dc-dc power coverter is firstly sesed ad scaled via a commoly used resistive voltage divider circuit with gai factor equal to H s. Hece, ay sesed voltage higher tha the ADC full dyamic scale must be atteuated by a factor to be processed withi the desired rage. Other sigal coditioig circuits ca also be cosidered for suitable iterfacig with ADCs. This icludes differet aalogue circuits such as buffer circuits with wide badwidth operatio. A ati-aliasig filter is ofte used to filter the frequecy cotet i the output voltage that is above half of the ADC samplig frequecy Nyquist criteria []. Typically, this would be a low-pass filter.

44 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 2 The sesed output voltage v sesig is digitised by the ADC. I digital cotrol desig for SMPC, there are two factors that must first be cosidered for the appropriate selectio of a ADC: The A/D umber of bits or A/D resolutio. This is importat to the static ad dyamic respose of the cotrolled voltage of SPMC. The A/D resolutio has to be less tha the allowed variatio i the sesed output voltage [40, 4]. 2 The coversio time is a importat factor i the selectio of ADC as it dictates the maximum samplig rate of the ADC. I digitally cotrolled SMPCs, the coversio time is required to be small eough to achieve a fast respose ad high dyamic performace. Typically, the samplig time of a ADC is chose to be equal to the switchig frequecy of the SMPC. This will esure that the cotrol sigal is updated at each switchig cycle. The digital referece sigal, V ref is compared with the scaled sampled output voltage, v o. The resultat error voltage sigal, e, is the processed by the digital cotroller via its sigal processig algorithm. A secod order IIR filter is used as a liear cotroller that govers the output voltage of the SMPC as described i 2.8 ad show i Fig. 2.6 [20]. Geerally, this IIR filter performs as a digital PID compesator as a cetral cotroller i the feedback loop. Both o-liear cotrol ad itelliget cotrol techiques ca also be applied for the digital cotrol of SMPCs [24, 42-45]. N i q i z i0 Gc z M k sk z k 2.8 However, the cotrol sigal, d, is the computed o cycle-by-cycle basis. The desired duty ratio, ct, of the PWM is produced by comparig the discrete cotrol sigal with the discrete ramp sigal; i the digital domai it is represeted as a digital couter. Here, the DPWM performs as a iterface circuit betwee the digital ad aalogue domais of the digitally cotrolled architecture withi the SMPC,

45 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 22 simulatig the purpose of the digital-to-aalogue coverter DAC. Fially, the geerated O/Off commad sigal across the DPWM is amplified by the gate drive circuit. The output of the gate sigal is the used to activate the power switches of the SMPC. e q d z - e- q s d- z - z - e-2 q 2 -s 2 d-2 z - Fig. 2.6 Two-poles / Two-zeros IIR digital cotroller It is worth otig that a high resolutio DPWM is essetial for the digital cotrol of SMPCs. This will lead to accurate voltage regulatio ad avoid the limit cycle oscillatio pheomeo. Limit cycles are defied as o-liear pheomea that occur i digital cotrol of dc-dc coverters durig steady-state periods. I accordace to [46], the udesirable limit cycle oscillatios i digitally cotrolled dc-dc coverters ca be avoided whe the DPWM resolutio is greater tha the ADC resolutio. Therefore, i order to elimiate the limit cycle oscillatios, the resolutio of DPWM has to be at least oe bit greater tha the ADC resolutio [46]. Also, care is required i the selectio of the itegral gai i PID cotrollers, as excessively high values of itegral gai ca cause limit cycle oscillatios aroud the steady-state value. For more rigorous details ad aalysis of the limit cycle oscillatio, the reader should refer to the work preseted by Peterchev ad Saders [46]. 2.8 Digital Proportioal-Itegral-Derivative Cotrol The digital PID cotroller is well kow ad it is commoly used i cotrol loop desig of SMPCs [47]. This is because the PID cotrol parameters are easy to tue ad the desiged cotroller is easy to implemet. Geerally, the discrete PID cotroller ca be described as give by 2.9 [48]. Here, the PID cotroller is i

46 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 23 parallel form structure, where the cotrol actio is divided ito three cotrol sigals as show i 2.20 ad the PID gais ca be tued idepedetly. z K z K K z E z D z G D I P c 2.9 d d d d D I P 2.20 where: e e K d d e K d e K d D D I I I p p 2.2 The variables K P, K I, ad K D, are the proportioal-itegral-derivative gais of PID cotroller, e is the error sigal [e = V ref v o ], ad d is the cotrol actio. From 2.9, the discrete time domai of the PID cotroller ca be described as show i Fig. 2.7 ad give i 2.22 ad 2.23: 2 2 e q e q e q d d o 2.22 D D P D I P o K q K K q K K K q z - e e- e-2 q 0 d z - z - q q 2 Fig. 2.7 Digital PID compesator

47 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 24 System performace, loop badwidth, phase margi ad gai margi are determied based o PID coefficiets. For example, decreasig the steady-state error is achieved by the itegral gai K I. However, the itegral part will add a pole at the origi to the ope loop trasfer fuctio of the system. This pole requires more cosideratio i the cotrol loop desig to esure the system stability. I the frequecy domai, the itegral part acts as a low-pass filter, which makes the system less susceptible to oise. However, it adds a phase-lag to the system, which reduces the phase margi of the cotrol loop, thus more oscillatios ca be observed i the output respose [49, 50]. Therefore, the derivative part should be itroduced i the cotrol loop to icrease the phase margi phase-lead. This i tur leads to a improvemet to the stability of the system ad ehace the dyamic performace [5]. The derivative cotroller is resposible for the rate of chage of the error sigal. For istace, if the sesed output voltage of SMPC reaches the desired set poit quickly, the the derivative part slows the rate of the chage i the output cotrol actio [49]. Therefore, the derivative part ca be cosidered as a itelliget part of the PID cotroller. However, the derivative part is more sesitive to the oise i the system [5], therefore the derivatio of the error sigal will amplify the oise i the cotrol loop. Now, the proportioal gai makes the output of the PID cotroller respod to ay chage of the error sigal. For example, a small chage i the error sigal at high value of K P results i a large chage i the cotrol actio. I summary, the PID cotroller has the same scheme fuctioality of a phase lead-lag compesator [49, 50]. The parameters of the PID cotroller ca be determied directly or idirectly. I the direct method, the discrete time model of SMPC ad the PID cotroller are used, thus all the calculatios are obtaied i the z-domai. Therefore, a more accurate cotrol loop ca be achieved, where the errors related to the trasformatio approximatio from the s-to-z domais are avoided i this approach [, 5]. I the idirect approach, a cotiuous time domai of SMPC is utilised ad the PID cotroller is desiged i the s-domai. Differet trasformatio methods ca be applied to trasfer the PID cotroller from the cotiuous domai to the discrete domai s-to-z, such as the biliear trasform method, the backward Euler method, ad the pole-zero cacellatio method. However, iaccuracy i system performace

48 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 25 will be icreased usig this techique. This is due to the trasformatio approximatio from s-to-z domai [52]. Dua et al. [37], demostrated a systematic evaluatio approach to compare the performace of the PID cotroller for SMPCs usig four types of discretisatio methods. The direct desig approach has also bee compared with the idirect method. It was discovered that that the direct method provides better performace compared with the idirect method. A similar coclusio was demostrated by Al-Atrash ad Batarseh [53]. I this research we are iterested i two approaches that are commoly used i the digitally cotrolled desig of SMPCs: the pole-zero matchig approach [40, 54-56], which provides a simple discrete time differece equatio [52], ad the systematic pole placemet method [47, 57-59] Digital Cotrol for Buck SMPC Based o PID Pole-Zero Cacellatio The desig method preseted i this sectio follows the same procedure demostrated i [26, 54, 55]. The desig starts from the cotiuous model of the buck dc-dc coverter as described i 2.3. I order to cacel the two poles of power coverter i 2.3, two zeros should be placed exactly at the same frequecies defied by w o of the dc-dc power coverter as give i equatio For simplicity of desig, we assumed that R C = 0: G s G c co s Qw o s s w o Therefore, the overall loop gai is reduced to oly oe pole at origi together with the dc gai: G G L s o co s 2.25 From 2.24, it ca be deduced that the desig of the PID compesator usig a pole-zero cacellatio techique requires the precise kowledge of the power coverter parameters, such as the quality factor ad coverter corer frequecy [33]. This ca be oe of the drawbacks of this method, where the effect of ay chage i

49 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 26 the dc-dc coverter parameters will directly ifluece the PID coefficiets ad i tur to the overall cotrol loop. Therefore, a accurate parameters estimatio is required for adequate cotrol desig [54]. For this reaso, the authors i [33, 54, 55] choose the quality factor as a fixed value. As show i 2.5, the quality factor is related to the dampig factor ξ. For a effective dampig respose, the dampig factor is varied betwee 0.6 ad.0 [28]. The resoat frequecy of PID zeros i 2.24 is approximated to be at the same value of power coverter corer frequecy. As a result, the compesator zeros are assiged close to the coverter poles; this will esure system robustess. As a result, the overall loop gai ca be writte as [33]: L s G G o co 2 s s wz wz s s s Qwo w o 2.26 Here, G co is the dc gai. This gai is selected to satisfy desig requiremets such as phase margi ad gai margi. The root-locus method ca be used to fid G co [55]. From [33, 54], the dc gai ca be determied directly based o the desired loop badwidth 2.27; i practice, the badwidth chose will be f b = f s /0 [33, 54]. G co 2 f G o b 2.27 Fially, by usig the pole-zero matchig trasformatio method the discrete PID gais described i 2.22 ca be determied i.e. q 0, q, ad q Simulatio desig of a buck SMPC based o PID pole-zero Cacellatio I order to evaluate the PID cacellatio method, the digital voltage mode cotrol of a sychroous dc-dc buck SMPC circuit is simulated Fig The circuit parameters of the buck coverter are as follows: L = 220 µh, C = 330 µf, R o = 5 Ω, R L = 63 mω, R C = 25 mω, V i = 0 V, the switchig frequecy is f sw = 20 khz, H s = 0.5, ad the samplig time T s = 50 μs f s = f sw. A dampig respose of ξ = 0.7 with the zero cetre frequecy is chose as w z w o rad / s. The dampig factor ad the zero cetre frequecy are the substituted ito equatio 2.24 to determie

50 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 27 the cotrol trasfer fuctio. The s-to-z based MATLAB pole-zero matched method is used to obtai the discrete PID cotroller coefficiets as writte i equatio Accordigly, the PID gais Fig. 2.7 are optimally tued to: q o = 4.27, q = 7.84, ad q 2 = d d 4.27e 7.84e 3.82e 2.28 Fig. 2.8 displays the frequecy respose of the cotrolled system; here it show that the phase margi of the compesated system is 4. o ad the gai margi is 2.6 db. Fig. 2.9 shows the root locus of the power coverter stage. The locatios of the PID roots are preseted i Fig. 2.0, ad the root locus cacellatio paths for the cotrol loop are illustrated i Fig. 2.. It ca be see that the two poles of the dc-dc coverter are cacelled with very short paths by the two matched zeros of the PID cotroller. The PID compesator is set to cotrol the buck coverter output voltage at 3.3 V. The trasiet behaviour of the system is examied by abruptly chagig the load of the SMPC. Fig. 2.2 demostrates the trasiet respose of the desiged PID compesator whe the load is rapidly switched betwee 0.66 A-to-.32 A. It ca be oted that there is a small overshoot i the system at step load chages, however the respose quickly recovers to the desired value; this verifies the successful desig of the digital compesator.

51 Imagiary Axis Phase deg Magitude db Chapter 2: DC-DC SMPCs Modellig ad Cotrol Loop Gais Buck Model PID Cotroller Frequecy Hz Fig. 2.8 Frequecy respose of the compesated ad ucompesated dc-dc buck SMPC e e+005 e+005 8e+004 6e+004 4e+004 2e Real Axis x 0 4 Fig. 2.9 Power stage root locus 0.95

52 Imagiary Axis secods Imagiary Axis Chapter 2: DC-DC SMPCs Modellig ad Cotrol e e+003.5e e e e+003 2e e Real Axis e Fig. 2.0 PID compesator root locus Real Axis secods - x 0 4 Fig. 2. Total loop gais root locus

53 Chapter 2: DC-DC SMPCs Modellig ad Cotrol Times a Times b Times c Fig. 2.2 Trasiet respose of the PID cotroller, a: output voltage, b: iductor curret, c: load curret. Load curret chage betwee 0.66 A ad.32 A every 5 ms

54 Chapter 2: DC-DC SMPCs Modellig ad Cotrol Pole Placemet PID Cotroller for DC-DC Buck SMPC I the pole placemet approach, a discrete cotrol-to-output model of the buck coverter is utilised 2.29 ad the digital PID cotroller ca be described as writte i 2.30 [60]. I this case, a two poles/two zeros discrete PID cotroller 2.30 will be itroduced for the digital cotrol of the buck dc-dc coverter. Equatio 2.3 represets the discrete differece equatio form of b z b 2z G dv z 2 az a2z 2 z 2z G z o c z z z z d oe e e 2 d d As show i Fig. 2.3, the closed loop cotrol trasfer fuctio ca be writte as follow [57, 60]: G L z B z z A z z B z z 2.32 V ref + e β z z B z A z v o Fig. 2.3 Closed loop cotrol of the buck SMPC The desired closed loop dyamic of the system ca be used to solve the relatio i the deomiator polyomial expressed i I this way, the locatios of the closed loop poles are set accordig to the desired values, ulike other cotrol techiques which required tuig of the cotrol coefficiets for acceptable respose [28]. The characteristics equatio of 2.32 ca be formulated as [57, 60]:

55 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 32 4, 2 2 d N N k N k k N d z d d z d z d z d d z z B z z A z D 2.33 I a secod order model, such as a dc-dc buck coverter, the secod order characteristic equatio [57, 58] is ofte utilised to describe the desired closed loop dyamics of the system: w s w s s G 2.34 Therefore, the dyamic characteristic of a closed loop cotrol may be give as i 2.35 [60]. As preseted i sectio 2.5 the dyamics behaviour is defied by the dampig factor ad the atural frequecy. These factors should be selected appropriately for better performace ad adequate dampig respose. s e d T w s e d T w s T w cos To determie the parameters of the cotrol system, the sets of liear algebra equatios are required. This ca be obtaied by rewritig equatio 2.33 i matrix form Thus, the parameters of the PID cotroller ca be solved as described i , N d a a a d a d a b a a b b a b b b 2.36

56 Chapter 2: DC-DC SMPCs Modellig ad Cotrol 33 ] ][ [ ] [ ] ][ [ b b a b b a b b r b d b d b b b a b a b b a s a b r s a a b b b a a d b o 2.37 It ca be oticed that the solutio of 2.36, ecessitates a matrix iversio operatio to fid the cotrol parameters. Cosequetly, a high computatioal load is ivolved with o-lie updates of the cotrol loop [57]. Therefore, the pole-placemet method is more applicable for off-lie cotrol desig. This is clearly demostrated by Shuibao et al. [58], where the off-lie desig based o pole-placemet approach is used to cotrol the SMPC. Kelly ad Rie [57] preseted a direct method to desig a digital cotrol of a dc-dc buck coverter based o pole-placemet techique. It was discovered that the zeros of the pole placemet cotroller ca oly be used to fully cotrol the dc-dc buck coverter. The resultat cotrol structure may be compared to a PD cotroller. Whilst this cotroller is computatioally efficiet, it actually oly applies a PD compesator which ca yield a o-zero steady-state error Simulatio desig of a buck SMPC based o pole-placemet PID cotroller Similar parameters to those outlied i sectio are chose for the SMPC circuit. The atural frequecy is selected to be twice the corer frequecy of the power coverter w = 2w o = 7447 rad/s, with dampig factor ξ = 0.7 [57]. By usig 2.35 ad 2.37, the PID parameters are: β o = 4.672, β = 7.539, β 2 = 3.84, ad α = Therefore, the discrete PID cotroller ca be give as: d d e e e d 2.38 Fig. 2.4 displays the frequecy respose of the cotrolled system; here it is show that the phase margi of the compesated system is 35.7 o ad the gai margi is 4.8

57 Phase deg Magitude db Chapter 2: DC-DC SMPCs Modellig ad Cotrol 34 db. It is importat to ote that a phase margi greater tha 40 o is essetial for a robust SMPC cotrol system [6]. Accordigly, more tuig steps are required to icrease the phase margi ad improve the badwidth of the closed loop system. To ivestigate the trasiet characteristic of the system, repetitive step load chages have bee applied to the dc-dc coverter. Fig. 2.5 presets the trasiet performace of the feedback system whe the curret load alterates betwee 0.66 A- to-.32 A. As expected from the frequecy respose results, a poorly dyamic respose will be observed by the desiged feedback cotroller. Fig. 2.6 compares the loop gais of the pole-placemet cotroller with the pole-zero cacellatio approach. Clearly, a pole-zero cacellatio compesator achieves a higher phase margi ad loop badwidth compared with the pole-placemet compesator. As a result, a better respose is achieved with the pole-zero method, which demostrates a smaller overshoot ad udershoot o the output voltage, as well as a faster recovery time observed durig load chages Fig Therefore, this project has utilised the pole-zero cacellatio approach i the cotrol desig of dc-dc buck SMPC Loop Gais Buck Model PID Cotroller Frequecy Hz Fig. 2.4 Frequecy respose of the compesated ad ucompesated dc-dc buck SMPC

58 Chapter 2: DC-DC SMPCs Modellig ad Cotrol Times a Times b Times c Fig. 2.5 Trasiet respose of the pole-placemet PID cotroller, a: output voltage, b: iductor curret, c: load curret. Load curret chage betwee 0.66 A ad.32 A every 5 ms

59 Phase deg Magitude db Chapter 2: DC-DC SMPCs Modellig ad Cotrol Pole-Placemet 20 0 Pole-Zero Frequecy Hz Fig. 2.6 Loop-gai compariso betwee pole-placemet ad pole-zero PID cotrollers Pole-Placemet Pole-Zero Times Fig. 2.7 Compariso of trasiet respose results betwee pole-placemet ad polezero PID cotrollers. Repetitive load curret chage betwee 0.66 A ad.32 A every 5 ms

60 Chapter 2: DC-DC SMPCs Modellig ad Cotrol Chapter Summary Details ad aalysis of the modellig ad cotrol of the dc-dc power coverters were itroduced i this chapter. Commo circuit topologies of dc-dc coverters with focus o the buck dc-dc coverter cofiguratio ad circuit operatio were demostrated. The mathematical modellig i cotiuous ad discrete time domai of the buck SMPC was explaied. I additio, chapter 2 provided iformatio o the actual liear state space ad liear average model of buck dc-dc coverters, with most of the emphasis o the modellig of the cotrol-to-output voltage trasfer fuctio of dc-dc buck coverter. Therefore, the digital voltage mode cotrol architecture of the buck dc-dc SMPC was demostrated ad a overview of each block i this structure was highlighted. For the digital cotrol of the buck SMPC, two techiques of cotrol loop desig were explaied: the pole-zero cacellatio method ad the poleplacemet approach. Fially, the proof of cocepts for the most importat aspects were aalysed ad simulated.

61 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 38 Chapter 3 SYSTEM IDENTIFICATION, ADAPTIVE CONTROL AND ADAPTIVE FILTER PRINCIPLES -A LITERATURE REVIEW 3. Itroductio This chapter presets a overview of recet research i the area of SMPC cotrol. Three topics i this field are specifically cosidered: system idetificatio, adaptive cotrol ad adaptive filterig. The first part of this chapter describes the differet methods used i system idetificatio. It explais the differece betwee parametric ad o-parametric estimatio techiques ad clearly explais the ratioale for choosig a parametric approach i this work. The secod part of the chapter presets a geeral itroductio to adaptive cotrol ad adaptive filterig. The chapter cocludes by cosiderig the use of these digital techiques i state of the art solutios for system idetificatio ad adaptive cotrol of dc-dc SMPC applicatios. 3.2 Itroductio to System Idetificatio System idetificatio has bee widely used i a plethora of scietific fields ad has become essetial i the area of sigal processig ad adaptive/self-tuig cotrol systems automatic cotrollers. The objective of system idetificatio is to capture the dyamic behaviour of the system based o measured data [62]. I a rigorous mathematical sese, system idetificatio etails the costructio of the mathematical model that most closely resembles the dyamic characteristic of the system based o observed data [63]. A sigal with eriched frequecy cotet is ijected ito the system, which, alog with the measuremet of the resultat output, is processed to produce the system model.

62 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 39 This costitutes the uderlyig priciple of a system idetificatio process. Typically, the plat is treated as a black-box model ad whe the error betwee the real system ad correspodig model output is miimised, a accurate model of the system ca be derived Fig. 3. [64]. May cotrol approaches rely o a accurate model of the system, ofte represeted as a trasfer fuctio, to desig a robust cotroller. For example, the pole placemet techique is immesely iadequate without the trasfer fuctio of the process to successfully modify the locatio of poles ad zeros i order to meet the desig requiremets [28]. Ukow System y u + ε = e p Structure Model Estimated parameters w, w 2,..., w N ŷ Adaptatio Algorithm Fig. 3. Geeral block diagram of parametric idetificatio Two broad categories of system idetificatio exist, amely o-lie ad off-lie estimatio techiques [64]. a I the o-lie paradigm, the obtaied data i real-time is used to estimate the parameters of the model. RLS is the most recogisable method of o-lie system idetificatio [64]. The automatic cotrol scheme icorporates this approach to adapt the cotroller gais at each sample period. This is accomplished i two phases. I the iitial step, the system performace will be moitored ad the dyamic characteristics of the closed loop system will actively be idetified, providig a real-time estimatio of the model parameters. I the secod step, the cotrol parameters are fie-tued accordig to the ucertaities of the system ad this results i a profoud improvemet of the dyamic performace of the system [54].

63 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 40 b I the off-lie estimatio, the measured data is stored i the memory; a typical approach is to use a block array of memory. The the batch of observed sigals is processed to costruct the system model ad this process is called batch estimatio [64]. Geerally, this scheme is preferred whe the requiremet is to model a highly complicated system. The estimated model is the used to desig the desired cotroller. This ca be achieved by firstly costructig the model of the system, relyig oly o experimetal data, ad the by determiig the cotroller parameters based o the estimated model. Nomathematical assumptio is required i this approach; therefore, optimal cotrol parameters ca be calculated usig the off-lie estimatio method. It is worth otig that both schemes ca be applied to estimate specific parameters i the system; for istace, corer frequecy w ad dampig factor ζ/quality factor Q are the valuable parameters to idetify i SMPC applicatio. 3.3 Parametric ad No-Parametric Idetificatio The liear model of a system ca be determied usig two differet techiques: No-parametric estimatio techiques, 2 Parametric estimatio techiques [28]. No-parametric methods ofte use trasiet respose aalysis or correlatio aalysis to estimate the impulse respose of the system, or use frequecy aalysis ad spectral aalysis to estimate the frequecy respose of the system, without usig model parameters. Algorithms such as the Fourier Trasform FFT ca be used to costruct the o-parametric model of the system. The mai advatage of oparametric estimatio techiques is that o prior kowledge of the model is required to estimate the system dyamics. I additio, the level of complexity of oparametric methods is comparatively maageable for effective implemetatio [63, 65]. No-parametric methods are more sesitive to oise ad a appropriate excitatio sigal is required to accomplish accurate estimatio. Therefore, log sequeces of captured data are essetial for oise immuity ad data accuracy [30]. Cosequetly, the idetificatio process ca take a sigificat amout of time to complete. This i tur, restricts a schemes ability to idetify rapid system chages, such as abrupt load

64 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 4 chages i SMPCs. Also, it hiders the cotiuous iterative estimatio of the system model, which is a imperative ecessity for adaptive cotrol desig. Sigificat hardware resources may also be required i terms of processig power ad memory [66]. Furthermore, iaccuracies i the estimated parameters potetially may be icreased i the discrete time domai. This is attributable to approximatios occurrig o trasformatios from the s-to-z domai, ad effects of quatisatio error [30]. I additio, it ca be difficult to apply trasiet respose aalysis or correlatio based techiques for closed loop o-parametric estimatio. This is because i closed loop systems, the output has a impact o the iput sigal to the system due to the feedback loop. Therefore, ay assumptio of o-correlatio betwee the iput/output sigals is ot valid [28]. This is clearly described i 3.2 ad 3.3; here the sampled iput sigal u ad the disturbace sigal v, such as measuremet oise should be o-correlated to satisfy coditio a below for accurate impulse respose estimatio [65]. As show i Fig. 3.2, the liear time ivariat discrete system ca be expressed as [67]: y g k u k v k 3. e Hz u Gz v + y Fig. 3.2 Geeral liear model trasfer fuctio Here, u is the sampled iput sigal, y is the discrete output sigal, g is the discrete impulse respose of the system, ad h is the discrete impulse respose of the oise, e, ad v is the disturbace sigal. Startig from 3., the crosscorrelatio betwee iput u ad output y ca be described as:

65 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 42 Ruy m u y m g Ruu m Ruv m 3.2 where, R uu m is the auto-correlatio of u ad R uv m is the cross-correlatio betwee the iput ad the disturbace. Two coditios should be cosidered for valid o-parametric estimatio of the impulse respose [68]: a The iput u ad disturbace v are ucorrelated, therefore R uv m = 0. b R uu is the auto-correlatio of a white oise iput sigal, thus R uu m = δ. Cosequetly, equatio 3.2 ca be writte as: R m g m 3.3 uy I the parametric techique, a model structure is assumed ad the parameters of the model are idetified usig iformatio extracted from the system [65, 68]. Therefore, the parametric idetificatio of the system is required to defie the order of system umber of poles, zeros, i advace [69] ad the cadidate model is applicatio depedet. For example, a dc-dc buck coverter may be represeted as a secod order IIR filter. Differet approaches ca be icorporated to estimate the system parameters whe usig parametric techiques. LMS, RLS, ad subspace based methods are some of the domiat approaches [63, 65]. Fudametally, the mai target i parametric idetificatio is to determie the optimal parameters that best describe the ukow model i the system. I accordace with this, the defiitio of a cost fuctio is also required. Parameterised predictio error methods such as RLS are seekig to miimise the error betwee the real system y ad the estimated model ŷ for optimal system idetificatio as show i Fig. 3., ad give i 3.4. This error is kow as the predictio error ε [63]. y yˆ 3.4 The mai advatage of parametric estimatio is that advaced cotrol techiques ca easily be itegrated with the estimatio method. Pole placemet ad model referece cotrol costitute some of the aforemetioed paradigms [28]. Furthermore, a direct cotrol desig implemetable i a discrete time domai ca be applied. This

66 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 43 will substatially reduce errors attributable to trasformatio approximatios from the s-domai to z-domai. I additio, the model ca be estimated o-lie ad i closed loop form, immue to cocers associated with weakesses iheret to oparametric idetificatio. Aother positive attribute of parametric estimatio is its isesitivity to oise. A disadvatage of parametric idetificatio methods is the sigificat depedece o sigal processig, which ultimately iflicts a cost pealty for the target applicatio. The case becomes more complicated if the model cotais too may coefficiets to estimate, where the solutio requires sigificatly large multiplicatio matrices. 3.4 Model Structures for Parametric Idetificatio As metioed i the previous sectio, the iitial step i parametric system idetificatio methods is to select the appropriate model structure that optimally resembles the dyamic behaviour of the system. As depicted i Fig. 3.2, a liear system model ca mathematically be represeted by equatio 3.5 [70]: y G z u H z e 3.5 It is perfectly appropriate to assume that: B z G z A z F Z C z H z A z D z 3.6 The by substitutig 3.6 ito 3.5, the liear model ca be described as: B z C z y u e A z F z A z D z 3.7 where, the models polyomials Az, Bz, Cz, Dz, ad Fz are as [70]:

67 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 44 2 A A z az a2z aaz 2 B B z b z a2z bbz 2 C C z cz c2z cc z 2 D D z dz d2z ddz 2 F F z fz f2z af z 3.8 e e Az Cz Az u Bz Az + y u Bz Az + y a ARX b ARMAX e e Cz Dz u Bz Fz + y u Bz Fz + y c OE d BJ Fig. 3.3 Parametric idetificatio model structures Depedig o the choice of polyomial, there is adequate flexibility to use oe of the four popular model structures that are depicted i Fig. 3.3 [63, 70]. The dyamic characteristics of the system ad the exteral disturbace are the most decisive factors i selectig the appropriate model structure. Auto-Regressio with Extra iput ARX is the most popular model, which is ofte kow as the equatio error model. The oise term, e, is etered directly to the iput/output differece equatio [63]. Therefore, with miimal effort the miimisatio problem ca be solved aalytically, where the model parameters are estimated directly from the kow iput ad output data vectors. For these reasos, ARX is the preferred choice i may applicatios

68 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 45 [63]. It is imperative to emphasise that the equatio error IIR adaptive filter is icorporated i this research exhibitig similar characteristics with the ARX model. The models of ARX ad Auto-Regressio Movig Average with Extra iput ARMAX that iclude a disturbace term all have a set of commo coefficiets with the system model, that is Az parameters [65]. Thus, the estimatio of ukow system parameters usig these structures may be biased if the system does ot have these commo parameters with the oise model. The estimatio of the parameters of the oise model usig the ARMAX structure provides ehaced flexibility compared with ARX. This is due to the fact that the omiator of the oise model cotais the Cz polyomial. This polyomial ca cacel the effects of the deomiator polyomial, Az [63, 65]. Therefore, to obtai a accurate depictio of the dyamics of the system model idepedetly from the disturbace model, the Output Error OE ad Box-Jekies BJ structures are immesely more popular. As show i Fig. 3.3c, d the dyamics of the disturbace i BJ ad OE models are separated from the system model, rederig a flexibility to hadle the disturbace model separately [63, 65]. However, i the OE structure, oly the model of the system is described ad the oise sigal is directly added to the fial output, where there is o model that describes the disturbace i this structure [65, 70]. The model structures are further classified ito two types: The black box model ad the grey box model [63]. I the black box model, there is o prior iformatio about the iteral costituets of the system or the physical modellig of the system. Here, the choice of the model structure ad the estimatio of the parameters of the system are accomplished based o observed data from the system [65, 7]. I the grey box model, the system dyamics ad the model structure are partially kow i advace. The remaiig ukow coefficiets are estimated from the measured data. This prior iformatio ca be used as a bechmark to aalyse the estimatio of the model. I additio, this prior iformatio improves the covergece of the applied algorithm. As a illustrative example, some of the power coverter parameters i SPMCs such as the capacitace, iductace, or ay other measurable physical parameter ca be used as kow coefficiets ad ca be iitially utilised to calibrate the grey box model [3].

69 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review Parametric Idetificatio Process This sectio summarise the process of parametric idetificatio of the ukow system. As depicted i Fig. 3.4, the procedure of parametric idetificatio is performed by four mai steps [63, 72]. It starts with measurig the experimetal iput ad output data of the ukow system. It is worth otig that a appropriate excitatio sigal should be ijected ito the system before collectig the iput ad output data. This excitatio is essetial for accurate parameter estimatio ad to improve the covergece rate of the adaptive algorithm. Iput ad output data collectio Data Pre-processig Model structure selectio Processed Data Apply the Adaptive Algorithm Model validatio No Best fit Model Yes Fig. 3.4 Parametric idetificatio flowchart More detail o the excitatio sigal will be preseted i the ext chapter

70 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 47 Next, the measured data passes to the pre-processig stage. Some examples refer to the pre-processig step, icludig data filterig to remove the uwated oise ad to determie the mea value from the iput ad output data for proper estimatio. Now, the model structure should be selected ad the order of the model is defied. This ca be accomplished from the prior kowledge of the system to be estimated. I this case, the selected model cosidered is a grey box model. The optimisatio algorithm is the applied i order to estimate the parameters of the model. The estimated model should provide a best fit with the pre-processed data. This ca be achieved by comparig the estimated output data with the measured data. The differece is kow as a model error. Whe the model is acceptable the the estimated parameters are foud. Otherwise, the process is repeated by selectig a ew model or by pre-processig the iput ad output data [63, 73]. 3.6 Adaptive Cotrol ad Adaptive Filter Applicatios Accordig to Astrom ad Wittemark, to adapt meas to adjust a behaviour to coform to ew eviromet [74]. Adaptive sigal processig ad adaptive/selftuig cotrollers have a somethig i commo; both scietific disciplies rely o similar mathematical tools ad strategies. The desig of the adaptive ad self-tuig cotrollers ecessitates system idetificatio techiques as a first step, which ca be realised by usig adaptive sigals processig algorithms. Widrow ad Plett [75, 76] successfully tued the parameters of the cotroller icorporatig a adaptive iverse filter scheme. The LMS algorithm has bee used to adjust the iverse filter coefficiets that pertai to the ukow system. Subsequetly, Shafiq i [77, 78] preseted a similar paradigm usig a iverse adaptive filter. Here, the parameters of the adaptive filter are estimated usig the RLS method [78]. Oe commo example of sigle processig applicatios is the adaptive filter. Adaptive filters, as well as adaptive cotrollers, are time varyig systems. Their parameters are updated frequetly i order to meet the performace requiremet. Adaptive cotrollers offer a robust cotrol solutio ad ca improve the closed loop dyamic respose. They are ofte used i low rate applicatios, such as process cotrol due to the complexity of the adaptive cotrollers. This may require a highspecificatio microprocessor for successful implemetatio. Advaces i

71 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 48 microprocessor efficiecy have sigificatly mitigated the particular drawbacks, makig it more feasible to implemet adaptive cotrollers i the applicatios that operate with a higher samplig rate. Therefore, there is a requiremet for further research ad developmet of cost-effective computatioally light automatic methods, which cotiue to offer robust cotrol performace. 3.7 Adaptive Cotrol Structures There is a plethora of adaptive cotroller structures that are classified ito differet categories. The most commoly used cotrollers are the model-referece adaptive system MRAS ad the self-tuig cotroller STC. I the MRAS paradigm Fig. 3.5, the cotrol parameters are adjusted based o the error sigal betwee the referece model ad the plat. I this way, the parameters coverge to their true values. This forces the plat to follow the desired specificatio as dictated by the model referece. This i tur leads to miimise the error sigal to a small value. Here, the error sigal is the differece betwee the referece model ad the process model output. To miimise the error sigal ad esure system stability, a appropriate adjustmet mechaism is required. This is the biggest issue i MRAS [60, 74]. Referece Model Cotroller Parameters Adjustmet Mechaism Set Sigal Cotroller Actio Sigal Plat Output Fig. 3.5 Adaptive model referece structure I the STC desig paradigm, the tuig of the cotrol parameters is accomplished with o-lie system idetificatio techiques ad the adjustmet is performed o-thefly via the appropriate cotrol desig block Fig Normally the ukow

72 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 49 parameters are estimated based o RLS algorithms. A ijectio of a perturbatio sigal i the feedback loop may be essetial to improve the covergece of the estimated parameters [74]. The mai issue i a STC scheme is the reliability ad complexity that characterises the idetificatio part of the process. The auto-tuig cotroller ca also be cosidered as a special case of STC. I such a system, the adaptatio process is oly eabled to satisfy tuig demad. Some examples refer to adaptatio performed upo the start-up phase, adaptatio accomplished by moitorig chages i the system, such as load chages i SMPCs, or adaptatio iferred by the user. Clearly, this architecture imposes a reductio to the computatioal complexity of the adaptatio process. Icreasigly ehaced artificial itelligece techiques are also used i the desig of adaptive cotrollers. Some of the cadidates are fuzzy-logic ad eural-etworks [60, 79]. Cotrol Desig Idetificatio Cotroller Parameters Set Sigal Cotroller Actio Sigal Plat Output Fig. 3.6 Self-tuig cotroller block-diagram 3.8 Adaptive Filter Techiques A adaptive filter may be defied as a self-desigig filter [80], where the filter coefficiets are varyig cotiuously util the desired sigal is achieved. Ofte, the desired sigal is chose to be the filter iput or the desired estimated output. As show i Fig. 3.7, the adaptive filter cosists of two key compoets: a digital filter ad a adaptatio algorithm which is used to vary the tap weight coefficiets i realtime. Least square algorithms LS, such as RLS ad LMS, are the most commo

73 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 50 adaptive algorithms. The essece of these algorithms is to miimise the estimatio error. They accomplish the task by iteratively updatig the filter parameters. d r u Digital Filter ŷ + - e s w, w 2,..., w N Adaptatio Algorithm Fig. 3.7 A adaptive filter structure The digital filter ca be realised as either: FIR filter all zeros filter, or IIR filter poles/zeros filter. The selectio of the filter structure depeds o the applicatio ad the characteristics of the iput sigal [80, 8]. The FIR filter is simpler to desig ad robust, as the feedback path does ot impose o the geeral structure of this filter. I cotrast, the IIR filter structure, which cotais both poles ad zeros, etertais a higher level of complexity i the desig process. However, the modellig of the ukow system usig the IIR filter is computatioally more efficiet tha a FIR filter, sice it requires fewer tap-weights i the system model [8]. It is importat to emphasise that miimisig the estimatio error sigal e s is the mai objective i adaptive filter structure desig. The updated values of the filter coefficiets are accomplished by performig error miimisatio at each time istace. This miimisatio serves two purposes: the fidig of optimal filter coefficiets, ad esurig the output sigal of the adaptive digital filter ŷ estimated sigal is approximately equal to the desired sigal d r. A adaptive filter ca have differet structures depedig upo its iteded applicatio. Cadidates for this may be system idetificatio, sigal predictio, oise cacellatio, or iverse modellig. The theoretical developmet for these applicatios is usually based o a geeral block diagram of a adaptive filter as illustrated i Fig Four differet basic schemes of adaptive filter are depicted each tailored for optimality for idividual applicatios[80, 8]. I the system idetificatio scheme, Fig. 3.8a, the mai desig objective is to

74 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 5 implemet a filter that is ideally idetical to the ukow process. I this case, the estimatio error sigal is approximately equal to zero ad the adaptive filter algorithm o loger updates the filter coefficiets, as log as the system characteristics remai uchaged. I the case of the adaptive predictio error paradigm, Fig. 3.8b, the previous derived sigal is applied as iput to the filter ad the adaptive filter output is the preset estimated or predicted value of the desired sigal. The requiremet for the error sigal to be approximately equal to zero is essetial to best desig a predictio model. I the scheme depicted i Fig. 3.8c, the iverse model of the adaptive filter must be matched with the trasfer fuctio of the ukow plat. I this way, the error sigal betwee the previous desired sigal ad the output of the adaptive iverse filter is used i the idetificatio process. I a real time solutio, a delay fuctio for the iput sigal is required to esure that the system causality is preserved. Fially, a adaptive filter structure ca also be used to cacel the effects that the ukow iterferece i the iput sigal v may impart. Here, Fig. 3.8d, a auxiliary sigal v is supplied to the adaptive filter as a referece iput. Whe the filter coefficiets are coverget to their optimal values, the iformatio related to the desired sigal is extracted without ambiguity [8]. I this research, adaptive system idetificatio ad adaptive filter predictio schemes have bee employed to estimate the system parameters as well as to desig a real time adaptive cotroller for SMPC. More details will be preseted i Chapter 4 ad Chapter 5 relatig to these two schemes.

75 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 52 Process d r u + - e s Adaptive Filter ŷ a d r + e s - u Delay Adaptive Filter ŷ b Delay d r u + - e s Process Adaptive Filter ŷ c u+v d r v Adaptive Filter ŷ + e s - d Fig. 3.8 Adaptive Filter structures, a: system idetificatio, b: sigal predictio, c: iverse modellig, d: oise cacellatio

76 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review Literature Review o System Idetificatio ad Adaptive Cotrol for DC- DC Coverters Recetly a eormity of research effort was devoted to system idetificatio ad adaptive cotrol techiques for power electroic coverter applicatios. However, these solutios are ot always aimed towards low complexity systems. Ofte, the algorithms require advaced digital sigal processig resources which may itroduce cost pealties to the target applicatio. This sectio provides details o recet publicatios ad the motivatios i system idetificatio ad adaptive/self-tuig cotrollers for dc-dc power coverters No-Parametric System Idetificatio Techiques ad Adaptive Cotrol for SMPC A successful o-parametric method which cosiders perturbig the duty cycle with a frequecy rich iput sigal PRBS, is preseted i [68, 69, 82]. It starts with estimatig the impulse respose of the system by performig a cross-correlatio betwee the ijected PRBS ad output voltage of dc-dc coverters. Followig that, Fourier Trasform method FFT is applied to the resultig impulse respose data, i order to idetify the frequecy respose of the system. The proposed approach is simple ad ca hadle a wide rage of ucertaity i the power coverter. However, the idetificatio process may require sigificat amouts of time to complete ad may eed to process log data sequeces [8]. Accordig to Miao et al. [68], the capture of data usig 00 khz as a samplig frequecy takes approximately 23 ms to complete. I additio, durig the idetificatio process, the system operates i a ope loop paradigm without adequate regulatio. Furthermore, the ADC quatisatio has a sigificat impact o the idetificatio accuracy. Therefore, Shirazi et al. [69] proposed the itroductio of a pre-emphasis ad de-emphasis filterig techiques to improve the accuracy ad to smooth the estimated frequecy respose. Barkley ad Sati [67] developed a techique to improve the accuracy of cotrol-to-output idetificatio by widowig the measured cross-correlatio betwee the iput ad output of the dc-dc coverter. Roiila et al. [83, 84] proposed the ijectig of the other types of PRBS kow as iverse repeat biary sequece IRBS to improve the idetificatio sesitivity to disturbaces i the system.

77 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 54 Subsequet to [69], Ya Liu et al. [85] presets a similar techique to tue the cotroller coefficiets based o the idetified cotrol-to-output model of the dc-dc coverter usig a correlatio approach. A alterative system idetificatio methodology based o frequecy domai techiques is employed i [6]. The authors here proposed to iject a siusoidal sigal i order to directly estimate the frequecy respose of the cotrol-to-output trasfer fuctio usig FFT. Whilst these methods are straightforward to implemet, desigig a cotroller usig o-parametric system idetificatio methods is usually limited to frequecy respose methods oly. I additio, a complete real-time solutio of system idetificatio ad adaptive cotrol for SMPCs based o frequecy measuremet is rarely preseted i the literature. The authors i [67, 68, 82], used a FPGA board to implemet the cotrol loop, the PRBS geeratio ad to collect the experimetal data. This data is subsequetly post-processed i MATLAB for off-lie testig of the proposed algorithms. I [83, 84] a advaced, high cost, data acquisitio card NI PCI-65 is used. Agai, off-lie evaluatio based o the system idetificatio algorithm is carried out i MATALB/Simulik. Kog et al. [6] used a Texas Istrumet UCD9240 device based DSP for system verificatio. The literature cofirms that there is oly oe complete embedded auto-tuig cotroller that relies upo the o-lie frequecy respose idetificatio, preseted by the authors i [2, 86]. The implemetatio i this study was achieved through the Virtex-4 FPGA. Recetly, Costabeber et al. [87], icorporated the cross-correlatio approach preseted earlier with a model referece adaptive cotroller for a digitally cotrolled SMPC. The differece betwee the estimated impulse respose ad the model referece impulse respose has bee utilised to tue the gais of the PID cotroller. For simplicity the itegral gai was assumed to be fixed. As a result, the auto-tuig process is oly performed o the proportioal-derivative gais. A optimised search method is used to tue the PD coefficiets; this results i miimisig the estimated error. Accordig to [87] the cotrol parameters take a log time to coverge to the fial value. Cosequetly, a determiistic approach that does ot deped o the impulse respose estimatio is also ivestigated by the authors i [87]. Here, the

78 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 55 differece betwee the loop impulse respose ad the model referece impulse respose is cosidered i the tuig algorithm. The covergece rate usig this approach is superior to the cross-correlatio scheme. The proof of cocept was experimetally verified usig a low cost TMS320F2808-DSP. I summary, i may of the methods preseted, it was foud that these approaches restrict the ability of cotiuous parameters estimatio that is required i cotiuous parameters tuig [3] for adaptive cotroller applicatios. These self-tuig ad adaptive cotrol techiques are most effective durig the steady-state ad the parameters are tued usig pre-determied rules, such as phase margi ad gai margi requiremets. Therefore, these categories of cotroller are geerally usuitable for time varyig systems where o-lie compesatio is desirable. Oe solutio for o-lie parameter estimatio is itroduced by usig RLS algorithm. For this reaso, RLS is used i may system idetificatio ad adaptive cotrol strategies Parametric Estimatio Techiques ad Adaptive Cotrol for SMPC Straightforward relay-feedback based methods have bee successfully used i the parameter idetificatio ad auto-tuig of dc-dc coverters [7, 88, 89]. The idetificatio ad tuig processes are performed durig the period of system startup. The method starts to itroduce oscillatios at a specific frequecy ito the regulated output for a short period. The, the system parameters are estimated based o the measured frequecy of the oscillated sigal. Followig this, the parameters of the PID cotroller are auto-tued iteratively, util the predefied feedback-loop specificatios are met. However, this type of approach requires relatively complex algorithmic steps to tue the cotroller parameters. Typically, it requires three iterative tuig phases to adapt the PID parameters. I additio, a relatively large oscillated sigal at the output voltage of dc-dc coverter is itroduced durig the auto-tuig phases [52]. The auto-tuig process is completed after 27 ms at 200 khz samplig frequecy [86]. The algorithm is implemeted o a Virtex IV-FPGA usig the MATLAB System Geerator toolbox [86]. Similar techique i [54, 90] has bee proposed, such as isertig LCO ito the system durig steady-state period. Here, the LCO is geerated by reducig the

79 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 56 resolutio of DPWM istead of usig a relay i the feedback loop. Also, the feedback loop is temporarily compesated by itegral cotrol oly. I cosequece, the effect of LCO is amplified, thus it ca be easily observed. The amplitude ad frequecy iformatio are the extracted from the LCO sigal to fid the dc-dc coverter parameters corer frequecy ad quality factor [52]. I the secod phase, the PID compesator is re-tued usig the pole-zero cacellatio approach. Whilst hardware efficiet, this method results i a lower system idetificatio accuracy [48]. Aother egative aspect is that the idetifier ad the auto-tuer does ot cosider the ifluece of the R C resistace i the desig [54]. The authors here implemeted the DPWM by a Altera-FPGA ad the proposed algorithm has bee validated by Aalog Device ADMC-40-DSP. As previously idicated, for simplicity of the idetificatio ad adaptive cotrol desig, recursive techiques are also developed for dc-dc coverters. Recursive idetificatio methods are a very familiar approach i o-lie applicatios. However, these methods are ot fully exploited i low cost, low power SMPCs due to the computatioal complexity of the idetificatio algorithm, which may ecessitate a high specificatio microprocessor for effective implemetatio. Peretz ad Bi-Yaakov [, 30, 9] demostrated a ope loop system idetificatio approach, to determie the cotrol-to-output voltage model of a dc-dc coverters. The authors proposed to perturb the system by meas of a step chage i the duty cycle sigal. The same ijectio sequece has bee repeated for a umber of times, five sequeces i total. The DSP is the utilised to collect the averaged iput ad output sampled data. The recorded data is used for estimatio of the system parameters. It uses the iterative least square method icorporatig Steiglitz ad McBride IIR filter. Accordig to the authors [], a 5 % step chage i the duty cycle causes a chage of V at the output of the dc-dc coverter. The time elapsed for the idetificatio procedure to complete is about 20 ms. Therefore, the preseted approach is ot applicable for the desig of o-lie adaptive cotroller ad for trackig the variatio i parameters withi the system. The idetificatio scheme was implemeted o a TMS320F2808-DSP ivolvig MATLAB Real-Time Workshop toolbox. The resultat ope loop discrete dc-dc model was icorporated for the direct

80 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 57 digital cotrol desig method by Ragazzii s [27]. The proposed cotroller has bee implemeted experimetally by DSP platform. However, the desig steps ecessitated a off-lie optimisatio or curve fittig method, to covert the resultat high order Ragazzii cotroller to match the desired secod order digital PID cotroller. The authors here cocluded that the digital cotrol model relyig upo discrete estimatio provides better performace tha the mathematically calculated model. A black box No-liear modellig based o least square algorithm of dc-dc coverter is proposed by Aloge et al. [92, 93]. The techique preseted here is based o the Hammerstei model; this model cosists of a o-liear static model i cojuctio with a LTI ARX model. The ARX model captures the dyamic characteristics of the system. Two steps are required to defie the system model. I the first step, ad durig the steady-state period, the coverter is supplied by a costat iput voltage with a variable duty cycle sigal ad the correspodig output voltage is measured; the o-liear static model will the be idetified. I the secod phase, a PRBS is ijected to excite the system dyamics, ad the measured values of the cotrol-to-output voltage data are observed to estimate the secod order ARX model cadidate. This techique accurately describes the dc-dc coverter model; therefore, a robust cotroller is derived. However, the approach is quite complex ad time-cosumig for real-time operatio [92]. The experimetal data is captured usig a DSP platform dspace DS03. Aother approach of parametric black box modellig of the dc-dc coverter is preseted by Valdivia et al. [94]. Here, the dyamic respose of the dc-dc coverter is excited by a step load chage ad the output respose is captured. Whe the resultat dyamic is aalysed as a LTI resposes, the model ca be idetified usig the LTI idetificatio approach LS algorithm; otherwise the o-liear method should be used Hammerstei scheme. The OE model is employed i this techique to idetify the LTI parameters of the dc-dc coverter usig the MATLAB System Idetificatio toolbox [95]. The proposed method is suitable for a simulatio estimatio of the dc-dc coverter, where the estimatio procedure requires may steps ad advace aalysis prior to estimatio.

81 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 58 Kelly ad Rie [96, 97] proposed a adaptive, self-learig, digital regulator, based o a oe-tap LMS predictio error filter PEF for o-lie system idetificatio. The preseted solutio is simpler tha may other methods ad a prior kowledge of system parameters is ot required i the adaptatio process. However, there appears to be two limitatios to this system. Firstly, the scheme ivolves subjectig the system to a repetitive disturbace to excite the FIR filter ad improve the covergece of filter tap-weights [98], which after may iteratios the cotroller begis to lear. Furthermore, i this scheme oly a PD cotroller is cosidered ad this ca yield a o-zero steady-state error [54], thus a feed-forward loop should be itroduced to esure system stability ad achieve regulatio. Iitially, this adaptive cotroller was implemeted usig a DSP from Aalog device. This subsequetly lead to the desig of a microprocessor architecture adoptig dual multiply-accumulator MAC [99]. The feed-forward gai for the digitally cotrolled buck coverter as described i [57], has bee adaptively determied based upo the same cocept as usig a first order PEF. A real time parametric system idetificatio method usig a classical RLS techique is preseted by Pitel ad Krei [3]. It idetifies the parameters of a ope loop buck coverter durig abrupt load chages from the cotrol sigal to the iductor curret trasfer fuctio. This work accurately estimates the parameters durig the iitial start-up of the system, ad durig periods of relatively slow load chages. It cocludes that a major challege is to estimate the load value after abrupt chages. A effective implemetatio of the RLS algorithm based o fixed-poit DSP TMS320F282 usig the MATLAB Embedded Target Support Package toolbox has bee demostrated i this research. However, the estimatio process usig the RLS algorithm operates oly with a very low samplig rate of approximately 4 khz. B. Miao et al. [5] preseted a dual idetificatio scheme. I this approach both a parametric ad a o-parametric method are combied to estimate the parameters of a SMPC ad the to directly desig a digital cotroller. The idetificatio occurs i two phases. Iitially the ope-loop frequecy respose of the system is idetified based o FFT techiques, the the coverter parameters are estimated usig a

82 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 59 parametric recursive method, based o the obtaied frequecy respose data. Implemetig two differet methods is clearly more complex ad computatioally heavy for o-lie system idetificatio purposes. Therefore, it is more suitable to address off-lie scearios. A similar approach has bee proposed i [00, 0], for auto-tuig the cotroller of a SMPC. Durig the period that the system has reached the steady-state a perturbed sigal is ijected ito the cotrol loop ad the system frequecy respose is estimated. I this approach, it was proposed to icorporate a model fittig techique with a recursive parameterisatio algorithm. The objective is to determie the cadidate model which resembles the estimated frequecy respose data. Subsequetly, the cotroller parameters are re-tued based o the estimated model. This approach is ot immue to high computatios burdes which restrict its applicability for o-lie estimatio of SMPCs. Tae-Ji et al. [02] proposes a agig diagosis approach for the dc-dc coverter usig a least square idetificatio algorithm. A white oise sigal is ijected ito the feedback loop ad the iput ad output data cotrol/output sigals are stored ito the DSP memory. The parameters of the dc-dc coverter are the estimated usig MATLAB System Idetificatio toolbox based upo the output-error model OE structure [03]. The diagostic decisio relies upo estimatig the parasitic resistace R L /R C of the dc-dc coverter. These values are the compared by usig a maufactured of the dc-dc coverter sample ad cross-referecig the maufacture disclosed characteristics with those obtaied to cofirm validity. The proposed approach ca be used as a off-lie idicator of coverter agig. A applicatio of a adaptive cotroller for a dc-dc coverter based o the covetioal RLS scheme has bee proposed by Beid et al. [04]. A pole placemet approach is utilised i this scheme for the o-lie tuig of cotrol parameters. The performace of the proposed adaptive cotroller has bee verified by simulatio oly. Therefore, system complexity is ot ivestigated for this highly hardware demadig combiatio of RLS ad pole-placemet cotroller for the target applicatio.

83 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review Idepedet Adaptive Cotrol Techique for SMPC Several techiques that ivolve the desig of adaptive cotrollers immue to the eed for system idetificatio process are icorporated i the case of dc-dc coverters. The most popular paradigm i the literature is that of the o-liear cotrol. No-liear adaptive cotrollers are widely used i the cotrol desig of dc-dc SMPCs where their placemet i the cotrol loop results i improvemet of the trasiet respose of the dc-dc coverter. The o-liear compesators ca be employed as a stadaloe cotroller i the feedback loop or as a augmeted cotroller. It is worth metioig that the o-liear PID cotroller is the most frequetly structure that is applied to the SMPC. This is due to balace of the simplicity of desig ad effectiveess. The authors i [42, 5, 05] have developed this type of cotroller for the case dc-dc SMPCs. I these schemes, the gais of the PID cotroller are adaptively tued based o o-liear methodology. However, other o-liear structures have also bee proposed i the publicatios such as fuzzy logic FL cotrol. Fuzzy logic FL adaptive schemes are effectively implemeted for digitally cotrol of SMPCs. Farahai et al. [06] utilised a look-up table techique to implemet a fuzzy logic cotroller o a 8-bit microcotroller chip PIC8F452. The performace of the cotroller was compared with the covetioal PI cotroller, show that the FL cotroller provides better dyamic performace over the PI cotrol. However, the author has validated the system performace durig iitial start-up oly, where o abrupt parameter chages are applied to the SMPC to verify the robustess of the proposed cotroller subjected to fast chages. A real time adaptive cotroller based o a FL system has also bee preseted by Ofoli ad Rubaai i [07]. Here, the FL system is implemeted usig a PC ad the iputs sigals are sampled via a data acquisitio card DAP 840 usig a 4-bits ADCs. MATLAB ad LABVIEW are icorporated to acquire the sampled data ad the to implemet the FL o usig the PC. The output from the fuzzy cotroller is the exported to the microcotroller for PWM geeratio. The results from the fuzzy cotrol are preferable i compariso to the covetioal digital PID compesator. However, the experimetal setup requires the availability of sigificat hardware resources, i

84 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review 6 excess of what would be aticipated i a typical dc-dc coverter applicatio. It is worth metioig that L. Guo et al. [24] preseted a thorough compariso betwee fuzzy cotroller ad classical digital PID cotrollers i terms of demads o experimetal implemetatio for the two schemes. The evaluatio was applied to both buck ad boost dc-dc coverters usig a TMS320F28-DSP. Agai, it was demostrated that FL cotrol was more robust ad provided faster trasiet respose compare to covetioal PID cotroller. Alterative adaptive schemes that do ot rely upo a system idetificatio approach have bee preseted i the literature. Oe such paradigm is kow as the dual mode adaptive approach. I this approach a liear cotroller such as the PID cotroller operates at the steady-state mode ad a advaced cotrol algorithms, is used i trasiet mode; for example, o-liear cotrollers. This scheme was employed i [47, 08, 09]. Two loops, liear ad o-liear with a trasiet moitorig circuit, are utilised to obtai a efficiet trasiet respose of the SMPC. Aother techiques, usig a charge balace cotroller, is preseted by [0, ]. This methodology requires moitorig the peak ad the valley poits of the output voltage ad iductor curret to achieve optimal dyamic respose durig load chages. The mai challege i these schemes is formulatig the trasiet curve ad the method of detectig/measurig the required poits o this curve. This process ivolves complex mathematical aalysis ad precise kowledge of the power coverter parameters [52]. Fially, a model referece auto-tuig scheme was also proposed for digital cotrol of dc-dc coverters [48, 98]. The authors cosider ijectig the cotrol loop with a perturbatio sigal at a desired cross-over frequecy ad the tue the model referece cotroller util the pre-defied targets loop badwidth ad phase margi are achieved. Here, oly the PD parameters are tued ad a fixed itegral gai is placed i parallel with the adaptive PD cotroller ito the feedback loop. The proposed solutio has bee experimetally tested usig the TMS320F2808-DSP platform.

85 Chapter 3: SI, Adaptive Cotrol ad Adaptive Filter Priciples-A literature Review Chapter Summary This chapter has preseted a overview of the priciples ad techiques used i system idetificatio. It has provided details of the methods that are used i system idetificatio, with the focusig more o parametric estimatio techiques. Model structures used i parametric estimatio techiques have bee demostrated. I the chapter adequate iformatio o adaptive cotrollers ad adaptive filter was provided. Adaptive cotrol structures were outlied, with emphasis o model referece ad self-tuig adaptive schemes. Adaptive filter applicatios were also demostrated. Recet research o system idetificatio ad adaptive cotrol techiques for dc-dc SMPCs were reviewed. The mai focal poit is o adaptive cotrollers based upo parametric/o-parametric system idetificatio processes. Adaptive cotrol strategies that do ot ecessitate the icorporatio of system idetificatio for the case of dc-dc coverters were appropriately examied.

86 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 63 Chapter 4 SYSTEM IDENTIFICATION OF DC-DC CONVERTER USING A RECURSIVE DCD-IIR ADAPTIVE FILTER 4. Itroductio For a high performace cotroller with high dyamic performace, accurate estimatio of the system parameters is essetial [5]. Normally, i digitally cotrolled systems, a discrete time trasfer fuctio model of the plat is used for the cotrol desig [5, 6]. The actual form of the trasfer fuctio, ad the umerical values of its coefficiets, are depedet upo the idividual parameters of the plat to be cotrolled [54]. It is the fudametal role of the system idetificatio process to evaluate each coefficiet of the trasfer fuctio. I may applicatios, it is very importat that the coefficiets are calculated as accurately as possible, sice this will ultimately determie the closed loop cotroller respose. However, i SMPC applicatios, it is also ecessary to acquire the system parameters rapidly. The time costats i PWM switched power coverters are ofte very short, ad it is ot ucommo for abrupt load chages to be observed. Ay system idetificatio scheme must be able to respod appropriately to these characteristics. However, to achieve improved accuracy ad/or speed also implies the eed for a faster, more powerful microprocessor platform. This is ot always viable i SMPC applicatios, where it is essetial to keep system costs low ad competitive. Therefore, there is a eed for computatioally light system idetificatio schemes which eable these advaced techiques to be performed o lower cost hardware. Ufortuately, i may of the methods discussed i the literature review, sigificat sigal processig is required to implemet these schemes ad this

87 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 64 evetually has a cost pealty for the target applicatio. Furthermore, the computatioal complexity impacts upo time of executio i the microprocessor, ad this i tur makes it difficult to adopt i cotiuous parameter estimatio for adaptive cotrol applicatios [4]. I additio, idetificatio/adaptatio process required may steps to achieve. For this reaso, this chapter itroduces a ovel techique for o-lie system idetificatio. Specific attetio is give to the parameter estimatio of dc-dc SMPC. However, the proposed method ca be implemeted for may alterative applicatios where efficiet ad accurate parameter estimatio is required. The proposed techique is computatioally efficiet, based aroud a DCD algorithm, ad uses a IIR adaptive filter as the plat model. The system idetificatio techique reduces the computatioal complexity of classical RLS algorithms. Importatly, the proposed method is also able to idetify the parameters quickly ad accurately; thus offerig a efficiet hardware solutio which is well suited to real time applicatios. This algorithm has previously bee developed for use i the field of telecommuicatios [2, 3]. Here, we adapt the algorithm ad apply it for the first time i the system idetificatio of power electroic circuits. Results clearly demostrate that the proposed scheme estimates the dc-dc coverter parameters quickly ad accurately. Importatly, the approach ca be directly embedded ito adaptive ad self-tuig digital cotrollers to improve the cotrol performace of a wide rage of idustrial ad commercial applicatios.

88 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter System Idetificatio of DC-DC Coverter Usig Adaptive IIR DCD-RLS Algorithm v i t Q Q 2 R L L R C C DC-DC Buck Coverter v o t R o H s ct Driver DPWM d` + + d comp z q 0 q e z - A/D - v o + V ref Digital PID Compesator q 2 z - PRBS PRBS Geerator Adaptive IIR Filter ID DCD-RLS ID Eable IIR Filter System ID Block G dv Tuig the PID Cotrol Gais Fig. 4. The proposed closed loop adaptive IIR idetificatio method usig DCD- RLS algorithm Fig. 4. illustrates a block diagram of the proposed idetificatio scheme. Here, a closed loop sychroous dc-dc buck coverter is cotrolled via a digital PID compesator. I additio, a real-time system idetificatio algorithm is iserted alogside the cotroller, cotiually updatig the parameters of a discrete model of the buck coverter system o a sample by sample basis. The idetificatio system ca be eabled ad disabled o demad durig operatio. For example, it may be applied at start-up, at regular set itervals, or eabled o detectio of a system chage such as

89 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 66 a variatio i the system load. Moitorig the voltage loop error is oe simple way to detect a system chage ad eable the system idetificatio process. Whe eabled, a small excitatio sigal is ijected ito the cotrol loop. This is required to improve the covergece time of the adaptive filter; this is the time to obtai optimal filter tap weights for accurate parameter estimatio. For all o-lie idetificatio methods, some form of system perturbatio is essetial for the estimatio process. I this scheme, the Pseudo-Radom-Biary-Sequece PRBS is selected. As show i Fig. 4., the PRBS sigal is added to the PID cotroller output sigal, d comp. This creates a cotrol sigal, d`, with a superimposed persistet excitatio compoet. Oce applied to the DPWM, a small disturbace i the output duty cycle, ct is geerated. I this way, the duty cycle commad sigal at steady-state will vary betwee d comp ± PRBS. Here, the average steady-state duty cycle is 0.33 ad the magitude of PRBS sigal, PRBS = ± 0.025, therefore a chage of approximately equal to 33 % ± 2.5 % i duty cycle sigal will be observed. This will the cause a excitatio sigal i the buck coverter output voltage, v o t. Durig this process, the excited output cotrol sigal ad the sampled output voltage are d` ad v o i Fig. 4.. Oce the samples have bee pre-processed to elimiate ay uwated high frequecy oise, they are passed to the idetificatio algorithm DCD-RLS block i Fig. 4. to estimate the system parameters ad update the discrete IIR filter model of the SMPC. The followig sectios describe each block i Fig. 4. more details, icludig a complete descriptio of the algorithms proposed to implemet the system idetificatio.

90 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter Adaptive System Idetificatio u = d` DPWM ct DC-DC SMPC v o t Digital Filter A/D d r = v o + ε=e p ŷ w, w 2,..., w N Adaptatio Algorithm Fig. 4.2 Adaptive system idetificatio block diagram As iitially preseted i Chapter 3, a adaptive filter ca have differet structures depedig upo its applicatio. I Fig. 4., a adaptive IIR filter is employed for system idetificatio. The major cocer is miimisig the predictio error sigal, e p. Ideally, we wat this sigal to equal zero, idicatig excellet parameter estimatio. However, practical issues such as measuremet errors, uwated oise, quatisatio, ad delay time make this difficult to achieve. By miimisig the predictio error sigal, the optimal parameters estimatio is foud. As show i Fig. 4.2, the desired sigal is the sampled output voltage of the dc-dc coverter. Based o this, we ca write [80]: N yˆ wku k w T u k 0 u w w0 w u w N u T u N T where, the pre-filtered iput sigal u, is cotiuously adapted i respose to the filter weight update. The model of the ukow plat system i this case, the dc-dc coverter system is defied by the trasfer fuctio of the adaptive filter. Therefore,

91 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 68 as log as the parameters of the plat do ot chage, the digital filter coefficiets, w, will remai the same [80]. However, defiig the digital filter coefficiets requires aalytical calculatio of the liear system equatios. This ca be achieved usig Wieer equatios, but requires cosiderable computatioal effort [96]. Alterative methods, such as adaptive approaches ca also be used to optimally calculate the tap weights ad ca help to reduce the mathematical burde ad trim the computatioal load [80, 96]. Here, we employ a adaptive DCD-RLS algorithm to cotiuously adjust the filter coefficiets ad miimise e P. The error predictio is defied as [80]: N T ep dr yˆ dr wku k dr w u k Accordig to 4.3, the error predictio sigal is determied by applyig the iput sigal to the digital filter to produce a estimatio output sigal, ŷ. The predictio error is the the differece betwee the desired sigal, d r, ad this geerated estimatio output sigal. Whe the predictio error is miimised, the adaptive filter tap-weights reach steady-state ad o loger require updatig. However, if ay parameters of the plat chage, the predictio error will deviate from the miimum poit ad the adaptive algorithm will start to determie the ew filter tap-weights i respose to this chage. To miimise the error sigal, the adaptive algorithm must solve a series of liear equatios to estimate the vector coefficiets, w. Geerally, this is ca be accomplished usig the well kow least square LS algorithms [80]. 4.4 Least Square Parameters Estimatio LS estimatio techiques are fudametal i adaptive sigal processig applicatios. I real-time applicatios, the solutio is typically based o matrix iversio which, due to the computatioal complexity, is particularly difficult to implemet [4]. The LS algorithm evaluates ad calculates the fiite vector of estimated parameters, to obtai a small estimatio error. This is achieved by miimisig the predictio error sigal based o the criterio of the sum of the predictio error squares [80]:

92 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 69 k k T r p k k d k e J 2 2 u w 4.4 By differetiatig equatio 4.4 with respect to w ad settig this equal to zero; the estimated parameters that obtaied the miimisatio criterio of sum squares of predictio error ca be foud [28, 72]: 0 2 w u u w w J k k k d J k T r 4.5 If we assume that w = ŵ LS, ad by solvig equatio 4.5 for ŵ LS ; the estimated parameters values are calculated [63]: k r k T k k d k k LS ˆ u u u w 4.6 From 4.6, the estimated least square parameters vectors ca be writte as: ˆ LS β R w 4.7 where: k r k T k k d k k u β u u R 4.8 R is a auto-correlatio matrix of size N N, ad β is the cross-correlatio vector of legth N. These series of equatios ca be used to fid the estimated parameters values of ŵ LS. They are called ormal equatios [28, 63].

93 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter Covetioal RLS Estimatio May adaptive cotrol systems are based upo real time parameter estimatio [60, 74]. Amog them, RLS based algorithms provide a simple adaptive scheme which is capable of a fast covergece rate, good estimatio accuracy, ad fast trackig ability to system parameter chages. However, oly limited literature describes the applicatio of these methods i low complexity systems, such as dc-dc coverters. This is because the solutio is ormally based o matrix iversio operatio, which is computatioally heavy ad presets implemetatio difficulties. The best way to reduce computatioal complexity is to avoid or fid a approximatio method to the matrix iversio operatio [3]. Typically, a matrix iversio lemma algorithm is required to elimiate such operatio [80]. The RLS process ca be performed by arragig the computatios i such way that the results obtaied at time istace ca be used i order to fid the estimates at time istace [74]. Therefore, the auto-correlatio matrix ad crosscorrelatio vector are sequetially computig as give i equatio 4.9. The filter coefficiets are updated recursively with complexity of for matrix vector multiplicatio ad aroud for auto-correlatio matrix iversio 4.0 [2, 3]. As a result, the fial solutio of ormal equatios i 4.0 is directly proportioal to [ + ]. T R R u u 4.9 β β dr u w R β 4.0 May adaptive filter methodologies are based o matrix iversio operatio which results i umerical iaccuracies due to fiite precisio implemetatio. Aother techique ca be used to solve the iverse operatio i 4.0, ofte results i more accurate adaptive algorithm [2]. However, the covetioal RLS algorithm based matrix iversio lemma is summarised i Table 4. Appedix A shows the derivatio details of the RLS algorithm usig matrix iversio lemma ad the closed loop sigal operatio is depicted i Fig. 4.3 [80]. I Table 4., u is the data vector,

94 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 7 ŵ is the estimated tap-weights, e priori estimatio error, P is a N N iverse correlatio matrix, k is a N adaptatio gai vector, ad for ordiary RLS the forgettig factor λ =. Table 4.Covetioal RLS algorithm based matrix iversio lemma Step Equatio Iitializatio: ŵ = 0, for =, 2, P 0 I N S P u S 2 k T u S 3 ˆ T e dr w u 4 wˆ wˆ k e T 5 P P k u P d r e + u T k ŵ X z - ŵ Fig. 4.3 Closed loop operatio of covetioal RLS algorithm based matrix iversio lemma

95 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter Normal Equatios Solutio Based O Iterative RLS Approach As described i Table 4., the solutio of ormal equatios at every time istace is computatioally heavy ad presets implemetatio difficulties. However, there are alterative algorithms for solvig the liear equatios expressed i 4.0. Amogst them, the DCD algorithm appears to be a particularly effective method [2, 3, 5]. Attractively, the computatio is based o a efficiet, iterative approach with o explicit divisio operatios. This makes it very appropriate for real time hardware implemetatio. As metioed earlier, direct methods require a complex matrix iversio operatio to solve the liear equatios i 4.0. However, i this method first proposed by Zakharov et al. [2], i the field of commuicatios a alterative solutio is preseted by covertig 4.0 ito a sequece of auxiliary ormal equatios that ca be solved usig iterative techiques. Firstly, at time istace, the solutio to the system equatio ca be approximated; the approximate solutio is ŵ. The residual vector of this solutio ca be writte as [2]: r β R wˆ 4. The system i 4.0 is the solved at each time istace,. From which: R R R β β β w w wˆ 4.2 The objectives is to fid a solutio ŵ of liear equatio i 4.0 by usig the previous solutio ŵ ad the residual vector r. From this, a solutio for ŵ i 4.0 ca be described as: R [ wˆ w ] β 4.3 Usig , ad solve with respect to the ukow vector Δw, the ormal equatios i 4.0 ca the be represeted as a system of equatios [2]:

96 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 73 R w β R wˆ β R wˆ R wˆ r β R wˆ 4.4 Therefore, a solutio Δŵ ca be determie by solvig the auxiliary system of equatios: R w β 4.5 o Here: β r β R wˆ 4.6 o The approximate solutio of the origial system 4.0 ca the be determied as: wˆ wˆ wˆ 4.7 Cosiderig 4.6, this approach requires r of the origial system to be kow at each time istace. However, it ca be show that the residual vector for the solutio Δŵ to the auxiliary system 4.5 is actually equal to r of the origial system 4.0 [2]: r β R wˆ 4.8 β o R wˆ The iterative approach ca be formulated to solve the aforemetioed sequece of system equatios as illustrated i Table 4.2 [2]. At each time istace, this approach requires a solutio to a auxiliary problem 4.5 which deals with the icremet of the filter weights, Δw, rather tha the actual filter weights w, as described i the origial problem, 4.0. This approach is preferable sice it takes ito accout the accuracy of the previous solutio through the residual vector r, as well as the variatio of the problem to curretly be solved through the icremets ΔR ad Δβ [2]. The proposed approach ca also be applied to the expoetially weight RLS algorithm. This will be described i the ext sectio.

97 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 74 Table 4.2 Iteratively solvig for auxiliary equatios Step Equatio Iitialisatio: ŵ- = 0, r- = 0, β- = 0 for = 0,,. Fid ΔR ad Δβ 2 β o r β R wˆ 3 Solve R w βo wˆ, r 4 wˆ wˆ wˆ 4.6. Expoetially Weighted RLS Algorithm ERLS Expoetially Weighted Recursive Least Squares ERLS is commoly used i dyamic systems to track time varyig parameters. Geerally, a weightig fuctio is used to esure past samples are gradually forgotte if the operatig poit of the system is costatly chagig. Expoetial forgettig factor or expoetially weightig algorithm is a familiar method that used i data weightig of the system, where the weightig fuctio is give as [80]: k, k, k,2,, 4.9 Here, λ is a positive costat factor kow as the forgettig factor,. Accordig to equatio 4.9, more weight is assiged to the recetly recorded data. Approximately the value of / λ determies the memory size of the estimatio algorithm. Whe the value of λ is ear to oe, this correspodig to log memory ad if λ = ordiary RLS algorithm the memory becomes ifiite, whilst a small value of λ make the algorithm memory short [28, 80]. Therefore, the idetificatio will improve ad the estimatio for time varyig parameters will ehace, but the estimatio is more affected by the oise. However, the miimisatio of the sum of the squared error based o ERLS algorithms ca be defie as [2]:

98 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter mi ] [ k k d J T r k k T u w w w 4.20 where: П is a regulatio matrix, usually selected as: П = δ I N. I N is a N-by-N idetity matrix, ad δ is a small positive parameter ofte referred to as the regulatio parameter. Now, at each sample, the ERLS ca be used to solve the liear equatio described i 4.0. I weightig RLS, the auto-correlatio matrix ad crosscorrelatio vector are computig as [2]: d r T u β β u u R R 4.2 I order to iteratively compute the ERLS based o Table 4.2, the cross-correlatio vector β o should be preseted i terms of the filter iputs u ad the desired sigal d r. By substitute 4.2 ito 4.2, this results i [2]: d r T u β β u u R R 4.22 From 4. ad 4.22 we achieve: ˆ ] [ ˆ y u r β w R 4.23 where, at each time istat, the estimated output sigal is computed as: ˆ ˆ y T w u 4.24 The, based o 4.23 ad 4.3, the vector β o ca be described as: e p o u r β 4.25 Fially, Table 4.3 summarises the steps to fid the parameter vector ŵ, ad the computatioal effort of each step [2]. The overall complexity of the algorithm ca be show to be; multiplicatios ad additios,

99 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 76 where N is the filter order, ad are the umber of multiplicatios ad additios required to solve the liear equatio i step 5. Agai, these umbers deped sigificatly o the specific algorithms chose to solve this particular step [2]. For example, the matrix iversio lemma is oe familiar techique to complete the divisio process i step 5. I this work, we cosider the use of the DCD algorithm to achieve a computatioally light solutio to solvig this problem. Table 4.3 ERLS algorithm usig auxiliary equatios Step Equatio + 2 Iitialisatio: ŵ- = 0, r- = 0, R- = П for = 0,,. R R u u yˆ u T wˆ T 2N 2 N 2 3 e dr yˆ N N 4 βo r e u 2N N 5 R w βo wˆ, r M A 6 wˆ wˆ wˆ N 4.7 Coordiate Descet ad Dichotomous Coordiate Descet Algorithms There are may iterative methods to solve the ormal liear equatios i step 5 of Table 4.3. Solvig the liear equatios is equivalet to miimisig the followig fuctio [2, 6]: T T f w w Rw w βo Miimisig this fuctio determies the exact solutio of the ormal liear equatios. Iterative methods cosidered to miimise [7]. Typically, the iterative algorithms takes a iitial estimatio of the value deoted by Δw 0 ad at each cycle a ew sequece will be costructed Δw, Δw 2,..., Δw k [80]. At each iteratio cycle the update of the ext sequece Δw k+ is selected to be i a descedig

100 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 77 directio as [ Δ Δ ], ad is preferred to be as [ Δ Δ [7]. I this way, at each step, the algorithm cotiues to move towards the miimum of the value of. Oce the solutio of the liear equatios, approaches the desired result, the iteratio process is halted ad the estimated value, Δw k, is accepted [7]. Calculatig the step from to depeds o the choices of both the vector directio, ad the step size μ. Here, idicates the directio of movemet from to, ad μ represets the step legth alog the lie [7]. The step size μ is appropriately chose to esure that: Δ [8]. The procedure of selectig the step size is kow as a lie search method. The mai differece betwee the idividual methods is the choice of update directios ad the step size. However, it ca be show that settig the step size miimises the fuctio [2]. Therefore, to esure a reductio i the step size, the directio should be chose to be o-orthogoal to the residual vector r [6]. Details of the lie search approach take i this research are described i Table 4.4 [2, 6]. Here, N u is the umber of the iteratio. Table 4.4 Exact lie search algorithm descriptio Step Equatio Iitialisatio: Δŵ = 0,r = β o for k =,...,N u Choose a directio p such that p T r 0 2 v = Rp 3 μ = p T r/p T v 4 Δŵ = Δŵ + μp 5 r = r - μv

101 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 78 As show i Table 4.4, the step size update is ot a trivial task. It requires a matrix/vector divisio ad multiplicatio. The coordiate decet algorithm CD is oe approach which may be used to simplify the process. I the CD algorithm, the directios are selected based o the Euclidea coordiate. Here, oly the i- th elemet of vector e i is oe ad the other elemets are zeros [2]. As a result, step 2 i Table 4.4 which requires matrix-vector multiplicatio is sigificatly simplified. This results i further simplificatio of the other steps i Table 4.4 especially i step 3 ad 4 as follows [2]: v Rp R p p T T r r i v R i, i i r i wˆ i wˆ i R i, i 4.27 Here, is the i-th colum of the matrix. Whe the order of the directio is chose cyclically, as show i Table 4.5, the algorithm is kow as a cyclic CD algorithm [3]. However, i adaptive filter applicatios the cyclic approach is ot efficiet, where at each time istat, N iteratios are required [2]. Accordig to [2], the order of coordiate directio ca be chose by selectig the leadig idex i elemet as give i i arg max r 4.28 p p,, N where, arg max is the maximum argumet. This leadig idex correspods to the maximum absolute value of the residual elemet [max residual elemet ] [3]. I this way, istead of defiig the cyclic order directio, the leadig elemet is chose to speed up the covergece rate of the adaptatio process [2]. This procedure is kow as the leadig CD algorithm Table 4.6. The leadig CD algorithm requires oe divisio, N multiplicatios ad 2N additios [2, 3]. It worth otig that the DCD algorithm is derived from the CD techiques. The mai differece betwee CD ad DCD is the selectio of the step size. Here, it is

102 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 79 chose i a differet way that ca further simplify the computatio load ad preserve a faster covergece rate. Table 4.5 Cyclic CD algorithm descriptio Step Equatio + Iitializatio: Δŵ = 0,r = β o, k = 0 for i =,...,N μ = r i /R i,i 2 Δŵ i = Δŵ i + μ 3 r = r - μr i N N 4 k = k + 5 If k > N u, algorithm stop Table 4.6 Leadig CD algorithm descriptio Step Equatio + Iitializatio: Δŵ = 0,r = β o for k =,...,N u i =arg max p=,.., N { r p }, N- 2 μ = r i /R i,i 3 Δŵ i = Δŵ i + μ 4 r = r - μr i N N

103 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter Dichotomous Coordiate Descet Algorithm The DCD algorithm is similar to the CD algorithm which is based o a iterative approach to estimatig N parameters withi a estimatio parameters vector, Δŵ. The DCD algorithm begis to evaluate the residual vector ad, based o its amplitude, will update the parameters vector. Iitially, the step size, is chose such that it equals H. The durig each pass of the algorithm, the step size is halved, step. This divide by two process is very importat from a hardware poit of view. It allows a divisio operatio to be replaced with a more computatioally efficiet shift register [3]. Here, the reductio of the step size is cofigured with M iteratios. The exact umber of M depeds o the accuracy required by the applicatio. Table 4.7 Cyclic DCD algorithm descriptio Step Equatio + Iitialisatio: Δŵ = 0,r = β o, μ = H, k = 0 for m =,..,M μ = μ /2 2 Flag = 0 for i =...,N 3 If r i > μ / 2R i,i 4 Δŵ i = Δŵ i + sigr i μ 5 r = r - sigr i μr i N 6 k = k +, Flag = 7 If k > N u, algorithm stop 8 If Flag =, repeat for step 2 Table 4.7 shows the operatioal steps of the cyclic DCD algorithm [2, 3]. Step : O each pass of the algorithm, the step size is reduced util the update is complete ad the required level of accuracy is reached [3]. Steps 2-3: The magitude of the residual vector, r, is aalysed durig each pass. Two

104 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 8 outcomes are possible: a usuccessful iteratio, where the coditio set out i step 3 is ot met. I this case, the solutio ad the residual vector are ot updated, 2 A successful iteratio, where the coditio i step 3 is met. Here, the solutio i steps 4 ad 5 is updated [2]. Step 4-5: If the residual is sufficietly large Step 3: successful iteratio, oe elemet of the parameter vector is updated by addig or subtractig the value of ; depedig upo the polarity of r i. Followig this, the residual vector r is updated Step 5. For every chage of the step size, the algorithm repeats this process util all elemets i the residual vector r become small eough that the set coditio i step 3 results i a usuccessful iteratio [3], or the umber of iteratios reaches a predefied limit umber N u [2]. The iteratio limit may be used to cotrol the executio time of the algorithm. As show i Table 4.7, a major advatage of the DCD algorithm is that both multiplicatio ad divisio operatios ca be avoided. This is advatageous from a digital hardware implemetatio poit of view. Accordig to Zakharov et al. [2], the upper boud of the umber of additios usig cyclic DCD is.therefore, if, the complexity of the DCD ca be approximated by. However, if N u is small ad, the term will domiate the DCD computatioal effort [2]. The actual domiate term will be applicatio specific. Here, i the system idetificatio of a dc-dc coverter, it is foud that the secod case is geerally true;. For this reaso, a refied form of the DCD algorithm Leadig-DCD that preseted i [2] is cosidered. I this particular versio of the algorithm, it is possible to elimiate the domiat term. I the leadig-dcd, at each iteratio the algorithm begis to aalyse the residual vector ad determie the maximum absolute value of r Step, Table 4.8 [3]. This maximum absolute value of r represets the idetity of the i-th elemet leadig elemet i Δŵ to be updated [3]. Here, the update of the elemet is similar to the leadig-cd algorithm. Table 4.8 summarises the operatioal steps of the leadig- DCD algorithm [2, 3]. The umber of additios here is limited to, however, this is based o the worst case sceario ad oly results whe the update process completes N u iteratios ad the coditio i process 3 Table 4.8 is ot satisfied [5].

105 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 82 The DCD algorithms described have bee successfully implemeted i hardware usig FPGA techology [2, 3], a 6 tap-weight FIR filter is implemeted usig a Xilix-Virtex II FPGA ruig at 00 MHz clock frequecy ad the update rate up to 200 khz. The performace of this filter is close to the covetioal RLS method [2]. Table 4.8 Leadig DCD algorithm descriptio Step Equatio + Iitialisatio: Δŵ = 0, r = β o, μ = H, m = for k =,..., N u i = arg max p=,.., N { r p },go to step 4 N 2 μ = μ / 2, m = m + 3 if m > M, algorithm stops 4 if r i μ / 2R i,i, the go to step 2 5 Δŵ i = Δŵ i + sig r i μ 6 r = r - sigr i μr i N 4.8 Pseudo-Radom Biary Sequece ad Persistece Excitatio To accurately idetify the dyamic behaviour of the system ad to improve the performace of the idetificatio, the iput sigals are required to be rich i frequecy cotet. This esures that, the iput sigals are chaged or are fluctuated sufficietly to provide adequate excitatio to estimate the ukow system [72]. System idetificatio algorithms typically use the iput sigals to update their parameters; a persistetly excited iput sigal is crucial to update the estimated parameters properly. The key elemet i sigal processig applicatios such as adaptive filters is to uderstad the characteristics of the correlatio matrix which i tur leads to idetify the discrete time liear system ad discover if the iput is persistetly excited [80, 8]. The iput is persistetly excited if the correlatio matrix is o-sigular determiat of R 0, this i tur meas that the iput power

106 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 83 spectral desity is o-zero [63, 8]. Accordigly, to esure that the estimated parameters of the ukow system will covergece to their correct values, a higher order of persistetly excitatio sigal should be applied to the system; which also meas that a higher iput power spectral desity provides a better system estimatio [63]. There are differet types of iput excitatio sigals that ca be ijected ito the system durig the idetificatio process. These perturbed sigals ca take differet forms such as sie wave, white oise, or impulse sigal. A Pseudo Radom Biary Sequece PRBS is aother type of excitatio sigal that is commoly used i system idetificatio, sice it is frequecy rich ad cotais a wide rage of frequecies of iterest that provides sufficiet iformatio for the idetificatio of the system. The PRBS has very similar spectral properties to white oise [83, 9]. Therefore, it is possible to apply the PRBS to obtai a high order persistetly excited sigal to the system [63]. A PRBS is a periodic, determiistic, rectagular pulse sequece modulated i width Fig. 4.4 [20]. This sequece is easily to geerate without eed of ay radom umber i the geeratio usig a set of shift registers ad a exclusive-or gate XOR i the feedback; as depicted i Fig. 4.5, here a ie bits PRBS is utilised. This kid of the PRBS is kow as a maximum legth pseudo biary sequece MLBS. The legth or the period of MLBS sequece is, where m is iteger ad represet the umber of bits [84]. A MLBS is geerated by iteratively performig the XOR operatio betwee the k-th cell register ad a specific r-th cell register Table 4.9 [20]. For istace, the 9-bits MLBS ca be achieved by performig the XOR betwee bit 5 ad bit 9 Fig. 4.5, resultig i L = 5 [82]. At least oe value i the PRBS register should iitially be set to logic oe i order to geerate the pseudo radom sequece, s [63, 9].

107 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter Time s Fig. 4.4 Nie-bits sigle period PRBS Bit Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 s XOR Fig. 4.5 Nie-bits shift register with XOR feedback for 5 maximum legth PRBS geeratio Table 4.9 Bit cell setup for differet MLBS geeratio Number of bits m L = 2 m Bits i XOR operatio k-th, r-th bits 2 3 ad ad ad ad ad ad ,3,4, ad ad 9

108 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 85 The biary perturbatio amplitude geerated by shift registers is either oe or zero. These logic levels are usually mapped ito two possible amplitudes as preseted i A arbitrary symmetrical impulse sequece is resulted. For log sequece period this approximately has a zero mea value as described i equatio 4.30 [63, 84]. u p if s u u p if s M P L u L 0 u p L Equatio 4.3 describes the auto-correlatio properties of MLBS [63, 68], which illustrates that for very large value of L the auto-correlatio ca be approximated to a periodic sequeces of impulses as it is show i Fig. 4.6 [68]. The amplitude of these impulse is equal to at otherwise it equal to for all other. As a result, the auto-correlatio of MLBS is approximate to that of white oise [63]. Fig. 4.7 demostrate the auto-correlatio of a sigle period 9-bit PRBS. R 2 L u p 0, L, 2L, u k u k L u p k 0 else L uu u p 2-2L -u p 2 /L -L L 0 2L Fig. 4.6 Ideal auto-correlatio of a ifiite period of PRBS

109 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter PRBS legth Fig. 4.7 Sigle period 9-bit auto-correlatio of PRBS 4.9 Discrete Time Modellig of DC-DC Coverter ad Adaptive IIR Filter Discrete time modellig of a SMPC is essetial for a parametric idetificatio process. The primary cadidate model for system idetificatio i this work is the voltage trasfer fuctio cotrol-to-output trasfer fuctio. However, the importat factor i system idetificatio is to select a low complexity model that has few parameters to estimate. I cotrast, the selected model should be equivalet to the actual behaviour of the real system. ARMA model is the simplest model structure that is widely used i digital sigal processig applicatios. The ARMA model structure is a combiatio betwee Auto-Regressive AR model ad Movig-Average MA model. The AR process is defied as a liear mixture of predicts or past output values y, i this way a all-pole-filter is created, with M order model. The MA model has a opposite represetatio of AR model, i this model MA the process output is equal to the combiatio of past iput values; i this case a all-zero-filter with a N order model is costructed. Therefore, a MA model is iheretly a stable filter; hece it has a similar form of FIR filter [80]. Fially, the ARMA model with order M, N ca be costructed [70]:

110 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 87 M M N N M k k k N k k k z a z a z a z b z b z b z a z b z U z Y z G From the geeral form of the direct realisatio of the IIR filter 4.33, if M = N ad b 0 = 0. It ca be deduced that, IIR filter has a couterpart form of ARMA model [80]: N k M k k k k y a k u b y As expressed i Chapter 2, startig with the state space equivalet model of the buck coverter circuit i cotiuous time domai, it ca be show that the cotrol sigal d`s, to output voltage, v o s, trasfer fuctio is described as follow Fig. 4.: ` 2 L o L o L o C L o C o C i o dv R R L R R R R C C R s R R R R LC s s C R V s d s v s G 4.34 The average cotiuous-time trasfer fuctio described i 4.34 ca be coverted to a discrete equivalet model usig covetioal cotiuous to discrete trasformatio methods, resultig i geeral a secod order discrete trasfer fuctio: z a z a z b z b z G dv 4.35 Here, b, b 2, a ad a 2 are the parameters to be idetified. They all deped o circuit compoet values ad the samplig frequecy. The iput-output relatio give i 4.35 may also be described as a liear differece equatio: 2 ` 2 ` 2 2 d b d b v a v a v o o o 4.36 I this research, a IIR adaptive filter is employed to model the buck dc-dc SMPC. However, the DCD-RLS algorithm described i sectio 4.7 is ormally applied with FIR adaptive filters. For this reaso, a equatio error approach is developed here

111 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 88 whereby a IIR filter is effectively derived from a equatio error structure of two FIR filters, as it will be show i the followig sectio Equatio Error IIR Adaptive Filter There are two commo paradigms to realise the adaptive IIR filter: Output error scheme, ad 2 Equatio error scheme [80, 8]. Fig. 4.8 shows the block diagram of the adaptive output error IIR filter. Here, the iput sigal is applied to the both ukow system ad to the umerator, Bz of the IIR filter. The estimated sigal, ŷ is the used as a iput sigal to the deomiator, Az of the IIR filter. The error sigal e p is computed based o the differeces betwee the desired ad the estimated sigals [80], hece the ame of the output error. However, it is difficult to solve the cost fuctio i equatio 4.4 for output error IIR adaptive filter which is required a complicated mathematical aalysis [8]. This ca be solved by the secod scheme of the adaptive IIR filter equatio error IIR filter [80] which is effectively realised usig two FIR filters. I this paradigm, the error sigal is defied by a error equatio rather tha obtaied directly from the output of the IIR filter as the case of the output error model [80]. System to Idetify DPWM Switchig Power Coverter A/D y=v o d` Bz + ŷ - + ep Az b, b 2 a, a 2 Adaptive RLS Algorithm Adaptive Output Error IIR Filter Fig. 4.8 System idetificatio based o adaptive IIR filter usig output error block diagram

112 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 89 I a equatio error IIR filter, the iput sigal is applied to the ukow system ad to the first FIR filter Feed-Forward filter, thus the iput data vector ca be observed as i The secod FIR filter Feed-back filter utilises the desired sigal, illustrated i Fig. 4.9 ad the output data vector ca be give as i u FIR ` d` 2 d` d M T 4.37 u FIR2 v o vo 2 vo N T 4.38 w w FIR FIR 2 b a b 2 a 2 b T M an T 4.39 Here, the secod FIR filter does ot use past adaptive filter output samples as i the output error structure. Istead, it uses the delayed samples of the desired sigal. Thus, the miimisatio criterio is aalytically simple to derive usig this structure of IIR filter, where the iput ad output sigals are ot fuctio of the adaptive filter parameters [8], compare with the output error IIR structure. Cosequetly, the same data vector that is used i the basic idetificatio model of ARX systems [63] ca be observed i the equatio error scheme. Therefore, the iput/output differece equatio ca be writte as: [80, 8]: M N yˆ bk d` k ak vo k k k 4.40 The predictio error is defied as: ˆ y yˆ 4.4 e e

113 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 90 System to Idetify DPWM Switchig Power Coverter A/D y=v o d` Feedforward FIR Filter + ŷ - + êe Feedback FIR 2 Filter b, b 2 a, a 2 Adaptive RLS Algorithm Adaptive Equatio Error IIR Filter Fig. 4.9 System idetificatio based o adaptive IIR filter usig equatio error block diagram However, the update sequece for each FIR filters i Fig. 4.9 is ot optimal usig the DCD algorithm. Each filter requires a idepedet iput data vector ad adaptive algorithm to update a separate auto-correlatio ad cross-correlatio matrix; as defied previously i 4.9. Accordigly, the overall complexity of the adaptive filter is icreased. For this reaso, this ca be simplified by combiig the iput ad output data from the ukow system ad the parameter vectors ito a sigle data ad parameters vector [8]: φ v θ a o an, b v k, o b M T d` d` k T 4.42 Therefore, the estimatio output ca be writte as: yˆ φ T θ 4.43

114 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter Parameter Estimatio Metrics ad Validatio I parametric estimatio, several metrics may be used to evaluate the results of the idetificatio process. Predictio error, covergece rate ad parameters estimatio accuracy parameters error are the importat metrics. These factors measure the performace of the estimatio ad determie how closely the idetified model matches the actual system [3]. Accordigly, appropriate optimisatio algorithms are required to miimise the approved metrics, where these algorithms are adaptively adjusted to the cadidate model parameters util the objective fuctio is satisfied. I adaptive sigal processig algorithms, the quadratic error LS method is the popular factor to evaluate the performace of idetificatio as expressed i equatio 4.4, where the adaptive algorithms seek to miimise the summatio of the square error by fidig the optimal model parameters [28, 63]. I parametric estimatio methods, the predictio error sigal is the key elemet to miimise. Covergece rate is aother metric that measure the umber of iteratios or the time that the adaptive algorithms eed to estimate the optimal parameters. A fast covergece is essetial to track the time varyig system ad to idetify the abrupt chages i the system [80]. For istace, automatic cotrollers of SMPCs require a fast covergece rate to tue the cotroller gais ad quickly accout for ay chages i the system, such as the step load curret chage [3]. With respect to covergece time, the parameter accuracy, or the parameter error measuremet, ca be used to assess the true covergece of the parameters. The smaller the parameter error,, 4.44 the more accurate estimatio of ŵ, which i tur meas that the parameters coverge to the actual values of w. e w w wˆ 4.44 To further validate the performace of adaptive algorithms i digital implemetatios, the fiite word legth roudig-off-error ad trucatio ad quatisatio of the A/D coverter has to be take ito cosideratio as it has a effect o the parameter accuracy ad ca impact the overall performace of idetificatio [3]. I additio, fiite umeric precisio of the iput sigals ad iteral microprocessor computatios ca itroduce further errors i the system idetificatio

115 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 92 process. I particular, parameters error ad predictio error will be distorted due to these effects [8]. A method to help alleviate these side effects would be to icrease the umber of bits used withi the iteral computatio, which will reduce the umerical error variace ad thus will improve the estimatio accuracy; i this case the adaptive algorithms will be umerically stable [80]. 4. Model Example ad Simulatio Results I order to test the cocept of the proposed DCD-RLS idetificatio scheme Fig. 4., a voltage cotrolled sychroous dc-dc buck SMPC circuit has bee simulated usig MATLAB/Simulik see appedix C. The circuit parameters of the buck coverter are: R o = 5 Ω, R L = 63 mω, R C = 25 mω, L = 220 µh, C = 330 µf, V o = 3.3 V, V i = 0 V, H s = 0.5. The series resistace R S = 5 mω is added to measure the iductor curret; thus the equivalet series resistace R q = R L + R S = 68 mω. The R Dso of the power MOSFET ca also be added to the equivalet series resistace. The buck coverter is switched at 20 khz ad the output voltage is also sampled at the same switchig frequecy rate. Cosequetly, the cotrol-to-output voltage discrete trasfer fuctio of the SMPC ca be calculated as follow: G dv 0.226z z.94z 0.8z 0.949z For the expoetially weighted leadig elemet DCD-RLS algorithm Table 4.8, the parameters are as follow: N u =, H =, M = 8. The forgettig factor is chose as λ = 0.95 ad the typical value of regulatio factor chose as δ = 0.00 [72]. For completeess, the simulatio model icludes all digital effects; such as ADC quatisatio ad sample ad hold delays. To preset the viability of the proposed DCD-RLS algorithm, a equivalet system based o a covetioal expoetially weighted RLS usig matrix iversio lemma is also simulated Table 4.. The same settigs ad iitial coditios are used for both DCD-RLS ad covetioal RLS algorithms. For a regulated SMPC, the digital PID gais are tued usig a polezero matchig techique that preseted i Chapter 2. The PID cotroller is expressed as follows:

116 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 93 G c z 2 q0 qz q2z z 4.46 where, q o = 4.27, q = 7.84, ad q 2 = It is importat to metio that, the system model ad the loop cotrol desig are simulated ad evaluated i Chapter 2. Fig. 2.8 ad Fig. 2.2 preseted the tested results of the closed loop system. Normal PID Compesator ID-Eable NO Yes Iject PRBS Cycle-by-Cycle O-lie Idetificatio DCD-RLS ID-Complete a, a 2, b, ad b 2 G dv z Fig. 4.0 The procedure of system idetificatio Based o the system i Fig. 4., the system idetificatio sequece is described by the flowchart i Fig. 4.0, whilst the correspodig step-by-step results are illustrated i Fig. 4.. Iitially, the system is operatig ormally ad is regulated by the PID compesator. Whe the idetificatio process is eabled as show i Fig. 4.e, a 9-bit PRBS is ijected ito the feedback loop as a frequecy rich excitatio sigal as show i Fig Here, as a example, the PRBS sigal is ijected durig the steadystate period for 20 ms, superimposed with the cotrol sigal as depicted i Fig. 4.a, b. This is sufficiet to determie the parameter covergece time. The PRBS

117 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 94 samplig frequecy, f P, is selected as 20 khz. From this, the maximum PRBS pulse legth is 5, ad the magitude of PRBS sigal, PRBS = ± This is sufficietly small to cause excitatio i the PWM output, but ot eough to sigificatly compromise the ormal operatio of the SMPC; the output voltage ripple caused by this perturbatio sigal is approximately ± 2% of the dc output voltage, as show i Fig. 4.a. As each PRBS sample is ijected, the DC compoets are removed from the iput ad the output, thus a zero mea value is determied i the iput/output sigal. The DCD-RLS is the measures the cotrol output sigal, d`, ad the sampled power coverter output voltage, v o. The algorithm is implemeted ad the IIR filter tap-weight estimatio is updated. The effectiveess of the algorithm is verified i Fig. 4.c, d. The algorithm rapidly estimates the SMPC parameters [a, a 2, b, ad b 2 ] ad the miimises the error predictio sigal. It is worth otig that the iitial value for each parameter is assumed to be zero. This demostrates that prior kowledge of the SMPC parameters is ot essetial for covergece of the algorithm.

118 ID-Ea Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter a, Time s b,times a 2 b 0 b 2 - a c,times d, Time s e,times Fig. 4. Idetificatio sequece, a: output voltage durig ID, b: voltage model parameters ID, c: voltage error predictio, d. ID eable sigal

119 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 96 Fig. 4.2 shows a compariso betwee the DCD-RLS idetificatio algorithm ad the classical RLS idetificatio method. As depicted i Fig. 4.2, the DCD-RLS algorithm coverges quickly less tha 0 ms ad idetifies the ukow IIR filter coefficiets. This i tur miimises the predictio error sigal as show i Fig Both techiques appear to coverge to the same estimatio values. The actual estimatio error is illustrated i Fig. 4.4, where it ca be see that the performace of the DCD-RLS is comparable with the covetioal RLS scheme. Fig. 4.4a, b demostrates the parameters estimatio error for the classical RLS scheme ad DCD- RLS algorithm respectively. It is worth otig that the DCD-RLS estimatio accuracy ca further be improved by icreasig the umber of iteratios N u, or the umber of step size update M. I the algorithm results are also preseted where the effective resolutio is reduced; M = 4. Fig. 4.5 compares the estimatio performace of DCD- RLS with the covetioal RLS method; the umber of iteratios, N u = 4. It is observed that the DCD-RLS performace is ehaced ad approaches the characteristics of the covetioal RLS method. Makig this adjustmet will icrease the executio time of the algorithm but, with may systems, a compromise betwee complexity ad accuracy must be established. The estimatio performace of the DCD-RLS is also compared to the leadig CD algorithm. Fig. 4.6, clearly shows that the covergeces of the parameters i the DCD-RLS algorithm is faster tha those obtaied with the CD algorithm; ad as metioed previously requires less computatio. Further validatio of the proposed algorithm is observed whe comparig the frequecy respose characteristics of the estimated ad calculated discrete time model as show i Fig It ca be see that the DCD-RLS algorithm is closely matched to the cotrol-to-output model of the of the dc-dc coverter. The versatility of the proposed DCD-RLS scheme has bee verified with a rage of the dc-dc discrete time models duty-to-output voltage trasfer fuctio. I each case, the proposed method show very promisig results ad ca hadle a wide rage of ucertaity i the SMPC parameters. Table 4.0 presets three example systems, clearly showig how the algorithm closely matches the actual parameters for each buck coverter model. Here, the parameters estimatio accuracy has bee measured at the fial covergece values.

120 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter a 2 Parameters b 2 Parameters b Parameters DCD Parameters... RLS Parameters Model Parameters a Parameters Times Fig. 4.2 Tap-weights estimatio for IIR filter usig DCD-RLS ad classical RLS methods; compared with calculated model a, Time s b, Time s Fig. 4.3 Predictio error sigals, a: classical RLS, b: DCD-RLS

121 Estimatio Error Estimatio Error Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter Time s a Time s b Fig. 4.4 Parameters estimatio error, a: classical RLS, b: DCD-RLS

122 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter a 2 Parameters b 2 Parameters b Parameters DCD Parameters... RLS Parameters Model Parameters a Parameters Times Fig. 4.5 Tap-weights estimatio DCD-RLS at Nu = 4 ad classical RLS b 2 Parameters a 2 Parameters b Parameters DCD Parameters... CD Parameters Model Parameters a Parameters Times Fig. 4.6 Tap-weights estimatio DCD-RLS ad CD algorithms

123 Phase deg Magitude db Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter Frequecy Hz Fig. 4.7 Frequecy resposes for cotrol-to-output trasfer of fuctio; estimated ad calculated model Table 4.0 Discrete time cotrol-to-output trasfer fuctio idetificatio SMPC Model Buck Buck 2 Buck 3 Duty-to-Output Trasfer Fuctio G dv G dv G dv z z 0.925z z z.82 z z z.895 z Estimatio Parameters { b, b 2, a ad a 2 } {0.304, 0.79, 0.944,.9258 } {0.3398, 0.062,.8203, } {0.44, 0.253,.875, }

124 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter Adaptive Forgettig Strategy Usig recursive estimatio ad adaptive techiques for time varyig systems is a importat issue i a dyamic system where the behaviour, ad hece parameters, of the system may chage over time. It is importat to moitor behavioural chages to optimise the cotroller desig [2]. The RLS remais a effective idetificatio method i trackig time-varyig systems. However, rapid chages of parameters lead to umerical problems due to small data sets. For this reaso, a appropriate choice of forgettig factor λ is vital, where the sesitivity of a estimate ca be improved by adjustig the forgettig factor effectively. Geerally, the forgettig factor is varyig betwee [74]. Small values of forgettig factor will lead to improvemets i trackig ability. However, the RLS algorithm becomes more sesitive to oise. I cotrast, large values of the forgettig factor will result i a poor trackig ability at slow parameter variatios. However, the RLS algorithm is less sesitive to oise [22]. As a result, applicatio of a adaptive forgettig factor method to a dc-dc coverter system is proposed i order to make the idetificatio algorithm more sesitive to chage durig system parameter chages, by assigig more weight to recet samples. Differet techiques are proposed i the literature usig the adaptive forgettig factor [2-24]. The accuracy, complexity, robustess, ad the trackig ability are the mai factors to cosider whe selectig the appropriate adaptive forgettig factor. I this thesis, a method from the telecommuicatio field is adopted origially preseted by Chia et al. [24] to track the load chages i a closed loop dc-dc coverter. This method uses a fuzzy variable forgettig factor RLS FRLS Fuzzy RLS Adaptive Method for Variable Forgettig Factor The FL system has bee extesively used i various applicatios, ad is popular i feedback cotrol desig, automatic cotrol system, ad system idetificatio processes [25]. The FL system deals with liguistic variables rather tha umerical umbers to achieve the desig goal, without a mathematical model of the process. This is accomplished by covertig the expert liguistics descriptio ito a desired strategy. Liguistic variables are forms of words that give the best descriptio to iput variables [26]. Fig. 4.8 illustrates the proposed adaptive forgettig factor AFF for a dc-dc coverter usig the FL system. Here, a fuzzy adaptatio block is

125 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 02 desiged to cotiually update the forgettig factor, based o two iputs: the squared predictio error ad the squared chage of predictio error [e 2 p, Δe 2 p ]. Oe of the best sigals utilised i RLS i respect to moitorig ad supervisio the performace of the RLS, is the value of e 2 p [2]. The rate of the square predictio error is defied as: e p ep ep 4.47 System to Idetify DPWM Switchig Power Coverter A/D v o d` + IIR filter ŷ e p a,a 2,b,b 2 RLS Algorithm λ Fuzzy RLS-IIR AFF Fuzzy Adaptatio Δe p 2 * z - e p 2 Fig. 4.8 The proposed system idetificatio structure for a dc-dc coverter based o RLS fuzzy AFF The distict advatage of this method is i respect to the oliear chages withi the error sigal. This is a result of the chage i the model parameters. The FL rules based ca be mapped this chages i the error sigals ad therefore, defiig a better forgettig factor. A more precise dyamic ad adaptatio capability ca be defied by usig the two iputs, [e 2 p, Δe 2 p ]. The istataeous chage of the predictio error sigal ca be exploited withi the FL system by utilisig the Δe 2 p sigal. This will provide ivaluable assistace to the FL system for it to select the desired forgettig factor to be icorporated withi the RLS algorithm [24].

126 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 03 e p 2 Δe p 2 Fuzzificatio Iferece Mechaism Defuzzificatio λ Fuzzy Rule Base Fig. 4.9 Geeral block diagram of the fuzzy logic system Geerally, the FL system or adaptatio block i Fig. 4.8 is composed ito three mai sectios Fig. 4.9 [25]: - Fuzzificatio: i this phase the FL iputs [e 2 p, Δe 2 p ] are coverted ito iformatio that the iferece mechaism ca easily use to fid the successful rules which map to oe of the defied fuzzy sets. This is achieved by assigig each poit i the iput sigal a membership degree. For simplicity of desig a triagular membership fuctios are typically used i the fuzzificatio step [24]. Here, the umber of membership fuctios are trimmed compared with [24], thus the computatio load of the proposed solutio of AFF will be reduced. However, the umber of membership fuctios is maily depedet o the accuracy of the chage i predictio error. As show i Fig. 4.20a, b, c, there are five membership fuctios for e 2 p, four membership fuctios for the secod iput Δe 2 p, ad five output membership fuctios. The liguistic labels are {Very Small, Small, Medium, Large, Very large}, but for brevity are referred to as {VS, S, M, L, VL}. The uiverse of discourse for the iputs is chose betwee 0 ad 0. as show i Fig. 4.20a, b, whilst the uiverse of discourse for the output is varied betwee 0 ad as show i Fig. 4.20c. The choice of these values will sigificatly affect the performace of AFF. 2- Iferece Mechaism: the coectio betwee the fuzzifed iput ad the output fuzzy sets are achieved usig the iferece mechaism. Fuzzy rule base are used to obtai the combiatio betwee the fuzzifed iputs to fuzzy

127 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 04 output. A set of If-The expressios are used to describe these relatios [25]. Table 4. shows the rule base that was developed i this AFF. A set of 20 rules are used i AFF [2, 24] for system idetificatio of the dc-dc coverter. Whe the predictio error abruptly icreases, perhaps as a result of a step chage i load, λ will quickly decrease to compesate for the chage. This occurs whe the predictio error sigal is high, thus e 2 p is VL ad the Δe 2 p is VL, a VS value is assiged to λ to icrease the rate of covergece [24]. Whe the predictio error approaches zero, represetig the steadystate, λ will settle to a costat value, typically approachig a high value. Here, e 2 p is VS ad Δe 2 p is S the VL is assiged to the FL output. However, to prevet the λ becomig too small, ad to obtai a acceptable covergece rate at start up, a statioary rule should be added [2]. This rule is activated whe e 2 p is VL ad Δe 2 p is S, thus λ is M. 3- Defuzzficatio: as show i Fig. 4.9, the iput of this phase is the fuzzy set ad the output is a real umber. Cetre of area or gravity is used to calculate the forgettig factor, as preseted the followig equatio [24, 25]: q j q j j j j 4.48 where, μλ j is the membership grade of the elemet λ j ad q is the umber of the activated rules.

128 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter μ ep2 VS S M L VL 2 e p a μ Δep S M L VL S Δe p 2 b μ λ VS S M L VL λ c Fig Fuzzy logic iput ad output membership fuctios, a: e p 2, b: Δe p 2, c: λ

129 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 06 Table 4. The rule base for the forgettig factor λ e p 2 VS S M L VL Δe 2 p S VL L M VS M M L L M S VS L L M M S VS VL VL M S VS VS 4.3 Simulatio Test Similar circuit parameters to those outlied i sectio 4. are chose. To demostrate the effect of the forgettig factor for trackig the time varyig parameters i a dc-dc coverter, we assume that the load is chagig abruptly from 5 Ω-to- Ω at each 0. s. This yield: Gdv z at Ro Gdv z at Ro z 0.8z z 0.949z z 0.062z 2.8z z This cosiderable chage i the load of the dc-dc coverter is chose to clearly observe the trackig ability of RLS algorithm. A 9-bit PRBS with PRBS = ± amplitude is superimposed with the cotrol sigal as a rich excitatio sigal. Similar settigs for the PID compesator, PRBS geerator, ad DCD-RLS are chose as outlied i sectio 4.. Iitially the parameter values are set to zeros. The deomiator parameters [a, a 2 ] are the oly parameters i the cotrol-to-output trasfer fuctio preseted i the estimatio results. This is because the pole parameters vary sigificatly durig the load chage as described i equatio 4.49 ad 4.50, thus makig the system disturbace easy to detect. The desig of the FL system is carried out usig MATLAB Fuzzy Logic toolbox.

130 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 07 The trackig ability of the algorithm at a small fixed value of forgettig factor λ = 0.7 is preseted i Fig. 4.2a. It ca be see that the covergece rate durig iitial start-up ad at sudde load chages is rapid, but the estimated parameters chatter aroud the steady-state value makig the estimatio more sesitive to oise, ad thus the fial covergece values are difficult to determie. A similar settig is used with a higher forgettig factor λ = 0.99 as show i Fig. 4.2b. As expected, the covergece rate is relatively slow durig the iitial start-up of the system, where it takes approximately 50 ms; but the estimated parameters are less sesitive to oise. However, as illustrated i Fig. 4.22, the predictio error sigal provides a opportuity to both moitor the parameters chage with the system, ad to be icluded withi the idetificatio algorithm where, at iitial system start-up ad durig load chage, there is a greater disturbace i the predictio error sigal. Therefore, a variable forgettig factor relyig o predictio error sigal ca be applied to track this chage i the system parameters, as well as to icrease the covergece rate. The proposed AFF structure i Fig. 4.8 has bee employed to track the abrupt load chages i the dc-dc coverter. The result i Fig. 4.2c shows the effectiveess of the proposed AFF usig the fuzzy logic system, where the algorithm successfully estimates the system parameters quickly durig the iitial start-up ad at abrupt load chages with accurate estimatio metrics. Fig show the chage of variable forgettig factor. This forgettig factor is directly liked to the parameter variatio durig the load chage. This clearly shows that at a high chage of predictio error, the AFF produces a small λ ad at a steady-state the forgettig factor the recovers to a high value aroud λ The rapid chage, ad recovery, of the forgettig factor demostrates the ability of the method to track parameter chages.

131 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 08 0 a 2 - a Time s a 0 a 2 - a Time s b 0 a 2 - a Time s c Fig. 4.2 Parameters estimatio of cotrol-to-output voltage trasfer of a dc-dc coverter at load chages from 5-to- Ω usig DCD-RLS algorithm at a: λ = 0.7, b: λ = 0.99, c: fuzzy AFF

132 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter x Time s Fig Predictio error sigal durig iitial start-up ad at load chage x Time s Fig Forgettig factor at iitial start-up ad at load chage However, cotiuous moitorig ad estimatio of time varyig parameters required cotiuous ijectio of excitatio sigal i the feedback loop. Therefore, a small oscillatio is cotiuously observed i the output respose of SMPC. Here, the

133 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter 0 perturbatio sigal is approximately equals to ± 2 % of the regulated dc output voltage which is chose to be 3.3 V. Aother cocer is the resultat computatioal burde from applyig the AFF/FL system. To reduce the system complexity, a FL system ca be implemeted usig a two dimesioal look-up table which ultimately reduces the amout of computatio required. I real time implemetatio, a trade-off betwee the size of the look-up table ad the estimatio performace should be cosidered. 4.4 Chapter Summary I the area of system idetificatio, least square methods, like the basic RLS algorithm, provide promisig results i terms of fast covergece rate, small predictio error, ad accurate parametric idetificatio. However, they ofte have limited applicatio i SMPC ad other low power, low cost applicatios due to computatioally heavy calculatios demadig sigificat hardware resources. Therefore, this chapter has itroduced a ovel computatioally efficiet DCD-RLS method to overcome some of the limitatios of may classic RLS algorithms. The process is based o a proposed equatio error IIR adaptive filter scheme, which is well suited for SMPC parameter estimatio. The system idetifies the IIR filter tapweights o a cycle-by-cycle basis by ijectig a perturbed iput sigal ad moitorig the correspodig output respose. The proposed solutio demostrated that the idetificatio algorithm is able to work cotiuously i the cotrol loop ad quickly miimise the predictio error power; thus estimate the model parameters. Simulatio results demostrated that this approach exhibits very good idetificatio metrics covergece rate, parameters estimatio, ad predictio error ad the performace is comparable to more complex solutios such as recursive least squares techiques. The proposed scheme ca be easily accompaied with may adaptive cotrol solutios. The secod ew scheme i this chapter is the adaptive forgettig factor based o fuzzy logic system. A two iput, sigle output, fuzzy adaptive forgettig factor techique was applied to improve the estimatio process durig time varyig system, such as abrupt load chages. This method has a simple structure, detectig the fast chage i the system via sudde chage i voltage predictio error. The AFF

134 Chapter 4: SI of DC-DC Coverter Usig A Recursive DCD-IIR Adaptive Filter structure has bee validated by simulatios ad the results showed that the covergece rate ad the estimatio of the model parameters are very good i this method, where the abrupt chages of load are adapted to very quickly ad smoothly via the variable forgettig factor which simply respods to parameters chage. The adaptive forgettig factor method was successfully employed for the first time to the DCD-RLS algorithm. I summary, the proposed DCD-RLS algorithm ca be implemeted for may alterative applicatios where efficiet ad accurate parameter estimatio is required.

135 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 2 Chapter 5 ADAPTIVE CONTROL OF A DC-DC SWITCH MODE POWER CONVERTER USING A RECURSIVE FIR PREDICTOR 5. Itroductio May classical digital cotrol systems for SMPCs suffer from iaccuracies i the desig of the cotroller. Therefore, auto-tuig ad adaptive digital cotrollers are playig a icreasigly importat role i SMPC systems. Adaptive digital cotrollers offer a robust cotrol solutio ad ca rapidly adjust to system parameter variatios. This chapter presets a ew techique for the adaptive cotrol of power electroic coverter circuits. The proposed techique is based o a simple adaptive filter method ad uses a oe-tap FIR-PEF. This is a computatioally light techique based aroud the previously described DCD-RLS algorithm. I this case, the DCD-RLS algorithm is applied as the adaptive PEF. As a result, compared to the existig RLS algorithm, the computatioal complexity is reduced. Results show the DCD-RLS is able to improve the dyamic performace ad covergece rate of the adaptive gais withi the cotroller. I tur, this yields a sigificat improvemet i the overall dyamic performace of the closed loop cotrol system, particularly i the evet of abrupt parameter chages. The results clearly demostrate the superior dyamic performace ad voltage regulatio compared to covetioal PID ad adaptive LMS cotrol scheme, with oly a modest icrease i the computatioal burde to the microprocessor. The proposed cotroller uses a adaptive Proportioal-Derivative + Itegral PD+I structure which, alogside the DCD algorithm, offers a effective substitute to a covetioal PID cotroller. The o-adaptive itegral cotroller +I, itroduced i the feedback loop, icreases the excitatio of the filter tap-weight ad

136 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 3 esures good regulatio. The approach results i a fast adaptive cotroller with selfloop compesatio. This is required to miimise the predictio error sigal, ad i tur miimise the voltage error sigal i the loop by automatically calculatig the optimal pole locatios. The predictio error sigal is further miimised through a secod stage FIR filter adaptatio gai stage. This esures the adaptive gais coverge to their optimal value. 5.2 Self-Compesatio of a DC-DC Coverter Based o Predictive FIR v i t Q Q 2 v o t R L L R C C DC-DC Buck Coverter R o ct Driver Hs DPWM d + U d + U I Itegral Compesator K I z z e A/D v o + V ref Fixed Gai e p2 K Kd Kd DCD-RLS Adaptive FIR 2 Filter Gai Adaptatio Stage2 FIR e p e p TMS320F28335 DSP Core/ Adaptive PD+I DCD-RLS Adaptive FIR Filter Error Predictio Stage FIR e e Adaptio time Adaptive PD Cotroller & Two Stages FIR Predictor t Fig. 5. Adaptive PD+I cotroller usig oe tap DCD-RLS PEF Fig. 5. shows a block diagram of the proposed cotrol scheme. Here, a similar PD cotrol method to Kelly ad Rie [96, 97] is employed. However, a o-adaptive itegral compesator is icluded i the feedback loop. This replaces a referece voltage feed-forward path i the origial scheme. I this way, we look to achieve a

137 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 4 adaptive PD+I cotroller. The itegral compesator has a umber of roles. First, durig the iitial covergece time for the filter tap weight, the itegral compesator is used to excite the system. The itegral effectively itroduces a trasiet, which is the amplified. This, i tur, iitiates a oscillatio i the cotrol error sigal. The excitatio sigal improves the covergece time of the adaptive filter, the time to obtai optimal taps weight parameters. It also allows the adaptive cotroller to work cotiuously i a o-lie mode. The advatage of this scheme is that the adaptive PEF rapidly lears the behaviour of the oscillatio created by the itegral compesator ad rejects it from the cotrol loop. Therefore, for the majority of the time a smooth output respose is observed. The oscillatio i the output voltage respose oly appears for a very brief period of time, sufficiet for idetificatio purposes. The fial purpose of the itegral compesator is more obvious; it helps output voltage regulatio ad esures zero steady-state error i the system. Whe actually choosig the value of itegral gai K I, a compromise exists betwee the magitude of the excitatio sigal i the loop ad the eed to avoid uwated LCOs. At the output of the PD compesator, a fixed gai K is icluded i the cotrol loop Fig. 5.. This gai icreases the excitatio util the adaptive filter weight coverges to the optimal value. For the buck coverter system uder cosideratio, K = L/T, where T is the switchig period ad L is the iductor value [96]. 5.3 Auto-Regressive / Process Geeratio, Idetificatio To implemet a PEF as the cetral cotroller i the feedback loop requires the realisatio of a Auto-Regressive AR process geerator, followed by a AR idetifier Fig v AR u AR v^ Process Idetifier Fig. 5.2 Recostructio of white oise

138 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 5 The AR process geerator is defied as a all pole filter. The iput is typically a white oise sigal, v, whilst the AR process output, u, is ormally a o-white sigal [96]. The differece equatio for this filter ca be described as: u au am u N v 5. Fig. 5.3 depicts the AR process geerator model. To stabilize the AR filter, it is ecessary to place all roots of the characteristic equatio iside the uit circle of the z-pla 5.2. Therefore: 2 N a z a2z... a M z White oise v -a u AR Process u- z - -a 2 u-2 z - u-n -a M z - Fig. 5.3 AR process geerator Now, to idetify the ukow AR process, ad to reproduce the white oise iput of the AR filter; a matchig iverse filter must be desiged; this is kow as a Movig Average MA filter which is also referred to as a all zeros filter or FIR filter. Therefore, the output of the AR process filter is preseted to the AR idetifier Fig. 5.4, whose trasfer fuctio is described as [80]: N V z H ARA az U z H ARG 0 5.3

139 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 6 Here: H ARA is the trasfer fuctio of AR aalyser, H ARG is the trasfer fuctio of the AR geerator, ad a 0 =. This filter is itrisically stable. u AR Process u- u-2 u-n z - z - z - a a 2 a M v White oise Fig. 5.4 AR process idetifier 5.3. Relatioship betwee Forward Predictio Error Filter ad AR Idetifier A forward predictio filter is defied as a liear predictor that represets the combiatio of the past samples of the iput sigal [u-, u-2,..., u-n]. This filter cosists of N uit delays ad tap weights [80]. As show i Fig. 5.5 the estimated output ŷ of the forward predictor is the predictio of the preset iput sigal u. Mathematically, the estimated output ca be described as: N yˆ wku k w T u k 5.4 where: w w w 2 u u w N T u 2 u N T 5.5 The predictio error, e p, is defied as the differece betwee the desired sigal ad the estimated output sigal, ŷ. Here, the desired sigal is equal to the iput sigal u. Therefore: e p u yˆ 5.6

140 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 7 u u- u-2 u-n z - z - z - w w 2 w N ŷ Fig. 5.5 Oe step ahead forward predictor By substitutig equatio 5.4 ito equatio 5.6, ad combiig both terms ito a sigle summatio, the PEF ca be expressed as: N e p wf ku k k where: wf k w k k 0 k,2,, N 5.8 This is depicted i Fig The legth of the oe step ahead forward predictio filter is oe less tha the legth of the predictio error filter [compare equatio 5.4 ad 5.7]. However, the umber of delay elemets ad the order of both filters are the same. I such a way, the relatioship betwee the PEF error filter ad the AR idetifier filter is illustrated as it is shows i Fig. 5.7 [80]. I order to defie the vector coefficiets, w, of the liear predictio filter, aalytical calculatio of the liear system equatios is required. Adaptive algorithms such as LMS ca be used to optimally calculate the vector coefficiets filter tapweights ad reduce the computatioal load. Thus, a adaptive PEF ca be applied to predict the AR process ad recostruct the origial sigal. The differece equatio for the AR model has the same form as the differece equatio of a PEF. Therefore, the forward predictio filter ca be applied as the AR idetifier [80, 96].

141 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 8 u u- u-2 u-n z - z - z - wf 0 wf wf 2 wf N e p Fig. 5.6 Forward predictio error filter u z - u- Forw ard e P Predictor - + Fig. 5.7 Predictio error filter To clearly uderstad the aforemetioed descriptio, suppose a secod order AR model with costat filter coefficiets a = 0. ad a 2 = 0.5. The iput of the filter is a radom oise ad the MA filter is desiged to be exactly the iverse trasfer fuctio of AR filter as first show i Fig Therefore, assumig a perfect desig, the poles of the AR filter are cacelled by the zeros of the MA filter. I this case, as show i Fig. 5.8 a, the iput sigal radom oise ad the output sigal are idetical I Fig. 5.8, the dotted lie is the estimated output ad the solid lie is the actual iput. However, i practice, the AR process geerator is ukow; cosequetly, the MA filter must idetify the process sigal ad attempt to recostruct the origial sigal. Adaptive filter algorithms ca also be used to optimally calculate the tap-weight of the MA filter. Therefore, a adaptive PEF ca be applied to predict the AR process ad recostruct the origial sigal. This is clearly demostrated i Fig. 5.8b, c. Here, a oe/two tap PEF is desiged to idetify the AR filter coefficiets ad recostructed the iput sigal. It is worth otig that the AR process is assumed to be a secod order filter, thus a two tap PEF will provide better predictio results tha the suggested oe tap PEF. This will lead to a more optimal estimatio process. However, the first order PEF filter still produces a

142 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 9 reasoable estimatio of the AR model ad reduces the computatioal overhead. I this specific applicatio, this is deemed to be a worthwhile compromise Times a Times b Times c Fig. 5.8 AR aalyser, a: matched Iverse MA filter, b: oe tap adaptive PEF, c: two tap adaptive PEF filter. The dotted lie is the estimated output ad the solid lie is the actual iput

143 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor Oe-Tap Liear FIR Predictor for PD Compesatio A digital FIR filter ca be described, i differece equatio form, by equatio 5.. From this, it is possible to describe the digital filter i the z-domai as: ˆ 2 2 N Y z U z w z w z w N z 5.9 Referrig to Fig. 5.6 ad usig equatio 5.7 ad 5.8, a FIR-PEF ca therefore be represeted i z-form as: EP z w z U z 2 w2 z w N z N 5.0 The order of the digital filter cadidate model is applicatio depedet. SMPC systems ca usually be satisfactorily compesated with a secod order digital filter. However, as described i [57, 96], a secod order miimum phase plat, such as a buck coverter, ca be compesated usig a typical MA filter with β parameters oly 5. of pole placemet cotroller as: 2 o z 2z Dz 2 Gc z o z 2z z z Ez 5. By settig the order of the PEF filter to oe order lower tha the plat, the PEF is equivalet to a cotroller desig based o the pole placemet method preseted by Kelly ad Rie [57], where the order of the cotroller is also less tha the order of plat by oe. By comparig 5.0 with 5., a low order approximatio FIR-PEF ca actually be implemeted as a gai cotrollable compesator [96]: o z Kd w z 5.2 Equatio 5.2 is equivalet to a PD cotroller. Importatly, it oly requires oe additio ad oe multiplicatio operatio. A good quality regulator is required to optimally place the poles withi the z-plae uit circle [57, 96]. This is the secod purpose of the two-stage adaptive liear predictor show i Fig. 5.. I the first stage FIR, the adaptive algorithm places a zero w as close as possible to the domiat

144 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 2 poles of the auto-recursive model to miimise the error i the loop [27]. I the secod stage, the adaptive algorithm estimates ad adapts the gai K d to miimise the predictio error i the adaptive filter. Coveietly, the adaptatio of K d is performed by the same mathematical process as the stage FIR filter. However, here the FIR filter uses the predictio error sigal e p as a iput sigal [96], rather tha the voltage error sigal Fig. 5.. Fially, automatic adjustmet of K d, w reduces the variace of the predictio error ad iflueces the fial cotroller output duty sigal. This PD cotroller is the icorporated with the itegral compesator to form the PD+I structure. As a result, a low complexity adaptive cotroller is achieved. This cotroller is capable of self-regulatio, by fidig the optimal cotrol parameters, without explicit kowledge of the actual circuit parameters. 5.4 Least Mea Square Algorithm Geerally, to determie the optimal estimated parameter the adaptive algorithm requires solvig a set of ormal equatios give by 4.0 [ ]. This ca simply be achieved by performig the lie search approach i the directio p egative to the gradiet vector of the miimisatio fuctio 5.3. This techique is kow as Gradiet descet method [80]. f w p g f w w 5.3 Geerally, iterative computatio of the filter weights take the followig form [80]: w w p, 0,, Where, w is the filter vector tap-weights, μ is the step size ad p is a vector directio. Now, by isertig 5.3 ito 5.4, the iterative update of the filter coefficiets ca be writte as [80]: w w g, 0,, I the LMS algorithm, the estimated filter coefficiets are calculated based o the miimisatio of the mea square error MSE [8]:

145 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 22 E[ e 2 ] E d r w E[ d T u 2 r 2 ] 2w T E[ d r u ] w T E[ u u T ] w 5.6 Here, is the expectatio operatio. Equatio 5.6 ca be further simplified as [8]: 2 2 T T E[ e ] E[ d r ] 2w β w Rw 5.7 where: T R E[ u u ] 5.8 β E[ dr u ] It ca be otice that equatio 5.7 is a quadratic fuctio of the filter tap-weights w; thus there is oly oe value that results i a miimum mea square error. This value is fouded at the optimal value of the filter tap-weights. The optimal value is computed by settig the derivative with respect to w equal to zero [8]: 2 E[ e p ] g 2β 2Rw w 5.9 g 2 Rw β 0 wopt R β 5.20 Here, w opt is the optimal solutio of the liear equatio i This solutio is kow as the Wieer solutio [8]. By substitutig 5.9 ito 5.5, the update coefficiets equatio ca be represeted as: w w Rw β 5.2 I summary, to fid the optimum filter coefficiets: at each iteratio compute the gradiet vector usig 5.9 ad the 2 update the tap-weights vector usig 5.2. However, i real time implemetatio, the computatio of R matrix ad β vector is ot available. This ca be simplified by usig the istataeous value of vector β ad the matrix R istead of their actual value [80, 8]:

146 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 23 ˆ T R u u βˆ dr u 5.22 where, Rˆ ad βˆ are the istataeous estimatio of R ad β. From this, equatio 5.9 ca be writte as [8]: g T 2 dr u u u w T 2u [ u w dr ] 2e u 5.23 By isertig 5.23 ito 5.5, the update coefficiets vector ca be give as [80]: w w e u 5.24 The aforemetioed procedure is kow as LMS algorithm. Step-by-step operatio of the LMS algorithm is depicted i Table 5. ad Fig. 5.9 [80]. It ca be see that the LMS is a simple ad low complexity algorithm, where at each iteratio it requires oly N + multiplicatios for the error geeratio Step 2 ad N + 2 multiplicatios Step 3 for the update of the filter coefficiets [8]. However, the major drawback of the LMS algorithm is the speed of covergece, sice there is oly oe parameter μ to cotrol the covergece rate. The covergece of the LMS algorithm depeds maily o the step size factor, μ. Geerally, the rate of covergece is iversely proportioal to the step size. If μ is large, the covergece is relatively fast, but less stability is observed aroud the miimum value. O the other had, if the step-size is small the covergece rate will be slow but more stable aroud the miimum poit [80, 8].

147 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 24 Table 5. LMS algorithm operatio Step Equatio Iitialisatio: ŵ0 = 0, u0 = 0, μ = positive costat value for =, 2, yˆ u T wˆ 2 e dr yˆ 3 wˆ wˆ e u d r μ e + u T u ŵ+ X z - ŵ Fig. 5.9 Closed loop LMS system block diagram 5.5 Simulatio Results The proposed DCD-RLS adaptive cotrol scheme Fig. 5., for voltage cotrolled sychroous dc-dc buck SMPC circuit has bee simulated usig MATLAB/Simulik. The circuit parameters of the buck coverter are the followig: R o = 5 Ω, R L = 63 mω, R C = 25 mω, L = 220 µh, C = 330 µf, V o = 3.3 V, ad V i = 0 V. The buck coverter is switched at 20 khz usig covetioal pulse width modulatio. The output voltage is also sampled at 20 khz. For the DCD-RLS algorithm, the parameters are as follow: N u =, H =, M = 4. For completeess, the simulatio model icludes all digital effects, such as ADC, quatisatio, ad sample ad hold delays see appedix C. To preset the feasibility of the proposed DCD-RLS algorithm, a equivalet system

148 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 25 based o the covetioal LMS adaptive cotroller preseted i [96, 97] is also simulated. A secod alteratio to the origial structure i [96, 97] is made by replacig the origial LMS-PEF with a DCD-RLS-PEF. The advatages of this chage will be demostrated i the followig sectios Referece Voltage Feed-Forward Adaptive Cotroller Iitially, the origial referece voltage feed-forward structure preseted i [96] is simulated ad a compariso betwee the LMS with differet step size µ values ad the proposed adaptive DCD-RLS algorithm is made. The results are show i is Fig µ = µ = 3.3 DCD-RLS 3.2 µ = LMS, µ = 0. LMS, µ = 0.5 LMS, µ = DCD-RLS Times Fig. 5.0 Referece voltage feed-forward: Compariso of trasiet respose betwee LMS ad DCD-RLS. Repetitive load chage betwee 0.66 A ad.32 A every 5 ms

149 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 26 Both methods are able to maitai voltage regulatio ad recover from abrupt system chages. However, it is clear from Fig. 5.0 that the dyamic characteristics usig the proposed DCD-RLS are better tha the covetioal LMS. There is smaller overshoot ad a distictly faster recovery time after a parametric chage or whe there is a icrease i excitatio. From this, we ca deduce that the DCD-RLS method yields a overall improvemet i the trasiet respose of the system. Clearly, the trackig ability for the abrupt parameters chages is better i DCD-RLS tha LMS. As metioed earlier, i the LMS algorithm the step-size may give rise to problems; oe has to compromise betwee fast covergece rate ad estimatio accuracy. It is also compulsory to esure that µ is withi a rage that guaratees the filter tap-weights will approach their optimal value. The adaptive gai tap weight of the LMS predictor filter, the covergece time, the tap-weight gradiet oise, ad the stability of the adaptatio, all deped heavily o µ. Large values of µ decrease covergece time ad improve the dyamic respose as show i Fig. 5.0 but icrease the filter gradiet oise ad vice versa for low values of µ [80, 96]. For this specific example we foud that the optimal step size value is whe µ =. Fig. 5. shows the adaptatio performace of the LMS ad DCD-RLS algorithms. I both methods, the tap weights approach approximately the same values. However, the DCD-RLS is superior i terms of covergece time. As a result, the choice of step size is importat for dealig with uexpected system disturbaces. For example, i SMPC applicatios, oe might observe a high cotrol error sigal, due to a high iitial trasiet or a abrupt chage i load curret; if the step size is large, istability may arise. This is because the update of the filter coefficiet is directly proportioal to the iput sigal as give i equatio Therefore a prior kowledge of the variatio of the iput sigal is essetial to select a appropriate step size, thus esure stability ad parameter covergece.

150 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor µ = µ = 0.5 DCD-RLS Times x 0-3 a LMS, µ = 0.5 LMS, µ = DCD-RLS.2 µ = µ = DCD-RLS 0.4 LMS, µ = LMS, µ = DCD-RLS Times x 0-3 b Fig. 5. Zoomed adaptatio of gai K d ad tap-weight w i the two stage adaptive liear predictor for differet step-size values

151 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor Voltage Cotrol Usig Adaptive PD+I Cotroller I this sectio, the adaptive PD+I cotroller iitially discussed i sectio 5.2 is implemeted. Fig. 5.2 shows the performace of placig the itegral compesator Fig. 5. i the feedback loop. This icreases the excitatio of the adaptive filter ad drive the steady-state error to zero, hece improvig the idetificatio accuracy of the adaptive filter. To ivestigate the robustess of the algorithm to system disturbaces, a load chage is itroduced ito the system. This load chage forces the load curret to switch betwee 0.66 A ad.32 A every 5 ms Fig Usually the performace of adaptive methods ad self-tuig cotrollers is measured usig particular metrics. A cost fuctio is oe metric that ca be used to describe the performace of a PEF. The beefit of usig a PEF is that a cost fuctio aturally exists. The optimum cost fuctio for a PEF is actually the miimisatio of the predictio error sigal power required to reduce the loop error to zero Fig. 5.3a. It is clear from Fig. 5.3b that the algorithm is capable of miimisig the predictio error power; thereby, a well regulated output voltage is esured. However, the mai role of the PEF is to cotiuously work alogside the adaptive algorithm to miimise the predictio error. This i tur improves the predictio ad idetificatio of the iput filter. The covetioal LMS method ca be applied with the adaptive PD+I structure to provide ehaced performace over the previous referece voltage feed forward method Fig With the itroductio of the itegrator ito the cotrol loop, the loop excitatio is icreased, ad this helps the idetificatio process. However, as metioed earlier, careful attetio must be give to the selectio of the step size µ. Fig. 5.4 also shows the equivalet performace of the PD+I structure usig the DCD-RLS techique. Oce agai, it is clear that the DCD-RLS approach provides superior performace tha LMS method.

152 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor Times a Times b Times c Fig. 5.2 Trasiet respose of the proposed adaptive cotroller, a: output voltage, b: iductor curret, c: load curret chage betwee 0.66A ad.32 A every 5 ms

153 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor x Times a x Times b Fig. 5.3 Error sigal behaviour durig adaptatio process, a: loop error e L, b: predictio error e p. Load curret chage betwee 0.66 A ad.32 A every 5 ms

154 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor LMS,µ = 0.5 LMS,µ = DCD-RLS Adaptive PD+I, LMS, µ =0.5 Adaptive PD+I, LMS, µ = Adaptive PD+I, DCD-RLS Times Fig. 5.4 Trasiet respose of the proposed adaptive PD+I cotroller usig DCD- RLS or LMS. Load curret chage betwee 0.66 A ad.32 A every 5 ms Furthermore, the versatility of the proposed PD+I adaptive cotroller has bee tested with other coverter circuit parameters to represet alterative dc-dc coverter desigs. It has bee evaluated by chagig the output capacitace with lower ad higher values from the origial desig. To study the dyamic behaviour of the system durig these chages, a periodic load chage is itroduced, Fig. 5.5a, b. The same procedure the followed with respect to chagig the output iductor to a lower value. Fig. 5.5c shows the dyamic performace durig this chage. I each case,

155 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 32 the proposed adaptive cotroller presets very promisig results ad ca hadle a wide rage of ucertaity i the SMPC parameters. Fially, the adaptive PD+I cotroller is compared with a covetioal PID cotroller optimally desig usig the pole-zero cacellatio techiques previously preseted i sectio The adaptive PD+I scheme yields sigificatly improved trasiet performace for the same dyamic load chage. It demostrates sigificatly less oscillatory behaviour ad faster recovery time.

156 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor Times a Times b Times c Fig. 5.5 Trasiet respose of the proposed adaptive cotroller durig load curret chage betwee 0.66 A ad.32 A every 5 ms, a: output capacitace C = 50 μf ad L = 220 μh, b: C = 660 μf ad L = 220 μh, c: output iductor L = 00 μh ad C = 330 μf

157 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor PID DCD-RLS Times Fig. 5.6 Compariso of trasiet respose results betwee the proposed adaptive PD+I usig DCD-RLS ad pole-zero PID cotrol. Repetitive load curret chage betwee 0.66 A ad.32 A every 5 ms 5.6 Robustess ad Stability Aalysis for the Proposed Adaptive PD+I Cotroller SMPC cotroller behaviour ad stability is ofte expressed i terms of frequecy respose criteria. The frequecy respose of the proposed adaptive cotroller is displayed i Fig Here, it is show that the phase margi of the compesatio system is icreased through the itroductio of the PD compesator i the loop. The phase margi of the adaptive PD+I compesator is 43 o, ad the gai margi is 7.8 db.

158 Phase deg Magitude db Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor Compesate Ucompesate PD+I Fig. 5.7 Frequecy respose of the PD + I compesator ad the compesated / ucompesated ope loop gais As show i Fig. 5.8, three types of disturbace should be cosidered i closed loop digitally cotrol dc-dc SMPCs [59]; measuremet oise, v i, cotrol oise v u, ad load disturbace v l. To assess the idividual impact of each of these disturbaces, ad measure oise rejectio capability, sesitivity aalysis ca be used. This aalysis ca also be used to measure system dyamics ad determie the effects of parameter chages i the system. By cosiderig Fig. 5.8 ad usig sesitivity aalysis the overall effect of the disturbaces o the SMPC ca be expressed i terms of a series of sesitivity fuctios [59, 72]: y Frequecy Hz GVref S y vl S yivi S yuvu 5.25 l

159 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 36 where: GcG G dv G G S yl S S yi yu c dv G G Lo Lo GcGdv GLo GcG G G c G G dv c dv G dv dv G G Lo G G dv Lo Lo Here, G ad G Lo are the closed ad ope loop trasfer fuctio respectively. S yl, S yi, ad S yu are the output, iput, ad cotrol sesitivity fuctios respectively. V ref + e v u v l v o G c G y dv v i Fig. 5.8 Closed loop scheme of voltage mode cotrol for SMPC I Fig. 5.8, S yl describes the system performace from a disturbace rejectio poit of view, S yi highlights the effect of iput oise upo the SMPC model, ad S yu sigifies of cotrol disturbace rejectio of the plat [72]. Fig. 5.9 depicts the correspodig sesitivity fuctio of the proposed adaptive cotroller. It ca be observed that the maximum value of S yl is about 2.8 db. From this, the modulus margi ca be determied.

160 Magitude db Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor Frequecy Hz Fig. 5.9 Sesitivity fuctios of the PD+I cotroller Modulus margi is defied as the radius of the circle cetred at, j0 o the Nyquist plae required to touch the closest taget to the plot of the ope loop trasfer fuctio G Lo. This is demostrated i Fig The coectio of the critical poit to the Nyquist plot of G Lo is give by [59, 72]: mi M jw GLo e jw mi S yl e jw max S yl e 5.30 Im /ΔG ΔM ΔФ Re Fig Margis o Nyquist plot From equatio 5.30 it ca be cocluded that the modulus margi is iversely proportioal to the maximum magitude value of the S yl fuctio. Accordig to [59, 72], ΔM should be kept higher tha 0.5 to esure system robustess, which implies

161 Chapter 5: Adaptive Cotrol of A DC-DC SMPC Usig A Recursive FIR Predictor 38 that the maximum value of S yl should actually be less tha 2. Therefore, the lower the maximum value of S yl the better the output disturbace rejectio will be. From Fig. 5.9, it is foud that ΔM is approximately equal to 0.72 i this particular system. ΔM is sometimes cosidered to be a alterative measure of system stability with or istead of gai/phase margi [28]. 5.7 Chapter Summary This chapter preseted the viability of icorporatio the adaptive PEF as a mai cotroller i the feedback loop. It has demostrated the mathematical relatioship betwee the AR process ad PEF filter. I additio, it described the relatio betwee the PEF ad a PD cotroller, ad it is suitability for use i a adaptive cotrol desig. I cosequece, this chapter has demostrated the feasibility of a ew adaptive PD+I cotroller based PEF for the output voltage regulatio of a dc-dc coverter. The adaptive cotrol system uses a two-stage/oe-tap FIR filter ad itegral cotroller. A computatioally efficiet DCD-RLS algorithm has bee used to implemet the adaptatios mechaism ad to overcome may of the limitatios of covetioal RLS methods, makig it well suited for real time power electroic applicatios. Furthermore, this chapter provided details o LMS adaptive algorithm. The performace of the proposed adaptive PD+I cotroller usig DCD-RLS was compared with the LMS method. It showed that the adaptive PD+I cotroller relied upo DCD-RLS provided superior performace tha the LMS oe. The proposed cotroller has the ability to work cotiuously i the feedback loop ad rapidly miimise the cotroller error sigal by fidig real-time tap weights for the FIR filter. The itegral cotroller amplified the oscillatio i the feedback loop for a very short period of time to icrease the excitatio for predictio ad idetificatio purposes. The adaptive filter parameters quickly coverge ad elimiate this oscillatio. I this way, the approach is suitable for two importat purposes: predictio/idetificatio ad cotroller adaptatio. Fially, the robustess/stability aalysis of the proposed predictive cotroller has also explaied i this chapter.

162 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 39 Chapter 6 MICROPROCESSOR APPLICATION BASED SYNCHRONOUS DC-DC SWITCH MODE POWER CONVERTER- EXPERIMENTAL RESULTS 6. Itroductio With the advet of icreasigly powerful, ad cost effective, microprocessor platforms, advaced sigal processig algorithms ad itelliget adaptive cotrollers ca ow readily be implemeted o microprocessor based systems to sigificatly improve the overall dyamic performace of the process. To fully validate the proposed schemes developed i this thesis, a microprocessor based experimetal sychroous dc-dc buck coverter has bee desiged ad tested for 5 W operatio. This chapter describes the laboratory prototype hardware i detail ad presets research results validatig the ovel system idetificatio method usig the leadig DCD-RLS algorithm preseted i Chapter 4 ad the digital adaptive cotrol structure described i Chapter 5. Texas Istrumets TMS320F28335 ezdsp DSP platform has bee used i the experimetal validatio. 6.2 Microprocessor Cotrol Platform A digital sigal processor DSP is a dedicated type of microprocessor that is programmed by the user for optimal system operatio. The DSP architecture is optimally desiged for fast ad effective operatio of digital sigal processig algorithms. The TMS320F28335-DSP platform Fig. 6. is used i this research for parameter estimatio ad for digitally cotrol of the dc-dc SMPC coverter. The TMS320F28335 microprocessor is a member of the Delfio C2000 DSP platform

163 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 40 from Texas Istrumets TI [28]. This chip is a floatig poit processor which is optimised for digital cotrol applicatios. It eables high performace computatioally advaced algorithms to be implemeted usig simple system programmig. Accordig to [29] from TI, the TMS320F28335 core offers a 50 % performace ehacemet over similar fixed poit platforms. Fig. 6. TMS320F28335 ezdsp Architecture [29] The TMS320F28335 based o Harvard architecture desig Fig. 6. is similar to the other geeral purpose microprocessors [28]. This platform icludes 52 KB flash memory, 68 KB RAM, ad 6 chaels direct access memory DMA. As show i Fig. 6., the processor core cosists of three mai parts: Arithmetic Logic Uit ALU, bit multiplier, ad 2 32-bit Floatig Poit Uits FPU. I additio, the TMS320F28335 processor is fully mixed sigal core that cosists of [28]: 2-bit / 6 chael ADC core with coversio time 80 s at speed up to 2.5 Mega Samples per Secod MSPS. Two built-i aalogue multiplexers are itegrated with the ADCs to eable coectio of 8 chaels per multiplexer with dual built-i sampled ad hold circuits S/H. The read operatio from the ADC chael ca performs simultaeous or sequetial coversio from

164 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 4 each multiplexer. The coverted values are stored ito its dedicated 6-bit results registers. The coversio operatio ca be started by a trigger sigal geerated by a evet mager or by a exteral trigger sigal through the geeral purpose iput/output GPIO. Two evets EVA, EVB are used to trigger the ADCs, these evets ca work idepedetly. The TMS320F28335-DSP has dual 6 chael/6-bit ehaced PWM. Each chael ca be idepedetly programmed to geerate symmetric ad asymmetric PWM. Each evet maager module has a 6-bit geeral purpose timer. The PWM compare registers are used to compare the associated cotrol sigal with the timer registers. The timers ca be programmig as up/dow couters to emulate the PWM operatio. The TMS320F28335 processor also has 6 chaels/32-bit ehaced capture iput ecap that ca be cofigured to geerate 6 PWM chaels. Several commuicatio iterface circuits are also itegrated ito the TMS320F28335 icludig: Ehaced Cotroller Area Network ecan, Serial Peripheral Iterface SPI, ad Serial Commuicatios Iterface SCI Microprocessor Code Developmet I order to implemet ad evaluate the proposed system idetificatio ad adaptive cotrol algorithms usig the TMS320F28335 ezdsp; Texas Istrumets Code Composer Studio CCS based Itegrated Developmet Eviromet IDE is employed o the host PC to write C laguage programmig code ad to compile the developed code for dowload oto the target DSP. I additio, Simulik Embedded Target Support Package TSP ad Real-Time Workshop RTW toolboxes are available for rapid prototypig of the developed adaptive algorithms, automatic C- code geeratio from Simulik models ad for settig the iput/output device peripherals e.g. PWM as specified by the hardware blocks i the real-time model. This provides a simple, fast, ad alterative way to implemet ad rapidly validate the proposed algorithms i real time usig MATLAB/Simulik [30]. After compilig the code, the CCS builds the process ad dowloads the executable files

165 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 42 oto the DSP core for real time operatio. The CCS provides a flexible iterface to test, edit, ad read the geerated code. 6.3 System Hardware Descriptio ad Microprocessor Setup The test platform of the digitally cotrolled buck dc-dc coverter cosists of four mai parts: sigle-phase sychroous dc-dc buck coverter with dyamic load chage circuit, gate drive circuits, sigal coditioig/measuremet circuits, ad the microprocessor core TMS320F28335 ezdsp. Fig. 6.2 shows the whole system setup used i this project ad Fig. 6.3 presets the correspodig block diagram of this setup see appedix B for the circuit schematic. Fig. 6.2 Hardware platform setup

166 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 43 V i RL L Q Q2 STS8DNH3LL Rs C R C Curret-Sesor /Measuremet INABP ilt Sigal Coditioig Diodes Protectio vot Sigal Coditioig Voltage-Sesor / Measuremet Diodes Protectio R R3 R2 R4 HCPL- 380 Load Dyamic Chages IRF 703 HCPL- 380 HCPL- 380 HCPL- 380 Fast Optocoupler Host PC OPA376 SN74L VC2G 7 SN74L VC2G 7 Dual Buffer PWM PWM TMS320F28335 DSP ADC USB Fig. 6.3 Block diagram of the sychroous dc-dc buck coverter based o microprocessor

167 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 44 The sychroous dc-dc buck coverter icludes: two N-chaels MOSFETs circuit STS8DNH3LL as a switched device, DC-iput voltage source with decouplig capacitors, power stage filter L ad C ad output load resistor. I additio, a dyamic load chage circuit is desiged to test the adaptive cotroller performace durig load chages. As illustrated i Fig. 6.3, two parallel load braches are coected with the output of the buck coverter. Each brach icludes two series resistors of 5 Ω. I the ormal operatio, the equivalet load resistace is equal to 5 Ω 0 Ω // 0 Ω. Therefore, at 3.3 V regulated output voltage the load curret is equal to I out = 0.66 A. I order to chage the load dyamic, a switchig circuit Power MOSFET IRF703PbF is icluded Fig By closig the switches i each load lie, the load resistace see by the power coverter ca be reduced, thus icreasig the overall load curret. I case oe, both switches are closed ad the total load resistace is reduced to 2.5 Ω 5 Ω // 5 Ω, I out =.32 A. I case two, oe of the switched is closed whilst the other is ope ad the load is cut to 3.3 Ω 5 Ω // 0 Ω, I out = A. The parameters of the prototype sychroous buck coverter are show i Table 6.. Fig. 6.4a, b depicts the prototyped sychroous dc-dc buck coverter circuit ad the selected digital sigal processor platform respectively. Table 6. Prototyped sychroous buck coverter parameters Symbols Parameters descriptio Values V i Iput voltage 0 V V o Output voltage 3.3 V I omax Maximum output curret.32 A L Iductor 220 µh C Capacitor 330 µf R L Iductor ESR Ω R C Capacitor ESR 25 mω R o Load resistors 5 Ω, 5 W R s BCS 8, T T Electroics 8w, 50 mω

168 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 45 a b Fig. 6.4 a: TMS320F28335 DSP platform, b: the sychroous dc-dc buck coverter circuit

169 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 46 As preseted i Fig. 6.3, two sigal coditioig ad measuremet circuits are desiged to measure the regulated output voltage ad iductor curret. The output voltage geerated from the dc-dc power processor is iitially scaled dow via resistive voltage divider circuit with gai factor equal to 0.5 to accommodate the full dyamic scale of the ADCs which is 3 V. To be cofidet that the measured voltage does ot exceed the ADC full scale, a protectio Schottky-Diodes BAT 85 is icluded i the measuremet circuit. I additio, a buffer protectio circuit usig a uity gai fast operatioal amplifier OPA376 is iserted ito the measuremet circuit before the ADC chip. A similar sigal coditioig ad protectio circuit is used for the iductor curret measuremet. I order to measure the curret sigal, a series shut resistor is used Fig. 6.3 with a high speed istrumet amplifier INBP. Compare to usig a hall effect trasducer, this approach reduces the cost ad space of the prited circuit board. Withi the microprocessor itself the built-i ADCs sample the iput sigals ad the sampled data is the processed by the software cotrol algorithm. After the cotrol algorithm is executed the duty-cycle sigals are updated ad a ew PWMs sigals will be geerated. The geerated PWM sigals are the passed through a dual buffer circuit SN74LVC2G7 to protect the PWM chaels Fig This buffer circuits are carefully selected to produce a match output levels to the DSP-PWM output voltage. From this, the buffered PWM sigals get passed to isolated gate drives HCPL-380. Aother two PWM chaels are cofigured to activate the dyamic load circuit. Here, the load is cofigured to repetitively chage every 25 ms. Fig. 6.5a shows the experimetal ope loop results of the buck dc-dc coverter circuit. The waveforms show the steady-state output voltage V o ad the correspodig PWM sigals for both N-chaels MOSFETs. I this istat the complemetary PWM sigals have the same duty cycle 50 % duty ratio. Similar results are preseted i Fig. 6.5b with a differet voltage regulatio level 33 % duty ratio.

170 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 47 V o PWM-/ A PWM-/ B a V o PWM-/ A PWM-/ B b Fig. 6.5 PWM waveforms i ope loop circuit test, a: duty ratio 50 %, b: duty ratio 33 %

171 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results System Idetificatio Usig DCD-RLS / Experimetal Validatio This sectio demostrates the practical validatio of the proposed system idetificatio algorithm preseted i Chapter 4. The adaptive leadig DCD-RLS algorithm system idetificatio scheme ad the adaptive PD+I architecture are programmed based o the flowchart show i Fig Iitialisatio i =arg max p=,.., N { r p } Yes r i μ / 2R i,i No μ = μ / 2, m = m + Δŵ i =Δŵ i + sigr i μ No m > M Yes r = r sigr i μ R i Stop k = k + Yes k =N u No Stop Fig. 6.6 Leadig DCD-RLS algorithm flowchart The desiged sychroous dc-dc buck coverter has bee used to geerate real time practical data for direct iput ito the DCD-RLS algorithm. For easy compariso with the origial simulatio results, similar parameters ad compoet values to those outlied i sectio 4. are chose as show i Table 6.. The TMS320F28335 platform is used to implemet the digital PID cotroller, to iject the digital PRBS

172 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 49 ad the to collect the iput/output measuremet data. A 9-bit PRBS is geerated ad implemeted i the DSP first show i Fig The PRBS amplitude, PRBS = ± 0.008, ad the total date legth is 5. Therefore, a complete PRBS sequece is L / f s = 25 ms. The PID gais used i the experimetal test are selected to match the simulatio settig i sectio 4., where, q o = 4.27, q = 7.84, ad q 2 = Durig the practical work, the same procedure as preseted i Fig. 4. is followed. Fig. 6.7 highlights the output voltage waveform of the experimetal buck coverter whe the PRBS disturbace is ijected to allow for system idetificatio. Iitially, the SMPC is workig uder ormal coditios system idetificatio disabled. The system idetificatio process is the eabled; the PRBS sigal is ijected ito the loop ad the system begis to estimate the ukow parameters of the buck coverter model. The disturbace i the output voltage, created by the PRBS, is clearly visible i Fig The voltage ripple is approximately ± 3% with respect to the omial dc output voltage. However, it ca also be see that this disturbace oly exists whe the idetificatio process is eabled. After 20 ms, the process is complete, ad the buck coverter reverts back to ormal operatio. The PRBS ijectio time is deliberately icreased i this example test to fully demostrate the covergece rate of the parameter estimatio. The actual legth of time of the excitatio ca be sigificatly reduced i the fial optimized solutio. v o PRBS ijectio ID Eable Fig. 6.7 Experimetal output voltage waveform whe idetificatio eabled. ac coupled

173 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 50 Now, the measuremet data from the dc-dc coverter is stored i the DSP memory, ad exported to MATLAB for post-processig after the full test sequece has bee applied to the power coverter. Practically, i order to focus the idetificatio o the frequecy rage of iterest ad remove uwated high frequecy measuremet oise; the iputs to the DCD-RLS algorithm require filterig prior to idetificatio. Here, a four tap movig average FIR filter is desiged to smooth the iput ad output data. I additio, offset i the iput sigals must be removed as the RLS algorithm assumes zero mea iput values. I dc-dc SMPC applicatios it is easier to remove offsets o a cycle-by-cycle basis from the iput sigals, where steady-state average values of the regulated output voltage ad the average duty-cycle ratio are kow. At each time istace, the average value of the iput sigal is directly subtracted from the excited sigal. A high-pass filter ca also be used to remove the offset from the iput sigals; however, this will add more computatio to the overall system that is ot essetial i the o-lie system idetificatio process. Fig. 6.8 shows the sampled output voltage ad duty cycle data from the dc-dc coverter durig the idetificatio process. From the measured data, the DCD-RLS performs the cycle-by-cycle parameter estimatio algorithm previously described to idetify the tap-weights of the IIR filter ad miimise the predictio error sigal. The experimetal parameters of the DCD-RLS algorithm are chose to match the iitial buck coverter simulatio settigs ad allow for easy compariso of results.

174 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results a, Time samples b, Time samples Fig. 6.8 Experimetal output voltage ad persistece excitatio sigal duty sigal + PRBS results durig ID, based o sampled data collected from DSP The results from experimetal measuremet are show i Fig Importatly, there is excellet agreemet with the origial simulatio results i Fig The practical based results show both the classical RLS method ad the DCD-RLS algorithm coverge quickly < 0 ms to virtually the same parameter estimatio values. Furthermore, it is apparet from Fig. 6.0 that the voltage predictio error sigals for both algorithms RLS ad DCD-RLS coverge quickly to zero. I this way, both techiques successfully idetify the discrete model of the SMPC from real time experimetal data. However, as show i earlier aalysis, the computatioal effort of the DCD-RLS is substatially lower. It is worth otig that i both methods the covergece time of the pole coefficiets a, a 2 is faster ad more accurate tha the zero coefficiets b, b 2. This is re-assurig sice i may cotrol systems, icludig SMPCs, accurate kowledge of the pole locatios is importat for stability aalysis ad cotroller desig. Fig. 6.a, b presets the actual estimatio error of the classical RLS ad DCD-RLS respectively. This result clearly shows that both algorithms reach approximately zero estimatio error with a rapid covergece rate. I summary, the performace of the DCD-RLS is comparable to the covetioal RLS method.

175 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results a 2 Parameters b Parameters 0 b 2 Parameters DCD Parameters... RLS Parameters Model Parameters a Parameters Time samples Fig. 6.9 Experimetal tap-weights estimatio for IIR filter with DCD-RLS ad classical RLS methods; compared with the calculated model 0.02 RLS a, Time samples DCD-RLS b, Time samples Fig. 6.0 Experimetal predictio error results, a: covetioal RLS, b: DCD-RLS

176 Estimatio Error Estimatio Error Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results Time Samples a Time Samples Fig. 6. Experimetal parameters estimatio error, a: classical RLS, b: DCD-RLS b

177 MSE Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 54 It has already bee oted that the estimatio performace of the DCD-RLS algorithm ca be improved by icreasig the umber of iteratios-albeit, at the cost of icreased computatioal complexity. Fig. 6.2 compares the mea square error MSE performace of the DCD-RLS algorithm with differet iteratio values N u ; agaist the covetioal RLS techique. It ca be see that the covetioal RLS covergece rate ad MSE magitude are lower tha the DCD-RLS, however the covergece rate of DCD-RLS is improved whe the umber of iteratios is icreased N u. As i may applicatios, a compromise must be made betwee performace ad complexity. I this particular case, N u =.0 is sufficiet for fast SMPC parameters estimatio with acceptable estimatio error. 8 x RLS Time samples Fig. 6.2 Experimetal learig curves compariso results of covetioal RLS agaist DCD-RLS at differet iteratio values

178 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results Realisatio of the Coverter Model I order to cofirm the suitability of usig a secod order model for the dc-dc coverter, experimetal iput ad output sample data is collected from the buck coverter. The mea value is the removed from the iput ad output data as show i Fig. 6.3a, b. Followig this, the iput ad output data is divided ito two parts. The first part is used to costruct the system model ad cosists of 750 samples 37 ms ad the secod part is used to validate the resulted model, a further 750 samples. The real output data of the secod part is compared with the estimated output data ad whe the differeces betwee the measured data ad the costructed model are small, the model ca be cosidered as a good fit to the collected data a, Time s 0.0 Model Data Validatio Data b, Time s Fig. 6.3 Experimetal sampled data collected from DSP, a: output voltage, b: cotrol sigal duty sigal + PRBS Now, two types of the model structure are tested usig this evaluatio: secod ad third order equatio error model, 2 secod ad third order output error model. As show i Fig. 6.4, equatio error model provides a better fit tha the output error model. Furthermore, icreasig the order of the model does ot provide ay

179 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 56 sigificat differece i the system data fits: both models provide 98.77% fit with the output data Fig This result cofirms that a secod order equatio error model is a good choice of cadidate model to estimate the system parameters of dc-dc buck coverter Equatio error Output error Time s Fig. 6.4 Model errors compariso betwee third/secod order output error ad equatio error model

180 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results Adaptive Cotroller / Experimetal Validatio This sectio presets the practical validatio of the proposed adaptive PD+I cotrol system. Iitially, a covetioal PID voltage cotroller is implemeted o the experimetal hardware. The PID is set to cotrol the buck coverter output voltage at 3.3 V. This serves as a bechmark for testig the adaptive PD+I cotroller based o the DCD-RLS method. The PID gais are optimally tued usig the well-recogised pole-zero matchig techique previously preseted i Sectio The trasiet characteristics of the PID cotroller are determied by applyig a repetitive step chage i load to the buck coverter. This step chage causes the load curret to switch betwee 0.66 ad.32 A at 25 ms itervals. The results show i Fig. 6.5 demostrate that the buck coverter is always operatig i cotiuous curret-mode CCM. The output voltage trasiet shows sigificat oscillatory behaviour at the poits of load chage. Followig this, the DCD-RLS adaptive algorithm is implemeted o the DSP for real time operatio Fig For cosistecy, all circuit parameters remai the same ad the buck coverter is subjected to the same load chage as previously described. The experimetal results show i Fig. 6.6 are i excellet agreemet with the simulatio results i Fig. 5.2, thus cofirmig the successful real time implemetatio of the proposed DCD-RLS cotrol scheme. Compared to the experimetal results achieved with the covetioal PID cotroller, the DCD-RLS scheme yields sigificatly improved trasiet performace for the same dyamic load chage. The DCD-RLS method demostrates lower trasiet overshoot, sigificatly less oscillatory behaviour ad faster recovery time. Fially, the LMS adaptive cotroller is implemeted o the DSP. Here, each DCD- RLS i Fig. 5. is replaced with a adaptive LMS filter. As previously described, with the LMS-PEF, there is a eed to carefully select a appropriate step size µ. A rage of step sizes have bee experimetally tested ad i agreemet with the simulatios, a optimal values of µ =.0 is selected. Agai, the same set of system parameters is used ad the experimetal results are show i Fig These results are a good match to the iitial simulatio waveforms show i Fig Compared to the covetioal PID cotroller, the adaptive LMS cotroller offers improved

181 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 58 trasiet performace. However, as predicted by the simulatio results ad cofirmed experimetally, the DCD-RLS offers superior dyamic performace over the LMS. I practical systems, the adaptive filter tap-weights ca remai at the same value for a log time without chagig. This situatio is sometimes referred to as stallig. This ca be caused by isufficiet excitatio i the sigal to cause ay chage i the estimated filter coefficiets. I LMS adaptive filters a high value of step size ca be oe solutio to avoid stallig. Alteratively, a small radom oise sigal ca be added to the filter tap-weights, this may be prevet the stallig effects [80]. It is worth otig that the switchig frequecy effect seeig o the experimetal waveforms is due to the commo mode oise o the oscilloscope probe.

182 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 59 v o i L Load Eable a v o i L Recovery Time Load Eable b Fig. 6.5 Trasiet respose of PID cotroller with abrupt load chage betwee 0.66 A ad.32 A. a 4 ms/div: showig two trasiet chages. b 400 µs/div: zoom-i o secod trasiet

183 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 60 v o i L Load Eable a v o i L Recovery Time Load Eable b Fig. 6.6 Trasiet respose of adaptive PD+I DCD-RLS cotroller with abrupt load chage betwee 0.66 A ad.32 A. a 4 ms/div: showig two trasiet chages. b 400 µs/div: zoom-i o secod trasiet

184 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 6 v o i L Load Eable a v o i L Recovery Time Load Eable b Fig. 6.7 Trasiet respose of adaptive PD+I LMS cotroller with abrupt load chage betwee 0.66 A ad.32 A. a 4 ms/div: showig two trasiet chages. b 400 µs/div: zoom-i o secod trasiet

185 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results Complexity Reductio I most applicatios, there is a trade-off betwee the dyamic performace ad computatioal complexity i.e., speed of executio of the cotroller. I adaptive PD+I cotroller two solutios are preseted, each givig a differet weightig to these two importat performace idicators. The LMS is desiged for good dyamic performace with low computatioal complexity, while the DCD-RLS is desiged for optimum dyamic performace. The DCD-RLS is a computatioal-efficiet algorithm compared to the classic RLS schemes, but it is ackowledged that a higher computatioal burde tha the LMS exists. For this reaso, the overall system complexity of the proposed DCD-RLS scheme Fig. 5. ca be reduced by exchagig the secod stage DCD-RLS for a classical LMS-PEF. The first stage DCD-RLS still remais i place. I this way, we develop a hybrid DCD-RLS: LMS cotrol scheme. This chage does ot appear to sigificatly compromise the behaviour of the system respose with respect to covergece time, idetificatio accuracy, ad cotrol error sigal power, eve durig the iitial trasiet or due to a sigificat chage i the system parameters. Whe the first stage is faced with a high error sigal, the DCD-FIR filter iflueces the predictio error sigal. This predictio error sigal is the passed oto the secod stage LMS-FIR filter to adapt the tap weights ad adaptive gai. The simulatio results from the DCD-RLS:LMS system are show i Fig. 6.8 load chage:.32a-to-6.5 A. The experimetal results are show i Fig. 6.9 load chage: A. Here, the same coditios have bee used as those origially specified i sectio 6.6. It ca be see that the dyamic performace of hybrid DCD-RLS: LMS achieves a excellet respose.

186 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results DCD-LMS DCD-DCD 4 DCD-LMS DCD-DCD Time s Fig. 6.8 Load trasiet respose at sigificat chage i load curret, with two stage DCD-DCD adaptive cotroller ad hybrid DCD-LMS adaptive cotroller

187 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results 64 v o i L Load Eable a v o i L Recovery Time Load Eable b Fig. 6.9 Trasiet respose of hybrid DCD-RLS:LMS µ = adaptive cotroller with abrupt load chage betwee 0.66 A ad.32 A. a 4 ms/div: showig two trasiet chages. b 400 µs/div: zoom-i o secod trasiet

188 Chapter 6: Microprocessor Applicatio Based Sychroous DC-DC SMPC-Experimetal Results Chapter Summary This chapter has focused o the experimetal validatio of the ovel leadig DCD-RLS system idetificatio algorithm preseted i Chapter 4 ad the proposed adaptive PD+I cotroller scheme illustrated i Chapter 5. The experimetal results of the system idetificatio scheme are i close agreemet to the simulatio results preseted i Chapter 4, demostratig the viability of the proposed algorithm for real time applicatio. Furthermore, the results demostrate that the parameter estimatio of the DCD-RLS is comparable to covetioal RLS method but with reduced computatioal complexity. This chapter has also successfully demostrated that the proposed algorithm ca be directly embedded ito adaptive ad self-tuig digital cotrol systems to improve cotroller performace. Experimetal results show that by applyig the DCD-RLS algorithm i the PD+I structure superior dyamic performace ad voltage regulatio ca be achieved compared to the covetioal PID cotroller.

189 Chapter 7: Coclusio ad Future Work 66 Chapter 7 CONCLUSION AND FUTURE WORK 7. Coclusio I SMPCs, parameter estimatio is essetial to acquire a appropriate model of the system ad is a first step i developig adaptive ad self-tuig cotrollers. To be successful, ay system idetificatio scheme must be able to respod to the characteristics of the system. However, to achieve high levels of accuracy ad/or estimatio speed typically implies the eed for sophisticated idetificatio methods which require sigificat sigal processig to implemet. Ufortuately, i applicatios, such as SMPCs, cost ad complexity are a major cocer. Covetioal RLS algorithms provide fast covergece speed, small predictio error, ad accurate parametric estimatio. However, they ofte have limited applicatio i SMPCs ad other low power, low cost applicatios due to computatioally heavy calculatios demadig sigificat hardware resources. Therefore, RLS schemes are ot always viable for real time estimatio, where it is ecessary to keep system costs low ad competitive. For this reaso, this thesis makes a research cotributio i the area of low complexity parameter estimatio algorithms for the system idetificatio ad adaptive cotrol of SMPCs. The work specifically presets a system idetificatio/ predictio error filter structure based o the DCD-RLS algorithm. Several ovel approaches have bee preseted i this thesis.

190 Chapter 7: Coclusio ad Future Work 67 DCD-RLS System Idetificatio of dc-dc Coverter: Here, a ovel o-lie system idetificatio method is proposed to overcome the limitatios of may classic RLS algorithms. The proposed algorithm ca be implemeted i may alterative applicatios where accurate ad efficiet parameter estimatio is required. I this research, specific attetio is give to the parameter estimatio of dc-dc SMPCs. The solutio based aroud the DCD-RLS algorithm is prove to be computatioally efficiet ad utilises a IIR adaptive filter as the idetificatio model. The IIR filter parameters are estimated o a cycle-by-cycle basis by superimposig a 9-bit PRBS ito the cotrol sigal ad moitorig the output sigal respose. Results demostrate the effectiveess of the proposed solutio. The idetificatio method is able to accurately estimate the model parameters ad quickly miimise the predictio error power. I additio, it is capable of workig cotiuously i the cotrol loop. Simulatio ad experimetal results, based upo a prototype sychroous dc-dc buck coverter cotrolled by Texas Istrumets TMS320F28335 DSP, show that the DCD-RLS algorithm provide a very good idetificatio metrics covergece rate, parameters estimatio, ad predictio error ad the system idetificatio performace is comparable to other complex solutios such as recursive least squares RLS techiques. Importatly, the DCD-RLS algorithm reduces the computatioal complexity of the classical RLS algorithms; thus offerig a efficiet hardware solutio which is well suited to real time applicatios. As a result, the proposed scheme ca be directly embedded ito adaptive ad selftuig digital cotrollers to improve the cotrol performace of a wide rage of idustrial ad commercial applicatios. A further research cotributio of this thesis is icorporatig a ew adaptive forgettig factor strategy to the DCD-RLS techique. This scheme is based o fuzzy logic ad uses a two iput, sigle output adaptive forgettig factor. The fuzzy logic approach is show to improve the model estimatio durig abrupt load chages withi the SMPC. The trackig approach relies o moitorig the predictio error sigal, where it is possible to detect fast chages i the system. The results ad coclusios of this work have successfully bee published i the followig joural ad iteratioal coferece papers:

191 Chapter 7: Coclusio ad Future Work 68 - M. Algreer, M. Armstrog, ad D. Giaouris, Active O-Lie System Idetificatio of Switch Mode DC-DC Power Coverter Based o Efficiet Recursive DCD-IIR Adaptive Filter, IEEE Trasactios o Power Electroics, vol.27, pp , Nov M. Algreer, M. Armstrog, ad D. Giaouris, "System Idetificatio of PWM DC-DC Coverters durig Abrupt Load Chages," i Proc. IEEE Idustrial Electro. Cof., IECON'09, 2009, pp , Porto, Portugal. Adaptive cotrol based o DCD-RLS ad LMS PEF: The secod major cotributio of this thesis is the alterative applicatio of the DCD-RLS algorithm for the adaptive cotrol of SMPCs. I this case, the proposed adaptive cotroller uses a simple two-stage/oe-tap FIR adaptive PEF. This two-stage cotroller is show to be comparable to a covetioal PD cotroller. A o-adaptive itegral cotroller +I, is the itroduced ito the feedback loop to icrease the excitatio of the filter tap-weight ad esure good output voltage regulatio. I this way, the proposed cotroller applies a adaptive PD+I structure which offers a effective substitute to a covetioal PID cotroller. The DCD-RLS algorithm is employed i this scheme as a adaptive PEF. Agai, the mai purpose is to reduce the computatioal complexity of the system which might typically employ a covetioal RLS algorithm for this purpose. Simulatio ad experimetal results, based upo a prototype sychroous dc-dc buck coverter cotrolled by Texas Istrumets TMS320F28335 DSP, show that the adaptive PD+I cotroller, based o the DCD- RLS algorithm, is able to ehace the dyamic performace ad covergece rate of the adaptive gais withi the cotroller. As a result, the overall dyamic performace of the closed loop cotrol system is sigificatly improved. The proposed approach results i a fast adaptive cotroller with self-loop compesatio. I tur, the voltage error sigal i the cotrol loop is quickly miimised ad will lead to miimise the predictio error sigal. Results clearly show the superior dyamic performace compared to covetioal PID ad adaptive LMS cotrol schemes. Sesitivity aalysis shows the PD+I cotroller to be robust ad stable.

192 Chapter 7: Coclusio ad Future Work 69 Further reductio to the computatio complexity of the proposed adaptive cotroller is also preseted i this work. Here, a hybrid DCD-RLS:LMS cotrol structure is developed. The motivatio for this study is that whilst the DCD-RLS is a computatioally efficiet algorithm compared to classic RLS schemes, it must still be ackowledged that it presets a higher computatioal burde tha covetioal LMS algorithm. Therefore, the overall system complexity of the proposed DCD-RLS scheme ca be reduced by exchagig the secod stage DCD-RLS for a classical LMS-PEF. Experimetal results show that this modificatio does ot appear to sigificatly compromise the behaviour of the system respose. The results ad coclusios of this work have successfully bee published i the followig joural ad iteratioal coferece papers: - M. Algreer, M. Armstrog, ad D. Giaouris, Adaptive PD+I Cotrol of a Switch Mode DC-DC Power Coverter Usig a Recursive FIR Predictor, IEEE Trasactios o Idustry Applicatios, vol.47, pp ,oct M. Algreer, M. Armstrog, ad D. Giaouris, Predictive PID Cotroller for DC-DC Coverters Usig a Adaptive Predictio Error Filter, i Proc. IET Iteratioal Cof. o Power Electro., Machies ad Drives, PEMD 202, vol. 202, Bristol, Uited Kigdom. 3- M. Algreer, M. Armstrog, ad D. Giaouris, Adaptive Cotrol of a Switch Mode DC-DC Power Coverter Usig a Recursive FIR Predictor, i Proc. IET Iteratioal Cof. o Power Electro., Machies ad Drives, PEMD 200, vol. 200, Brighto, Uited Kigdom. 7.2 Future Work This thesis has cocetrated o system idetificatio ad adaptive cotrol for a buck dc-dc SMPC. Therefore, applicatio to other power coverter topologies should be cosidered to further validate the applicatio of the proposed techiques for power electroic applicatios. I particular, the performace of the PEF adaptive cotroller should be studied o multiphase SMPCs. Here, it is assumed that the order of the PEF will be icreased ad the impact of this is ukow at preset.

193 Chapter 7: Coclusio ad Future Work 70 Withi the area of adaptive PEFs, it is suggested that further research work be carried out ito ehacig the LMS algorithm to solve the problem of step-size selectio ad improve the dyamic performace. For example, a time variable stepsize could potetially be used to speed up the covergece rate of the idetificatio process ad ca be used to improve the overall respose of the adaptive cotrol system. It may be worth ivestigatig more optimal implemetatios of the adaptive cotroller based o DCD-RLS algorithm, potetially usig dual-core microprocessor techology. Such a implemetatio could use oe core to implemet the cotrol loop ad the secod core for system idetificatio ad cotrol loop adaptatio. Furthermore, the work o this project ca be exteded to focus o complete solutios for the purpose of system idetificatio ad adaptive cotrol with emphasis o hardware optimisatio for efficiecy ad low cost implemetatio. The proposed schemes are iitially implemeted through a DSP; however, more itegrated solutios are possible ad the algorithms are well suited for applicatio i advaced FPGA ad ASIC techologies. The proposed adaptive algorithm DCD-RLS opes several potetial topics that would make the o-lie parameter estimatio more useful for low cost ad low complexity applicatios. For example, oe ca ivestigate o-lie estimatio of the SMPCs parameters based o limit-cycle oscillatios LCOs. With this techique it is possible to cotiuously idetify the parameter of the model without ijectig ay excitatio sigal ito the loop. The LCO is used as a excitatio sigal ad this i tur could lead to a further reductio i the computatio complexity of the idetificatio process. I additio, more emphasis may be cosidered o iverse model adaptive filter techiques based o the DCD-RLS algorithm. This scheme ca be applied for two purposes: system idetificatio ad adaptive cotroller, which may reduce the computatio, overhead of the existig adaptive cotroller. Alteratively, there is iterestig research i the field of o-liear modellig of dc-dc coverters. These methods require complicated umerical aalysis ad extesive off-lie testig to develop a appropriate system model. Therefore, there is the potetial to explore the applicatio of o-liear adaptive filter algorithms for

194 Chapter 7: Coclusio ad Future Work 7 system modellig. This will offer a o-lie o-liear model of the system that may directly operate alogside the adaptive cotroller.

195 Appedix A: Derivatio of RLS Algorithm Based o Matrix Iversio Lemma 72 APPENDIX A DERIVATION OF RLS ALGORITHM BASED ON MATRIX INVERSION LEMMA As described i Chapter 4 that the ormal equatio of the least square solutio ca be writte as: k k k T k k y k k y k k ˆ u R u u u w A. where, u is the data vector, y is the output sigal of the system. I weightig least square algorithm, the auto-correlatio matrix R ad the crosscorrelatio vector β ca be give as [63]: k k T k k y k k k k,, u β u u R A.2 Let assume that the weightig fuctio defie as:, k. For simplicity we deotes to λ as λ [63]. Therefore, the solutio i equatio A. ca be reformulated i recursive form by assumig that ŵ- represets that previous time solutio - of least square problem A. [74]. Form this; the auto-correlatio matrix ca be defied as: T u u R R A.3

196 Appedix A: Derivatio of RLS Algorithm Based o Matrix Iversio Lemma 73 Now, equatio A. ca be rearraged as: ˆ y k k y k k y k k u u R u R w A.4 Oe ca write: ˆ k k y k w R u A.6 By usig equatios A.3-A.6 the estimated coefficiets ca be described as follows [63]: ˆ ˆ ˆ ˆ ˆ y y y T T w u u R w u w u u R R u w R R w A.7 Fially, the recursive solutio of the filter coefficiets ca be writte as: ˆ ˆ ˆ y T w u u R w w A.8 Matrix iversio lemma As give i equatio A.8, the estimatio of the parameters of the system require at each time istat to fid the matrix iverse of R. To overcome this issue a matrix iversio lemma ca be used [63]: DA B DA B C A A BCD A A.9 Let suppose: P = R -, A = λr -, B = D T = u, ad C =.

197 Appedix A: Derivatio of RLS Algorithm Based o Matrix Iversio Lemma 74 Thus: T T u P u P u u P P P A.0 Assumig that [80]: ˆ y e T T w u S u S k u P S A. By isertig equatio A. ito A.0 this will result i: T P u k P P A.2 Fially, by substitutig equatio A. ad A.2 ito A.8, this yields [80]: ˆ ˆ e k w w A.3

198 Appedix B: Schematic Circuit of the Sychroous Buck Coverter 75 APPENDIX B SCHEMATIC CIRCUIT OF THE SYNCHRONOUS BUCK CONVERTER J HDRX2 C26 0F G U C2 6 00F 5 4 STS8DNH3LL PW PW2 L 220µH R 5mΩ 330µF RG Vs VDD -2V 250Ω C4 U2 00F C7 00F INABP Curret Sesor C R5 5Ω R7 5Ω R6 5Ω R8 5Ω R3 330Ω % R4 330Ω % VSS 3V D2 N200C D3 N200C G U IRF_703 LE LE2 Load Dyamic Cotrol R3 330Ω % R4 330Ω % VSS 3V D7 N200C D N200C U OPA376 VEE 5V C0 00F J3 HDRX0 Fig. B. Schematic circuit of the buck coverter

199 ADJ Appedix B: Schematic Circuit of the Sychroous Buck Coverter 76 2V VCC U Isolated DC-DC U NMR U NMR U NMR GND LE2 C27 0µF C29 0µF PW2 LE PW G G2 C3 0µF C33 0µF R25 R29 0Ω R26 2Ω R30 0Ω C28 C25 00F 00F C30 00F C32 00F HCPL Opto DIP8 Opto DIP8 Opto DIP GND GND GND GND GND R6 00Ω R2 00Ω R23 00Ω R24 00Ω C2 00F VSS 3.3V U SN74LVC U SN74LVC VSS 3.3V C3 00F GND GND GND J2 GND HDRX0 G 2Ω Fig. B.2 Schematic circuit of the isolated gate drive circuit J4 HDRX4 C36 00F VDD 0µF -2V C35 Vs C6 00F C34 0µF 3 C22 00F IN U2 LM37 OUT 2 R0 560Ω 5% R 00Ω 5% R28 220Ω 5% C24 00F VEE 5V C23 µf Supply Voltage Voltage Regulator Fig. B.3 Schematic circuit of the aalogue side power supply with 5 V voltage regulator

200 ADJ Appedix B: Schematic Circuit of the Sychroous Buck Coverter 77 J5 HDRX2 GND VCC 2V C4 00F Supply Voltage GND C5 0µF VCC 2V 3 C7 00F IN U4 LM37 OUT 2 R5 330Ω 5% R22 8Ω 5% R27 220Ω 5% C2 00F VSS 3.3V C8 µf GND Voltage Regulator Fig. B.4 Schematic circuit of the digital side power supply with 3.3 V voltage regulator

201 Appedix C: Simulik Model of the Proposed Structures 78 APPENDIX C SIMULINK MODEL OF THE PROPOSED STRUCTURES Fig. C. Simulik model of the proposed system idetificatio structure