AN ESTIMATION OF MULTILEVEL INVERTER FED INDUCTION MOTOR DRIVE

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1 9 IJRIC. All rights reserved. IJRIC E-ISSN: AN ESTIMATION OF MULTILEVEL INVERTER FED INDUCTION MOTOR DRIVE K.RAMANI AND DR.A. KRISHNAN SMIEEE Seior Lecturer i the Departmet of EEE at K.S.Ragasamy College of Techology, Tiruchegode, INDIA Dea, K.S.Ragasamy College of Techology, Tiruchegode ad guide at Periyar Uiversity, Salem ad Aa Uiversity, Cheai, INDIA ABSTRACT This paper highlights a hybrid multilevel iverter for A.C electrical drives. I recet days multilevel iverters has become very popular for motor drive applicatios of idustry.multilevel pulse width modulatio iversio is a effective solutio for icreases the level umber of the output wave form ad thereby dramatically reduced to the harmoics ad total harmoic distortio. I covetioal methods, the eed of coverters to supply the cells of reversible multilevel coverters icreases the cost ad losses of such iverters. I this ew topology the output waveform cosists of SVdc; S-umber of stages ad the associated umber of level equal s+1 1. The output waveform has 15 levels. Moreover, the stage with higher DC lik voltage has lower switchig frequecy ad thereby reduces the switchig losses. Compariso of covetioal results will be preseted. Keywords: Estimatio, Hybrid Multilevel Iverter, Modulatio Iversio, Switchig, Compariso I. INTRODUCTION Multilevel iverters have very importat developmet for high power medium voltage AC drives. Quite a lot of topologies have foud idustrial approval; Neutral Poit Clamped, flyig capacitor, H-bridge, cascaded with separated DC source, several cotrol ad modulatio strategies have bee developed Pulse Width Modulatio (PWM), Siusoidal PWM, Space Vector PWM ad Selective harmoic elimiatios [1-3]etc. A most importat issue with multilevel iverter is elimiatig the harmoics from the output voltage. The output voltage of the iverter must meet maximum Total Harmoics Distortio (THD) boudaries as specified [4]. Every idividual iverter is capable of geeratig three differet voltage output +V dc,, -V dc by coectig the dc source to the ac output side by differet combiatios of the four switches S 1, S, S 3 ad S 4 [1]. The sythesize ac output voltage waveform of the sum of all the idividual iverter s outputs. The umber of output phase voltage level of cascade multilevel iverter is s+1 where S is the umber of dc sources. This outstadigly icreases the level umber of the output wave form ad thereby dramatically reduced to the low order harmoics ad total harmoic distortio. Oe of the foremost motives for developig the multilevel iverter is to reduce cost [5]. Fig. 1 Topology of hybrid multilevel iverter. 19

2 9 IJRIC. All rights reserved. IJRIC E-ISSN: II. HYBRID H-BRIDGE MULTILEVEL INVERTER The H-bridge multilevel iverter is i figure.1. The output waveform cosists of SVdc; S-umber of DC source or stages ad the associated umber of level equal s+1 1. The output has 15 levels for S=3., + 7, + 6, + 5, combiatios for Vout ± 3 V dc & ± 1V dc. Oe of the advatages is that the stage with the higher DC lik voltage has a lower umber of commutatios. Hereby reducig the switchig losses. + 4, + 3, +, + 1 ad.fig ad fig 3.ilustrate the relatioship of the switchig states ad output voltages for H-bridge multilevel iverter P ad N apply the output voltage of the stages with V DC = 1V, V ad 4V, with positive & egative polarities correspodigly. More over idicates that the associated stage is i a free wheelig state which meas that the termials of the output are both coected to the positive ad egative DC lik. There are two combiatios of switchig states for V out = ± V dc ad three. Fig. Topology of hybrid multilevel iverter for oe leg Fig. 3 output voltage waveform of iverter Output voltages ad switchig states for the hybrid iverter, S=3 Vdc Vout -7V -6V -5V -4V -3V -V -1V V 1V V 3V 4V 5V 6V 7V 1V N P N P N N N P P P N N P N P P N P V N N N N P N P N P P N P N P N P P P 4V N N N N N N N N N P P P P P P P P P Table.1 OUTPUT VOLTAGES AND SWITCHING STATES FOR THE HYBRID INVERTER

3 9 IJRIC. All rights reserved. IJRIC E-ISSN: Table.1 cosists of output voltage ad switchig state for hybrid multilevel iverter. For S=3; S is umber of stage or umber of Dc source. Hece the output has 15 levels ( + 7 ad ). Table. shows the performace the hybrid multilevel iverter. It cotais the expressio of umber of levels, maximum output voltage of hybrid ad the maximum value of the output voltage i.e. maximum voltage ratio (MVR). TABLE..HYBRID MULTILEVEL INVERTER PERFORMANCE RESULTS Multi level Iver ter Hybri d Level umb er s+ 1 1 (15) V k (m ax) V out (m ax) s 1 Vdc ( s 1) V dc MV R s 1 s 1 A factor kow as the maximum voltage ratio (MVR), it is defied as the ratio of maximum output voltage of H-bridge, Vk (max) to the maximum value of the output voltage, V out (max) defied by (1) is used as the performace idex. V MVR = V k (max) (max) out a) Harmoics (1) Harmoics are udesirable curret or voltage[6-9]. They exist at some multiple or fractio of the fudametal frequecy. The harmoics causes i three ways are a) The applicatio of a o siusoidal drivig voltage to a circuit cotaiig o liear impedace b) The applicatio of a siusoidal drivig voltage to a circuit cotaiig o liear impedace. c) The applicatio of a o siusoidal drivig voltage to a circuit cotaiig liear impedace. The harmoics orders ad magitude deped o the iverter type ad the cotrollig methods for example i sigle phase VSI, the output voltage waveform typically cosists oly of odd harmoics. The eve harmoics are abset due to the half wave symmetry of the output voltage harmoics. For three phase VSI, i additio to the eve harmoic triple (third ad multiple of third harmoics) are also abset. The harmoic spectra deped o the switchig frequecy ad the cotrol method. b) PWM for harmoic reductio PWM techique is extesively used for elimiatig harmful low-order harmoics i iput ad output voltage ad curret of static power. I PWM cotrol, the iverter switches are tured ON ad OFF several times durig a half cycle ad output voltage is cotrolled by varyig the pulse width. At preset, available PWM schemes ca be broadly classified as carrier modulated siusoidal PWM (SPWM) ad pre calculated programmed PWM schemes. The iverters of the pulses are varied by chargig the amplitude of the siusoidal wave form. I this method the lower order harmoics are elimiated. As the switchig for icreases more harmoics ca be elimiated. The limitig factors are the switchig devices speed, switch losses & power ratigs. c) Harmoic Elimiatio i Multi Level Iverter The output voltage V (t) of the multi level iverter ca be expressed i Fourier series as ( t) 1 = v = ( a si α + b cos α ) () Due to quarter wave symmetry of the output voltage the eve harmoics are abset ( b = ) ad oly odd harmoics are preset. The th amplitude of the harmoic a is expressed oly with the first quadrat switchig agle α 1, α, α 3,... α m 4V a = dc cosα k (3) π k=1 π < α < α < α <... α m < (4) For ay odd harmoics ca be expressed up to k th term, where m is the umber of variable correspodig to switchig agle α 1 through α m of the first quadrat Total harmoics distortio (THD); 1

4 9 IJRIC. All rights reserved. IJRIC E-ISSN: THD = (5) = 1 fudametal 1 th ( harmoic compoets) III. INVERTER EFFICIENCY The efficiecy of a hybrid iverter is higher tha this of a covetioal iverter, for the applicatios where the switchig losses are biggest. The efficiecy of the proposed structure is betwee the efficiecy of the ideal hybrid iverter ad this of a covetioal multilevel iverter fully supplied with dc-dc coverters. At the same time, it is a attractive solutio to get a large umber of levels together with a good efficiecy. IV.SIMULATION RESULTS 3 Phase to Groud Voltage 1 Voltage i Volts -1 - (a) x 1 4 (a) 4 Phase to Phase Voltage 3 Voltage i Volts (b) (b) x Stator Curret 4 Curret i Amps x 1 5 (c) (c)

5 9 IJRIC. All rights reserved. IJRIC E-ISSN: Electromagetic Torque 7 Electromagetic Torque Torque i Nm Torque i Nm x x 1 5 (d) (d) Speed of the Motor Speed Speed i RPM Speed i Rpm x x 1 5 (e) (e) Fig 4.Hybrid multilevel iverter for 15 levels. Fig 5. Hybrid multilevel iverter for 7 levels. a) Phase to groud voltage (Volts) a) Phase to groud voltage (Volts) b) Phase to phase voltage (Volts) b) Phase to phase voltage (Volts) c) Stator curret (Amps) c) Stator curret (Amps) d) Torque (Nm) d) Torque (Nm) e) Speed of the motor (rpm) e) Speed of the motor (rpm) V. RESULT ANALYSIS Steady state phase to groud voltage is show i fig 4. (a); the high umber of levels geerated by 15 level iverter ca be clearly appreciated i the voltage. To be icrease the umber of level early gets siusoidal voltage waveform compares the fig.5 (a) cosists of 7 level. The same ways fig.4 (b) ad fig.5 (b) are phase to phase voltage. Fig 4. (c) ad fig 5. (c) are illustrated the stator currets. The Fig 4. (c) cosists of high startig currets about 4 amps but it should be reach very quickly to get steady state. But the Fig 5. (c) cosists of high startig currets about 4 amps but it should be take some delay time to get steady state ad also gets harmoics i the waveform visibly. Fig 4. (d) ad fig 5. (d) are ivolves electromagetic Torque. The Fig 4. (d) cosists of high startig torque about 6 Nm but it should be reach very quickly to get steady state about. msec. But the Fig 5. (d) cosists of high startig torque about 4 Nm.but it should be take after.msec delay time to get steady state ad also gets harmoics i the waveform visibly. Fig 4. (e) ad fig 5. (e) are ivolves Speed of the motor. Fig 4.(e) illustrate the motor speed 15 rpm which is reaches.1 msec ad its maitai as costat. but the fig.5 (e) illustrate the motor speed 15 rpm which is take time. msec to reach ad its maitai as 3

6 9 IJRIC. All rights reserved. IJRIC E-ISSN: costat. ad fially the result aalysis says the umber of levels should icreases the harmoics less ad good performace. VI. CONCLUSION A improved hybrid multilevel iverter structure is proposed. The proposed hybrid iverter scheme is to get the better siusoidal output compare with low level iverters. The asymmetrical multilevel iverter is to obtai a high resolutio. The proposed a way to decrease the umber of isulated supplies ad to get better the efficiecy. The hybrid multilevel iverter techique is used to improve the level of iverter ad exteds the desig flexibility ad reduced the harmoics. REFERENCES [1] Y.S.Lai ad F.S.Shyu. Topology for hybrid multi level iverter, IEE Proc-Electr.Power Appl.Vol 149,No 6 ov. [] O.M. Mueller ad J.N. Park. Quasi-liear IGBT iverter topologies. APEC 94 Coferece Proceedigs, 1:53 59, February [3] M.D. Majrekar, P.K. Steimer, ad T.A. Lipo. Hybrid multilevel power coversio system: A competitive solutio for high power applicatios. IEEE Trasatios o Idustry Applicatios, 36(3): , May/Jue. [4] K.A. Corzie, S.D. Sudhoff, ad C.A. Whitcomb. Performace characteristics of a cascaded two-level coverter. IEEE Trasactios o Eergy Coversio, 14(3), September [5] A. Rufer, M. Veestra, ad K. Gopakumar. Asymmetric multilevel coverter for high resolutio voltage phase geeratio. EPE 99. [6] Gui-jia su. Multilevel DC lik iverter.ieee tras o idustry appl.vol.41.no.3.may/jue 5. [7] M. Veestra ad A. Rufer. Cotrol of a hybrid asymmetric multi- level iverter for competitive medium-voltage idustrial drives. IAS 3, 1:19 197, October 3. [8] ] S. Mariethoz ad A.C. Rufer. Desig ad cotrol of asymmetrical multilevel iverters. IECON, November. [9]A.k.Ali Othma Elimiatio of harmoics i multi level iverters with o equal DC sources usig PSO.IEEE cof.proce EPE PEMC 8. BIOGRAPHIES K.Ramai was bor i Vedarayam o May 7, 198. He is graduated i 4 from Bharathiar Uiversity, Coimbatore ad post graduated i 6 at Aa Uiversity, Cheai. He is a Research scholar i Aa Uiversity Cheai uder the guidace of Dr.A.Krisha, Dea, K.S.Ragasamy College of Techology, Tiruchegode.. He is curretly workig as a seior lecturer i the departmet of EEE at K.S.Ragasamy College of Techology, Tiruchegode from Jauary 6 owards. He published 1 iteratioal/atioal cofereces, jourals. his research iterest ivolves i power electroics, iverter, modelig of iductio motor ad optimizatio techiques. He is guidig UG, PG Studets. He is a ISTE, IETE member. Dr.A.Krisha received his Ph.D Degree i Electrical Egieerig from IIT, Kapur. He is IEEE seior member ad FIE. He is ow workig as a Dea at K.S.Ragasamy College of Techology, Tiruchegode ad guide at Periyar Uiversity, Salem ad Aa Uiversity, Cheai. His research iterest icludes Cotrol System, Digital Filter, Power Electroics, Digital Sigal Processig, ad Artificial Itelliget Techiques. He is a visitig professor i ISTE chapter. He has bee Published more tha 5 techical papers at various Natioal ad Iteratioal Cofereces ad Jourals. He is a visitig professor foreig uiversities ad ISTE. 4