Design and Implementation of Vedic Algorithm using Reversible Logic Gates

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1 Iteratioal Joural Of Egieerig Ad Computer Sciece ISSN: Volume 4 Issue 8 Aug 2015, Page No Desig ad Implemetatio of Vedic Algorithm usig Reversible Logic s Hemagi P.Patil 1, S.D. Sawat 2 1 Studet, E&TC Departmet, NBN School of Egieerig, Ambegao (BK), Savitribai Phule Pue Uiversity, Pue, Idia. hemagipatil63@gmail.com 2 Assistat Professor, E&TC Departmet. NBN Sihgad School of Egieerig. Ambegao (BK), Savitribai Phule Pue Uiversity, Pue, Idia. sharad.sawat@sihgad.edu Abstract: Multiplicatio is oe of the importat operatio i most digital sigal processig (DSP) applicatios. Sometimes the performaces of DSP applicatios is domiated by the speed at which a multiplicatio operatio ca be executed. The mai goal to desig the multiplier is to reduce the delay ad power dissipatio of a multiplier. Hece improved vedic multiplier is desiged to icrease the efficiecy of the system. Implemetig this vedic multiplier with reversible logic additioal reduces power dissipatio. Vedic multiplier is desiged usig oe of the vedic algorithm," Nikhilam Navatascaram Dasatah which is mea by All from Nie ad the last from Te. This method is implemeted usig reversible logic gates to reduce the power dissipatio ad umber of logic gates. The sythesis ad simulatio of Nikhilam Reversible algorithm is obtaied by usig ilix ISE 13.2, implemetatio ad detailed desig aalysis results are give i the paper. Keywords: Computatio,, Nikhilam Algorithm, Power dissipatio, Reversible logic gates, Vedic mathematics. 1. Itroductio I Digital sigal processor (DSP) the operatio is performed by various methods such as adder, subtractor, multiplier. The performace of the DSP processor is maily depeds o the multiplier, because the multiplicatio require more time ad area of the device. To improve the speed of the DSP, the digital multipliers such as Array, Wallace tree multiplier ad booth multiplier are desiged. These multipliers are implemeted usig the VLSI techology. The low power ad high speed VLSI ca be implemeted with differet methods. The three mai cocers for VLSI desig are power, area ad delay. I a array multiplier the multiplicatio of two biary umbers is doe by usig a combiatioal circuit that gives the product bits all at oce thus makig it a fast way of multiplyig two umbers sice the oly delay is the time for the sigals to propagate through the gates that form the multiplicatio array. The disadvatage of array multiplier is it eeds a large umber of gates ad hece it is less ecoomical [1]. The efficiecy of the multiplier is improve by usig the arragemet of adders, this arragemet ca be doe by two methods such as a carry save array (CSA) method ad a Wallace tree method. But these multiplier also have some drawback such as, the CSA multiplier caot achieve the high speed operatio because the executio time depeds upo the umber of bits of the multiplier ad i the Wallace tree multiplier, the circuit layout is difficult though the speed of operatio is high meawhile the circuit is somewhat ubalaced [1]. The aother improvemet i the multiplier is by the Booth recordig multiplier which reduces the umbers of partial products; this multiplier ca sca the three bits at a time to reduce the umber of partial products. This method also reduces the umber of adders ad hece the delay ecessary to produce the partial sums by examiig three bits at a time. This high performace Booth multiplier have drawback of power cosumptio, because of the large umber of adder cells (15 cells for 8 rows-120 core cells) which cosumes more power. The coclusio is that all these multiplier leads to more cosumptio of power ad reductio i efficiecy[1][2]. To reduce the power dissipatio ad improve the speed ad efficiecy of the multiplier, the ew techique is used which is called as the vedic multiplier. This vedic multiplier is based o aciet Idia vedic mathematics. Vedic mathematics cosists of 16 vedic formulae or sutras, from these 16 sutras the multiplier is desiged by usig two sutras, such as the Urdhvatiryakbhyam sutra which mea vertically ad crosswise ad aother oe is NikhilamNavatas' caramam Dasatah which mea All from 9 ad the last from 10. This paper proposes a implemetatio of Nikhilam Navatas'caramam Dasatah 8 8 multiplicatio algorithm by usig reversible logic gates. Reversible logic is oe of the promisig field for future low power desig techologies. Sice oe of the requiremets of all DSP processors ad other had held devices is to miimize power dissipatio multipliers with high speed ad lower dissipatios are critical. 2. Vedic Mathematics The fouder of vedic mathematics the great sait ad mathematicia 'Shri Bharati Krisa Thirthaji Maharaja',itroduced the Vedic Sutras (formulae). Vedic mathematics icludes 16 differet formulae for various Hemagi P.Patil, IJECS Volume 4 Issue 8 Aug, 2015 Page No Page 13734

2 computatio, the complex multiplier desig usig oe of the vedic formula for high speed performace ad low power applicatio is preseted i this paper.the multiplier is implemeted with the Nikhilam Sutra usig reversible logic gate is described i this paper. 2.1 Nikhilam Algorithm The Nikhilam Navatascaram Dasatah literally meas All from Nie ad the last from Te. The sutra basically meas start from the left most digit ad begi subtractig 9 from each of the digits; but subtract 10 from the last digit [2]. The followig examples illustrates the way i which this Sutra could reduce the umber of iteratios to reduce the whole Multiplicatio. Case 1: Whe both the umbers are less tha the base Nearest Base = 100 Table 1: Multiplicatio for the two umbers less tha the base. Multiplicad 92 (100-92)= 8 Mulitiplier 96 (100-96)= 4 Result 8832 RHS : Multiplicatio result = 32 LHS : Commo differece = 88 Fial Result : = 8832 (92-4) or (96-8) = = 32 Case 2: Whe two umbers are higher tha the base Nearest Base = 100 Table 2: Multiplicatio for the two umbers higher tha the base. Multiplicad 103 (100+3) = 3 Mulitiplier 109 (100+9)= 9 (103+9)or (109+3) = 112 Result = 27 RHS :Mutiplicatio result = 27 LHS : Here we calculate the commo additio, which is =112 ad 109+3=112. Fial Result = Case 3:Whe oe umber is higher ad oe umber is lower tha the base Nearest Base is 100 Table 3: Multiplicatio of the two umbers higher ad lower tha the base. Multiplicad 93 (100-93) = 7 Mulitiplier 105 (100+5)= +5 Result 9765 (93+5) or (105-7) = = -35 RHS : Multiplicatio result is -35, the subtract 35 from the base 100, hece the result = 65 LHS : Commo differece is 98, but subtract 1 from 98, hece the result = 97 Fial result = 9765 After this illustratio, ow we discuss the operatioal priciple of Nikhilam Sutra. Suppose we take two umbers for multiplicatio x ad y. p is the product of x ad y. mathematically it is expressed as, (1) the result of this umber is take as, At RHS, p xy First we subtract two umbers from the base a = 10 x ad b = 10 y respectively. The multiply these two umbers, RHS ab Now for LHS, LHS ( x b) ( y a) (2) (3) Now the fial result is p (4) 10 2 xy 10 ( x y) 10 ( x y) x b ab y a ab p (5) Hece the multiplicatio of two umbers ca be doe by reducig the umber of steps. As less umber of steps required to perform the multiplicatio, the delay required is also miimum ad it also reduces the power dissipatio. This is the reaso that Nikhilam multiplier is efficiet for the large umber multiplicatio. 3. Reversible Logic s Nowadays, it is ecessary to desig a complex digital system which dissipates a low power because, because as the complexity of system icreases it will icrease the problem of heat dissipatio. This complexity of digital system gives rise to the developmet of ew computig hardware which dissipates the less heat to icrease the computig power. I 1961,Ladauer itroduced that losig of bit i circuits causes the smallest amout of heat i computatio ad the theoretical limit of eergy dissipatio for losig of oe bit computatio is KTl2[4]. Where K is a Boltzma s costat equals to JK 1 ad T is the temperature at which the computatio is performed[4]. At T=300K, this limit is Joules. Reversible logic has received great attetio over the irreversible circuits due to their ability to reduce the power dissipatio which is the mai requiremet i low power VLSI desig as well as the computig system. It has wide applicatios i low power CMOS ad Optical iformatio processig, DNA computig, quatum computatio ad aotechology. Irreversible hardware computatio results i eergy dissipatio due to iformatio loss. Reversible logic supports the process of ruig the system both forward ad backward. This meas that reversible computatios ca geerate iputs from outputs ad ca stop ad go back to ay poit i the computatio history. Garbage outputs are those which do ot cotribute to the reversible logic realizatio of the desig. Quatum cost refers to the cost of the circuit i terms of the cost of a primitive gate There are some importat costrait for reversible logic circuits as follows: Hemagi P.Patil, IJECS Volume 4 Issue 8 Aug, 2015 Page No Page 13735

3 Fa-out is ot allowed i the reversible logic circuits[7]. Miimum umber of costat iputs must be use[8]. Reversible circuits ca be optimized to obtai miimum umber of garbage output[9]. Quatum cost should be miimum for reversible logic circuit[9]. 3.1 Basic Reversible Logic s: Some of the basic reversible logic gates are proposed such as Toffoli gate(tg) [12], Fredki gate (FRG)[13], Feyma gate (FG)[14],Peres gate (PG),HNG gate. I the proposed system we uses the Peres (PG) ad HNG gate. Here we are reviewig the logic circuit ad quatum implemetatio of these reversible gates Feyma : The Feyma gate is a 2 2 gate ad its logic circuit is as show i the figure[14]. It is also kow as Cotrolled Not (CNOT). It has quatum cost 1 ad is geerally used for Fa Out purposes HNG : HNG gate is a gate ad its logic circuit is as show i the figure. It has quatum cost 6. It is used for desigig ripple carry adders. It ca produce both sum ad carry i a sigle gate thus miimizig the garbage ad gate couts. W HNG P = W Q = R=W Z S= (W ) W. Z 4. System Architecture Figure 5: HNG The block diagram of proposed system cosists of the basic blocks such as Base selectio Module (BSM), 8 bit reversible multiplier ad 8 bit. Block diagram of the system is give i Fig.7 : a[7:0] b[7:0] Feyma P= BSM Peres Q = Figure 1: Fyma Peres : Peres gate is a 3x3 gate ad its logic circuit is as show i the figure [15]. It has quatum cost 4. It is used to realize various Boolea fuctios such as AND, OR. P= Q= Z R = (.) Z Figure 2: Peres Fredki : It is a 3x3 gate ad its logic circuit is as show i the figure [13]. It has quatum cost 5. It ca be used to implemet a multiplexer. Z Fredki P= Q = 1 +.Z R =.+ 1 Z Figure 3: Fredki Toffoli : The Toffoli is a 3 3 reversible gate with 3 iputs ad 3 outputs. It has Quatum cost 5 [12]. LHS of the Product RHS of the Product Figure 6: System Architecture First block of the proposed system is Base Selectio Module(BSM), which selects the base of the iputs a ad b. The output of the BSM is give to the Subtractor. I subtractor block the iputs "a" ad "b" are subtract from the Base ad the output is give to the multiplier ad the adder or subtractor block. The mai Block of this proposed system is 8 bit reversible multiplier. 4.1 SUBTRACTO R / ADDER SUBTRACTOR MULTIPLIER ADDER performs the importat computatio of the proposed Nikhilam Vedic multiplier. This multiplier is reversible multiplier because the multiplicatio operatio is performed by the two reversible logic gates. These two reversible logic gates are HNG ad Peres (PG). The block diagram of the multiplier is show below : Z Toffoli P= Q= R=. Z Figure 4: Toffoli Hemagi P.Patil, IJECS Volume 4 Issue 8 Aug, 2015 Page No Page 13736

a[7:4] b[7:4] a[3:0] b[7:4] a[7:4] b[3:0] a[3:0] b[3:0] Desig aalysis cotais the report of delay ad device utilizatio summary. Table 4: Timig Summary Speed Grade -4 Combiatioal Path Delay 8.

up of the two reversible gates such as HNG gate ad PG gate. HNG gate is a gate It is used for desigig ripple carry adders.

4 a[7:4] b[7:4] a[3:0] b[7:4] a[7:4] b[3:0] a[3:0] b[3:0] Desig aalysis cotais the report of delay ad device utilizatio summary. Table 4: Timig Summary Speed Grade -4 Combiatioal Path Delay 8.73s Number of Slices Table 5: Device Utilizatio Summary Used Available Utilizatio % Figure 7 : Block Diagram of Reversible Number of 4 iput LUTs % The multiplier is the block made up of the two reversible gates such as HNG gate ad PG gate. HNG gate is a gate It is used for desigig ripple carry adders. It ca give both sum ad carry i a sigle gate thus miimizig the garbage ad gate couts. The logic circuit of this gate is show i sectio 3. Peres gate(pg) is a 3x3 gate. It is used to realize various Boolea fuctios such as AND, OR. The logic circuit of this gate is also show i sectio 3. Due to the use of reversible gates i multiplier miimum umber of gates are utilize i the system. It should require miimum quatum cost ad reversible gate does ot allows Fa-out. 5. Simulatio Results ad Desig Aalysis After the sytem desig, the code is verified usig a simulatio software i.e. ilix ISE Simulator 13.2 for differet iputs to geerate outputs.the simulatio is doe by the behavioral simulatio. The code is sythesized usig Sparta 3 FPGA. The differet iputs are give usig the VHDL test bech. The RTL schematic ad simulatio results are show below: Number of boded IOBs % Figure 9: Simulatio Waveform for 8 8 multiplicatio 6. Coclusio The objective of developig the vedic multiplier is to icrease the speed of the operatio ad reduce the propagatio delay ad power cosumptio. From the vedic formulae Nikhilam formula, is used for the multiplicatio of large umbers. I proposed system the multiplier is implemeted by usig the reversible logic gates to miimize the utilizatio of logic gates ad reduce the power cosumptio. Nikhilam multiplier is implemeted ad simulated i ilix 13.2 ISE simulator. The simulatio waveform ad delay results are give i the paper. I future this system ca be implemet for the ALU as well as for desigig of FFT to reduce the umber of logic gates ad delay of the system. Figure 8: RTL Schematic Refereces [1] H. D.Tiwari, G. Gakhuyag, C.Kim,. Cho, desig based o aciet Idia Vedic Mathematics, Hemagi P.Patil, IJECS Volume 4 Issue 8 Aug, 2015 Page No Page 13737

5 Iteratioal SoC Desig coferece Busa, Vol.2. pp.65-68, [2] P. Mehta, ad D. Gawali, Covetioal versus Vedic mathematical method for Hardware implemetatio of a multiplier, Proceedigs of IEEE Iteratioal Coferece o Advaces i Computig, Cotrol, ad Telecommuicatio Techologies, Trivadrum, Kerala, pp , [3] J. S. S. Bharathi, Kirsa Tirathji, Vedic Mathematics or Sixtee Simple Sutras From The Vedas, Motilal Baarsidas Pulishers Pvt Ltd, Varaasi (Idia), [4] R.Ladauer, Irreversibility ad heat geeratio i the computatioal process, IBM J. Res. Develop., vol. 5, pp , [5] Matthew Moisi ad Nagaraja Ragaatha, Desig of a reversible ALU based o a ovel programmable reversible logic gate structures, IEEE computer society aual symposium o vlsi, [6] G.De Mey ad A.De Vos, The miimum eergy for a oe bit commutatio: a proof of the Ladauer limit, proc.26th iteratioal cof. O microelectroics IEEE, [7] Michael P.Frak, Itroductio to reversible computig: motivatio, progress, ad challeges, proceedigs of 2d iteratioal coferece o computig frotiers ACM New ork, [8] Mjid Haghparast, Mazid Mohammdi, Keiva Navi, Optimized reversible multiplier circuit, Joural of circuits, systems ad computers. [9] Abu Sadat Md.Sayem ad Sajib Kumar Mitra, Efficiet approach to desig low power reversible logic blocks for field programmable gate arrays /11/IEEE [10] H.R.Bhagyalakshmi, M.K.Vekeatesha, A improved desig of a multiplier usig reversible logic gates, Iteratioal joural of egieerig sciece ad techology, vol.2 (8), pp ,2010. [11] T. Toffoli, Reversible Computig, Tech memo MIT/LCS/TM-151, MIT Lab for computer sciece [12] E. Fredki ad T. Toffoli, Coservative logic, It 1J. Theoretical Physics, Vol.11, pp ,1985. [13] R. Feyma, Quatum Mechaical Computers, Optics News, Vol11-20,1985. [14] Peres, Reversible Logics ad Quatum computers, Physical review A,32: ,1985. Hemagi P.Patil, IJECS Volume 4 Issue 8 Aug, 2015 Page No Page 13738

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