Test Time Minimization for Hybrid BIST with Test Pattern Broadcasting

Transcription

1 Test Time Miimizatio for Hybrid BIST with Test Patter Broadcastig Raimud Ubar, Maksim Jeihhi Departmet of Computer Egieerig Talli Techical Uiversity EE Talli, Estoia {raiub, Gert Jerva, Zebo Peg Embedded s Laboratory (ESLAB) Liköpig Uiversity SE Liköpig, Swede {gerje, zebpe}@ida.liu.se Abstract 1 : This paper describes a hybrid BIST architecture for testig core-based systems together with a method for test time miimizatio. The approach uses test patter broadcastig for both pseudoradom ad determiistic patters. To overcome the high complexity of the test time miimizatio problem we propose a fast algorithm to fid a efficiet combiatio of pseudoradom ad determiistic test sets uder give memory costraits. The efficiecy of the approach is demostrated by experimetal results. 1. Itroductio The advaces i microelectroics techology has made it possible to itegrate a large umber of differet fuctioal blocks, usually referred as cores, i a sigle IC. Testig of such systems-o-chip (SoC) is a problematic ad time cosumig task, maily due to the resultig IC s complexity ad the high itegratio desity [1]. Oe of the solutios to this problem is o-chip test, usually referred to as built-i self-test (BIST). I our earlier work we have proposed a hybrid BIST techique [2], [3] as oe of the promisig methodologies for self-test i SoCs. The key issue for the hybrid BIST is to fid the best balace betwee pseudoradom ad determiistic test patters, such that the system desig costraits are satisfied ad test cost is miimized. There exists extesive work for testig core-based systems. The mai emphasis has bee so far o test schedulig, TAM desig ad testability aalysis. The earlier test schedulig work has had the objective to determie start times for each test such that the total test applicatio time is miimized. This assumes a fixed set of tests ad test resources together with a test access architecture. Some approaches ca also take ito accout test coflicts ad differet costraits, e.g. power [4]-[8]. However there has t bee ay work to fid the optimal test sets for testig every idividual core i such a maer that the total system test time is miimized ad the differet desig costraits are satisfied. I our earlier work it has bee assumed that every core has its ow dedicated BIST logic that is capable to 1 This work has bee supported by the EC project EVIKINGS (IST ), Estoia Sciece Foudatio Grats 4300 ad 5649, ad by the Swedish Foudatio for Strategic Research (SSF) uder the Strategic Itegrated Electroic s Research (STRINGENT) program. produce a set of idepedet pseudoradom test patters [9]. This however may lead to high area overhead ad may require redesig of the cores (to iclude the BIST logic). I this paper we propose a ovel self-test approach that is based o test patter broadcastig [10]. The proposed architecture eables us to geerate pseudoradom patter simultaeously for all cores by usig a sigle pseudoradom patter geerator. These patters will be complemeted with dedicated determiistic patters for every idividual core ad the whole test process is carried out i such a maer that the total testig time is kept miimal without violatig the desig costraits, i particular, the amout of o-chip resources. I the followig sectio we will describe the hybrid BIST architecture with test patter broadcastig i detail. It is followed by the test time miimizatio procedure that is fially demostrated with experimetal results. 2. Hybrid BIST Architecture Usig Test Patter Broadcastig I our earlier work we have proposed a hybrid BIST methodology ad its optimizatio for sigle core desigs [2]-[3]. We have also proposed a hybrid BIST architecture for multi-core desigs, where it is assumed, that every core i the system has it s ow dedicated BIST structure [3]. This type of architecture however may ot always be feasible as ot all cores may be equipped with self-test structures. It may also itroduce a sigificat area overhead ad the performace degradatio, as some cores may require excessively large self-test structures (LFSRs). To avoid those problems a sigle pseudoradom test patter geerator for the whole system gives a better solutio. It ca be implemeted as a dedicated hardware block or i software. I the latter case the test program, together with test data (LFSR polyomial, iitial state, pseudoradom test legth, sigature), is kept i a ROM ad executed i a test mode. This, however, may lead to a very complex test cotroller, as every core requires pseudoradom patters with differet characteristics (polyomial, iitial state ad legth, for example) ad therefore may lead to very complex ad expesive solutios. I this paper we propose a ovel methodology, where oly a sigle set of pseudoradom test patters that is broadcasted to all cores simultaeously will be used. This uiversal pseudoradom test set is followed by additioal determiistic vectors applied to every idividual core, if eeded. Those determiistic test vectors are geerated

2 durig the developmet process ad are stored i the system. For this purpose arbitrary software test geerators may be used, based o determiistic, radom or geetic algorithms. This architecture together with appropriate test access mechaism is depicted i Figure 1. Embedded Tester LFSR Emulator Tester Test Cotroller Core Core k Core Core Figure 1. Hybrid BIST architecture with test patter broadcastig TAM 12 Testig of all cores is carried out i parallel, i.e. all pseudoradom patters as well as each determiistic test sequece TD k is applied to all cores i the system. The determiistic test sequece TD k is a determiistic test sequece geerated oly by aalyzig the core C k. For the rest of the cores this sequece ca be cosidered as a pseudoradom sequece. The width of the hybrid test sequece TH is equal to MAXINP=max{INP k }, k=1, 2,,, where INP k is the umber of iputs of the core C k. For each determiistic test set TD k, where INP k < MAXINP, the ot specified bits will be completed with pseudoradom data, so that the resultig test set TD k * ca be applied i parallel to the other cores i the system as well. I case of hybrid BIST, we ca dramatically reduce the legth of the iitial pseudoradom sequece by complemetig it with determiistic stored test patters, ad achieve 100% fault coverage. The method proposed i this paper helps to fid tradeoffs betwee the legth of the best pseudoradom test sequece ad the umber of stored determiistic patters, uder give memory costraits. The problem of fidig the exact solutio is NP-complete. To overcome the high complexity of the problem we will propose i the followig a simple ad fast algorithm that gives us a quasioptimal solutio with low computatioal cost. Although the solutio is ot optimal it ca be used successfully for desig space exploratio. 3. Formulatio of the Test Time Miimizatio Problem Let us assume a system S, cosistig of cores C 1, C 2,, C, that are all coected to the bus. For this system a pseudoradom test sequece TP with legth LP is geerated ad applied i parallel to all cores. This sequece should preferably achieve 100% fault coverage for all cores. I this sequece we ca specify... k subsequeces TP k with legth LP k, k = 1, 2,,, for each core, so that all the subsequeces start i the begiig of TP, ad by the last patter of a subsequece TP k the 100% fault coverage for the core C k is reached. I a case whe LP k is too log, we restrict the legth of the pseudoradom sequece to the maximum acceptable legth LP max, thus reducig the legth of the whole pseudoradom sequece to LP max. For all cores where 100% fault coverage has ot bee achieved with this test set TP we geerate complemetary joit set of determiistic test patters TD, so that by applyig to the system both test sequeces TP ad TD with total legth L, the 100% fault coverage for all cores is achieved. TP Figure 2. Iitial test sequece for multi-core system As a example, i Figure 2 a hybrid test sequece TH = {TP, TD} is show cosistig of a pseudoradom test set TP with legth LP ad a determiistic test set TD with legth LD (L=LP+LD). Here LP i deotes a momet where 100% fault coverage is reached for the core C i, ad LP j deotes a momet where 100% fault coverage is reached for the core C j. I this example we assume that ot for all cores 100% fault coverage is achieved by the pure pseudoradom test sequece TP ad a additioal determiistic test set TD has to be applied to achieve 100% fault coverage. Those determiistic test patters are precomputed ad stored i the system. The mai problem of the hybrid BIST is to fid the optimal balace betwee the pseudoradom test part TP ad the determiistic test part TD, so that the total testig time is miimal, ad that the memory costraits COST M.LIMIT for storig determiistic test patters are satisfied, COST M COST M,LIMIT. The memory cost ca be calculated as follows: COSTM = ( LDk * INPk ), k = 1 where INP k is the umber of iputs of the core C k ad LD k is the legth of the determiistic test set of the core C k. If the same determiistic patter is eeded simultaeously for a subset S S of cores, we say that it is dedicated for the core C k S with the highest umber of iputs. The efficiecy of the hybrid BIST approach is achieved by miimizig the total test legth LH = LP + k = 1 LD k TD LP i LP=LP max L LP j for a give memory costrait COST M COST M,LIMIT. As all cores are tested i parallel, the problem is to fid a time momet whe to switch from the parallel pseudoradom test to the parallel determiistic test. The problem of miimizig the hybrid test legth at the give memory costraits for parallel multi-core testig is extremely complex. The mai reasos of this complexity are the followig: The determiistic test patters of oe core are used as pseudoradom test patters for all other cores; ufortuately there will be (-1) relatioships for

3 cores to aalyse for fidig the optimal iteractio; o the other had the determiistic test sets are ot readily available ad calculated oly durig the aalysis process; For a sigle core a optimal combiatio of pseudoradom ad determiistic patters ca be foud by rather straightforward algorithms [9]; but as the optimal time momet for switchig from pseudoradom to determiistic test will be differet for differet cores the existig methods caot be used ad the parallel testig case is cosiderably more complex. For each core the best iitial state of the LFSR ca be foud experimetally, but to fid the best LFSR for testig all cores i parallel is a very complex ad time cosumig task. To overcome the high complexity of the problem we have proposed a straightforward algorithm for calculatig TP ad TD, where we eglect the optimal solutios for idividual cores i favour of fidig a quasioptimal solutio for the whole system [11]. 4. Test Time Miimizatio Procedure We solve the test time miimizatio problem i three cosecutive steps: first, we fid as good as possible iitial state for the LFSR for all cores; secod, we geerate a determiistic test sequece if the 100% fault coverage caot be reached by a pure pseudoradom test sequece for all cores; ad third, we update the test sequece by fidig the quasi-optimal time momet for switchig from parallel pseudoradom testig to parallel determiistic testig at the give memory costrait. Fidig the iitial state for the LFSR. To fid the best iitial state for the parallel pseudoradom test geerator, we carry out m experimets, with radomly chose iitial states, for all cores. Let us deote with INP k the umber of iputs of core C k. Withi each j th experimet we calculate for each core C k the weighted legth LP k,j * INP k of the test sequece which achieves the 100% fault coverage for the core C k. The, for all the experimets we calculate the average weighted legth L j = 1 k= 1 LP k * INP as the quality merit of pseudoradom sequeces for parallel testig of all cores. The best pseudoradom sequece is the oe that gives as shortest L j, j = 1,2,, m. Let us call this iitial pseudoradom test TP 0. Geeratio of the iitial determiistic test set. Suppose there are k cores where 100% fault coverage caot be achieved with TP 0 because of the practical costraits to the pseudoradom test legth. Let us deote this subset of cores with S S. Let us deote with FP 0 i fault coverage of the core C i, achieved by TP 0. Let us order the cores i S as C 1, C 2,, C k, so that for each i < j, 1 i,j k, we have FP i FP j. We assume here that every determiistic test patter, to be propagated, j k to the system, has to be as wide as the maximum width of the TAM. If the core uder test has less iputs tha the width of the TAM, all uused bits i the TAM are filled with pseudoradom data. The iitial determiistic test set ca be foud by geeratig determiistic test patters for every core i S idividually, startig from the core C 1, i order to achieve 100% fault coverage for this particular core. The geerated test patters are simulated with the remaiig cores ad their respective fault coverages FP j will be updated. This process is carried out for every cores i S ad guaratees 100% fault coverage for all cores i the system. Optimizatio of the test sequece. After the previous 2 steps we have obtaied a hybrid BIST sequece TH 0 = {TP 0, TD 0 } with legth LH 0, cosistig of the pseudoradom part TP 0 with legth LP 0, ad of the determiistic part TD 0 with legth LD 0. I special case TD 0 may be a empty set. Let us deote with COST M (TD 0 ) the memory cost of the determiistic test set TD 0. We assume that the memory costraits are at this momet satisfied: COST M (TD 0 ) < COST M,LIMIT. I a opposite case, if COST M (TD 0 ) > COST M,LIMIT, the legth of the pseudoradom sequece has to be exteded ad the secod step of the procedure has to be repeated. If COST M (TD 0 ) = COST M,LIMIT the third step is uecessary, ad the procedure is fiished. Uder optimizatio of TH 0 we mea the miimizatio of the test legth LH 0 at the give memory costraits COST M,LIMIT. It is possible to miimize LH 0 by shorteig the pseudoradom sequece, i.e. by movig step-by-step efficiet patters from the begiig of TP 0 to TD 0 ad by removig all other patters betwee the efficiet oes from TP 0, util the memory costraits will become violated, COST M (TD 0 ) > COST M,LIMIT. To fid the efficiet test patters i the begiig of the TP 0 we have to fault simulate the whole test sequece TH 0 for all the cores i the opposite way from the ed to the begiig. As a result of the fault simulatio we get for each patter the icremets of fault coverage i relatio to each core = { 1, 2,,,}. As the result of this procedure we create a ew hybrid BIST sequece TH = {TP,TD} with total legth LH ad with legths LP LP 0 ad LD LD 0 for the ew pseudoradom ad determiistic parts correspodigly. Due to removal of all o-efficiet patters LP - LP 0 >>LD 0 LD. Hece, the total legth of the ew hybrid BIST sequece will be cosiderably shorter compared to its iitial legth, LH < LH 0. The proposed approach does t guaratee absolute miimum of the test legth, however, the procedure is rather straightforward (similar to the greedy algorithm) ad fast ad therefore suitable for use i the desig process. The method ca be used to fid a cheap practical solutio as well as for a fast referece for compariso with more sophisticated optimizatio algorithms to be developed i the future.

4 5. Experimetal data We have performed experimets with three systems composed from differet ISCAS bechmarks as cores. The data of these systems are preseted i Table 1 (the lists of used cores i each system). ame List of used cores 6 cores 7 cores 5 cores c5315 c432 c880 c880 c499 c5315 c432 c880 c3540 c499 c1355 c1908 c499 c1908 c880 c5315 c5315 c6288 Table 1. s used for experimets The experimetal results for three differet systems are preseted i Table 2. The total legth of the hybrid test sequece is calculated for three differet memory costraits. The CPU time used for carryig out the procedure for each system is depicted i the last colum. For the first two systems ad the cost of the procedure is determied oly by the CPU time for pseudoradom patter geeratio ad subsequet simulatio of test patters for all the cores i the system. For the third system the CPU time icludes also the time eeded for geeratio of determiistic patters. I this case the legth of the pseudoradom test, to reach 100% fault coverage, would be too log to be practically feasible. The pseudoradom test was stopped at the legth of patters with 98,26% fault coverage for oe of the cores ad 26 determiistic patters were geerated i order to achieve 100% fault coverage. I Figure 3 the test schedules for all systems are preseted whe memory costrait is at bits. The left part represets the pseudoradom test, ad the right part represets the determiistic test. The full overview about the all possible hybrid BIST solutios for the three systems is preseted i Figure 4 represetig the memory cost as the fuctio of total test legth. By these curves for a arbitrary memory costrait the correspodig total testig time ca be foud. The three costraits illustrated i Table 2 are also highlighted i Figure Coclusios Test Legth Figure 3. Test Schedules Pseudoradom Determiistic We have preseted a ew architecture for the hybrid BIST i multi-core systems where for the first time the hybrid BIST idea is exteded by the cocept of test patter broadcastig, where the determiistic test set of each core is applied i parallel to all other cores i a similar way as the pseudoradom test patters. For this ew architecture we have formulated the task to miimize the total test time of the hybrid BIST at give memory limitatios for storig determiistic test patters. The problem of fidig the exact solutio for the formulated task is NP-complete. To overcome the high complexity of the problem we have proposed a straightforward algorithm for calculatig a possible combiatio betwee pseudoradom ad determiistic test sequeces, where we eglect the optimal solutios for idividual cores i favour of fidig a quasioptimal solutio for the whole system. The described procedure does t guaratee miimal test legth, however, the procedure is simple (similar to the greedy algorithm) ad fast. The latter is demostrated also by correspodig experimetal results. Although the curret work covers oly combiatorial circuits, it ca easily be exteded also for full-sca sequetial circuits ad ca be cosidered as a future work. The method proposed ca be used first, as a cheap practical solutio, ad secod, as a quickly computable referece for compariso with more sophisticated optimizatio algorithms to be developed i future. Name Number of cores Costrait Pseudoradom Test Legth Determiistic Test Legth Total Test Legth CPU Time Used (sec) , , Table 2. Experimetal Results

5 Total Test Applicatio Time Figure 4. cost as the fuctio of total test legth Refereces [1] B. T Murray, J. P. Hayes, Testig ICs: Gettig to the core of the problem, IEEE Trasactios o Computer, Vol. 29, pp , November [2] G. Jerva, Z. Peg, R. Ubar, Test Cost Miimizatio for Hybrid BIST, IEEE It. Symp. o Defect ad Fault Tolerace i VLSI s (DFT 00), pp , Yamaashi, Japa, October [3] G. Jerva, P. Eles, Z. Peg, R. Ubar, M. Jeihhi, Test Time Miimizatio for Hybrid BIST of Core- Based s, IEEE Asia Test Symposium 2003 (ATS 03), Xia, Chia, November 2003 (accepted for publicatio). [4] Y. Zoria, A distributed BIST cotrol scheme for complex VLSI devices, Proceedigs of the IEEE VLSI Test Symposium (VTS), pp. 4-9, Atlatic City, NJ, April [5] R. Chou, K. Saluja, ad V. Agrawal, Schedulig Tests for VLSI s Uder Power Costraits, IEEE Trasactios o VLSI s, Vol. 5, No. 2, pp , Jue [6] M. Sugihara, H. Date, H. Yasuura, Aalysis ad Miimizatio of Test Time i a Combied BIST ad Exteral Test Approach, Desig, Automatio & Test I Europe Coferece (DATE 2000), pp , Paris, Frace, March [7] K. Chakrabarty, Test Schedulig for Core-Based s Usig Mixed-Iteger Liear Programmig, IEEE Trasactios o Computer-Aided Desig of Itegrated Circuits ad s, Vol. 19, No. 10, pp , October [8] E. Larsso, Z. Peg, A Itegrated Framework for the Desig ad Optimizatio of SOC Test Solutios, Joural of Electroic Testig; Theory ad Applicatios (JETTA), for the Special Issue o Plugad-Play Test Automatio for -o-a-chip, Vol. 18, o. 4/5, pp , August [9] G. Jerva, Z. Peg, R. Ubar, H. Kruus, A Hybrid BIST Architecture ad its Optimizatio for SoC Testig, IEEE rd Iteratioal Symposium o Quality Electroic Desig (ISQED'02), pp , Sa Jose, CA, March [10] K-J. Lee, J-J. Che, C-H. Huag, Broadcastig Test Patters to Multiple Circuits, IEEE Trasactios o Computer-Aided Desig of Itegrated Circuits ad s, Vol.18, No.12, December 1999, pp [11] R. Ubar, M. Jeihhi, G. Jerva, Z. Peg, Hybrid BIST Optimizatio for Core-based s with Test Patter Broadcastig, IEEE Iteratioal Workshop o Electroic Desig, Test ad Applicatios (DELTA 2004), Perth, Australia, Jauary 2004 (submitted).