Hybrid BIST Optimization for Core-based Systems with Test Pattern Broadcasting

Transcription

1 Hybrid BIST Optimizatio for Core-based Systems with Test Patter Broadcastig Raimud Ubar, Masim Jeihhi Departmet of Computer Egieerig Talli Techical Uiversity, Estoia {raiub, Gert Jerva, Zebo Peg Embedded Systems Laboratory (ESLAB) Liöpig Uiversity, Swede {gerje, Abstract 1 This paper itroduces a techique for hybrid BIST time optimizatio for testig core-based systems that use test patter broadcastig for both pseudoradom ad determiistic patters. First we formulate the test time miimizatio problem for such a architecture. Thereafter we preset algorithms for fidig a efficiet combiatio of pseudoradom ad determiistic test sets uder give memory costraits, so that the system testig time ca be shorteed. We also aalyze the sigificace of the pseudoradom sequece quality for the fial results. The results are illustrated ad the efficiecy of the approach is demostrated by experimetal results. 1. Itroductio Built-i self-test (BIST) has became icreasigly viable solutio for testig complex systems-o-chip (SoC). Although it is a promisig techology it also has its problems. Some of the problems are related to the fact that BIST uses typically log sequeces of pseudoradom test patters that may lead to the very log test times ad caot guaratee sufficietly high fault coverage. Therefore we have proposed hybrid BIST [1], [2] as a possible improvemet of a classical logic BIST for testig SoCs. The ey issue for the hybrid BIST is to fid the best balace betwee pseudoradom ad determiistic test patters, such that the system desig costraits are satisfied ad test cost is miimized. Testig core-based systems is a complex problem i geeral. The existig wor has cocetrated so far o test schedulig, TAM desig ad testability aalysis. This assumes a fixed set of tests ad test resources together with a appropriate test access architecture. Some approaches ca also tae ito accout test coflicts ad 1 This wor has bee supported by the EC project EVIKINGS (IST ), Estoia Sciece Foudatio Grats 43 ad 5649, ad by the Swedish Foudatio for Strategic Research (SSF) uder the Strategic Itegrated Electroic Systems Research (STRINGENT) program. differet costraits, e.g. power [3]-[8]. However there has t bee ay wor to fid the optimal test sets for testig every idividual core i such a maer that the total system test time is miimized ad the differet desig costraits are satisfied. I our earlier wor it has bee assumed that every core has its ow dedicated BIST logic that is capable to produce a set of idepedet pseudoradom test patters [9]. We have also exteded the same approach for multicore systems where both, combiatorial cores ad sequetial cores with full sca may be used [2], [1]. This however may lead to high area overhead ad may require redesig of the cores as ot all cores may be equipped with self-test structures. Therefore we have recetly proposed a ovel self-test architecture that is based o test patter broadcastig [11]. I this approach oly a sigle pseudoradom test patter geerator is used ad all test patters are broadcasted simultaeously for all cores i the system. These patters will be complemeted with dedicated determiistic patters for every idividual core, if eeded. Those determiistic test vectors are geerated durig the developmet process ad are stored i the system. The whole test process has to be carried out i such a maer that the total testig time is ept miimal without violatig the desig costraits, i particular, the amout of o-chip resources. I this paper we will propose a method to evaluate tradeoffs betwee the legth of the pseudoradom test sequeces ad the umber of stored determiistic patters, uder give memory costraits. The problem of fidig the exact solutio is NP-complete. To overcome the high complexity of the problem we will propose i the followig a simple ad fast algorithm that gives us a ear-optimal solutio with low computatioal cost. Although the solutio is ot optimal it ca be used successfully for desig space exploratio ad gives a sigificat improvemet compared to the ad-hoc desiger solutio. I the followig sectio we will formulate the test time miimizatio problem for hybrid BIST. It is followed by

2 the proposed test time miimizatio algorithm that is followed by experimetal results ad coclusios. 2. Formulatio of the test time miimizatio problem Let us assume a system S, cosistig of cores C 1, C 2,, C. For this system a pseudoradom test sequece TP with legth LP is geerated ad applied i parallel to all cores. This sequece should preferably achieve 1% fault coverage for all cores. I this sequece we ca specify subsequeces TP with legth LP, = 1, 2,,, for each core, so that all the subsequeces start i the begiig of TP, ad by the last patter of a subsequece TP the 1% fault coverage for the core C is reached. I a case whe LP is too log, we restrict the legth of the pseudoradom sequece to the maximum acceptable legth LP max, thus reducig the legth of the whole pseudoradom sequece to LP max. For all cores where 1% fault coverage has ot bee achieved with this test set TP we geerate complemetary joit set of determiistic test patters TD, so that by applyig to the system both test sequeces TP ad TD with total legth L, the 1% fault coverage for all cores is achieved. TP Figure 1. Iitial test sequece for multi-core system As a example, i Figure 1 a hybrid test sequece TH = {TP, TD} is show cosistig of a pseudoradom test set TP with legth LP ad a determiistic test set TD with legth LD (L=LP+LD). Here LP i deotes a momet where 1% fault coverage is reached for the core C i, ad LP j deotes a momet where 1% fault coverage is reached for the core C j. I this example we assume that ot for all cores 1% fault coverage is achieved by the pure pseudoradom test sequece TP ad a additioal determiistic test set TD has to be applied to achieve 1% fault coverage. Those determiistic test patters are precomputed ad stored i the system. The mai problem of the hybrid BIST is to fid the optimal balace betwee the pseudoradom test part TP ad the determiistic test part TD, so that the total testig time is miimal, ad that the memory costraits COST M.LIMIT for storig determiistic test patters are satisfied, COST M COST M,LIMIT. The memory cost ca be calculated as follows: COST M = = 1 ( LD * INP ), TD LP i LP=LP max L LP j where INP is the umber of iputs of the core C ad LD is the legth of the determiistic test set of the core C. If the same determiistic patter is eeded simultaeously for a subset S S of cores, we say that it is dedicated for the core C S with the highest umber of iputs. The tas to be solved i this paper is to miimize the total LH = LP + = 1 LD for a give memory costrait COST M COST M,LIMIT. As all cores are tested i parallel, the problem is to fid a time momet whe to switch from the parallel pseudoradom test to the parallel determiistic test. The problem of miimizig the hybrid at the give memory costraits for parallel multi-core testig is extremely complex. The mai reasos of this complexity are the followig: The determiistic test patters of oe core are used as pseudoradom test patters for all other cores; ufortuately there will be (-1) relatioships for cores to aalyse for fidig the optimal iteractio; o the other had the determiistic test sets are ot readily available ad calculated oly durig the aalysis process; For a sigle core a optimal combiatio of pseudoradom ad determiistic patters ca be foud by rather straightforward algorithms [9]; but as the optimal time momet for switchig from pseudoradom to determiistic test will be differet for differet cores the existig methods caot be used ad the parallel testig case is cosiderably more complex. For each core the best iitial state of the LFSR ca be foud experimetally, but to fid the best LFSR for testig all cores i parallel is a very complex ad time cosumig tas. To overcome the high complexity of the problem we will propose a straightforward algorithm for calculatig TP ad TD, where we eglect the optimal solutios for idividual cores i favour of fidig a ear-optimal solutio for the whole system. 3. Test time miimizatio procedure We solve the test time miimizatio problem i three cosecutive steps: first, we fid as good as possible iitial state for the LFSR for all cores; secod, we geerate a determiistic test sequece if the 1% fault coverage caot be reached by a pure pseudoradom test sequece for all cores; ad third, we update the test sequece by fidig the quasi-optimal time momet for switchig from parallel pseudoradom testig to parallel determiistic testig at the give memory costrait.

3 Fidig the iitial state for the LFSR. To fid the best iitial state for the parallel pseudoradom test geerator, we carry out m experimets, with radomly chose iitial states, for all cores. Withi each j th experimet we calculate for each core C the weighted legth LP,j * INP of the test sequece which achieves the 1% fault coverage for the core C. The, for all the experimets we calculate the average weighted legth L j = 1 = 1 LP * INP as the quality merit of pseudoradom sequeces for parallel testig of all cores. The best pseudoradom sequece is the oe that gives as shortest L j, j = 1,2,, m. Let us call this iitial pseudoradom test TP. Geeratio of the iitial determiistic test set. Suppose there are cores where 1% fault coverage caot be achieved with TP because of the practical costraits to the pseudoradom. Let us deote this subset of cores with S S. Let us deote with FP i fault coverage of the core C i, achieved by TP. Let us order the cores i S as C 1, C 2,, C, so that for each i < j, 1 i,j, we have FP i FP j. We assume here that every determiistic test patter, to be propagated to the system, has to be as wide as the maximum width of the TAM. If the core uder test has less iputs tha the width of the TAM, all uused bits i the TAM are filled with pseudoradom data. The determiistic patters ca be geerated by usig the followig algorithm: Algorithm Start with core C i i S, i=1. 2. Geerate a determiistic test set TD i to complemet the TP to icrease the fault coverage FP i of the core C i to 1%. 3. Fill the uused bits of TD i with pseudoradom data by cotiuig the pseudoradom test TP. Deote this updated test by TD i. 4. Broadcast the test TD i for other cores i S, fault simulate it for the cores i S, ad update the fault coverage FP j for other cores i S. 5. Tae the ext core C i i S for i = i If i >, END. 7. If FP i = 1%, repeat Step 5, else go to Step 2. By usig Algorithm 1 a iitial hybrid BIST sequece TH = {TP, TD } ca be geerated. This sequece guaratees 1% fault coverage for all cores i the system. Defiitio 1: A patter i a joit pseudoradom test sequece is called efficiet if it detects at least oe ew fault for at least oe core that is ot detected by previous, j test patters i the sequece or by ay patter i the determiistic test sequece. Optimizatio of the test sequece. After the previous 2 steps we have obtaied a hybrid BIST sequece TH = {TP, TD } with legth LH, cosistig of the pseudoradom part TP with legth LP, ad of the determiistic part TD with legth LD. I special case TD may be a empty set. Let us deote with COST M (TD ) the memory cost of the determiistic test set TD. We assume that the memory costraits are at this momet satisfied: COST M (TD ) < COST M,LIMIT. I a opposite case, if COST M (TD ) > COST M,LIMIT, the legth of the pseudoradom sequece has to be exteded ad the secod step of the procedure has to be repeated. If COST M (TD ) = COST M,LIMIT the third step is uecessary, ad the procedure is fiished. Uder optimizatio of TH we mea the miimizatio of the LH at the give memory costraits COST M,LIMIT. It is possible to miimize LH by shorteig the pseudoradom sequece, i.e. by movig step-by-step efficiet patters from the begiig of TP to TD ad by removig all other patters betwee the efficiet oes from TP, util the memory costraits will become violated, COST M (TD ) > COST M,LIMIT. We caot remove patters with the same goal from the other ed of TP because the pseudoradom sequece will be exteded ad merged with the determiistic part TD to update the free bits of determiistic test patters geerated by Algorithm 1. I other words, by removig pseudoradom patters from the ed of the TP would brae the cotiuity of the pseudoradom test geeratio process o the border betwee TP ad TD. To fid the efficiet test patters i the begiig of the TP we have to fault simulate the whole test sequece TH for all the cores i the opposite way from the ed to the begiig. As a result of the fault simulatio we get for each patter the icremets of fault coverage i relatio to each core = { 1, 2,,,}. Accordig to Defiitio 1, we call the patter efficiet if, = 1,2,..., : The optimizatio procedure will be carried out by usig the followig algorithm. Algorithm Start with the first patter P i from the begiig of TP, i = If P i is efficiet, move it from TP to TD. 3. Recalculate the memory cost COST M (TD ) = COST M (TD ) + COST M (P i ).

4 4. If COST M (TD ) < COST M,LIMIT go to Step 5, else if COST M (TD ) > COST M,LIMIT go to Step 7, else go to Step Tae the ext patter P i i TP, i = i If P i is ot efficiet, remove it from TP, ad go to Step 5; else go to Step Remove P i from TD bac to TP. Go to Tae the ext patter P i i TP, i = i If P i is ot efficiet, remove it from TP, ad go to Step END: tae P i as the ew begiig of the pseudoradom test sequece TP. As the result of the Algorithm 2 we create a ew hybrid BIST sequece TH = {TP,TD} with total legth LH ad with legths LP LP ad LD LD for the ew pseudoradom ad determiistic parts correspodigly. Due to removal of all o-efficiet patters LP - LP >>LD LD. Hece, the total legth of the ew hybrid BIST sequece will be cosiderably shorter compared to its iitial legth, LH < LH. The memory costraits, accordig to the Algorithm 2, remai satisfied: COST M (TD) < COST M,LIMIT. The described procedure does t guaratee absolute miimum of the, however, the procedure is rather straightforward (similar to the greedy algorithm) ad fast ad therefore suitable for use i the desig process. The method ca be used to fid a cheap practical solutio as well as for a fast referece for compariso with more sophisticated optimizatio algorithms to be developed i the future. 4. Experimetal data We have performed experimets with three systems composed from differet ISCAS bechmars as cores. The data of these systems are preseted i Table 1 (the lists of used cores i each system) To show the importace of the first step of the procedure, i.e. the sigificace of the quality of the iitial state of the LFSR, a compariso of the best ad worst iitial states of the LFSR for all 3 experimetal systems has bee carried out. The legths of a complete pseudoradom test sequece (1% fault coverage), startig from the best ad worst iitial state, are depicted i Table 2. I case of system S3 the pseudoradom sequece was uacceptably log. Therefore the pseudoradom test geeratio was iterrupted ad a iitial set of determiistic test patters was geerated i order to achieve 1% fault coverage. System Name System ame List of used cores The best iitial state for the pseudoradom test S1 6 cores S2 7 cores S3 5 cores c5315 c432 c88 c88 c499 c5315 c432 c88 c354 c499 c1355 c198 c499 c198 c88 c5315 c5315 c6288 Table 1. Systems used for experimets The worst iitial state for the pseudoradom test S S S Table 2. Quality of differet pseudoradom sequeces The experimetal results for three differet systems are preseted i Table 3. The legths of the pseudoradom test sequece, the umber of additioal determiistic test patters ad the total legth of the hybrid test sequece is calculated for three differet memory costraits ad for System Name Number of cores Memory Costrait (bits) The best iitial state for the pseudoradom test Total test legth CPU time (sec) The worst iitial state for the pseudoradom test Total test legth CPU time (sec) S , S S , Table 3. Experimetal results

5 the best ad worst iitial states of the LFSR for all 3 systems. The CPU time eeded for the aalysis is preseted as well. For the first two systems S1 ad S2 the cost of the procedure is determied oly by the CPU time for the pseudoradom test patter geeratio ad by subsequet simulatio of the test patters for all cores i the system. For the third system S3 the CPU time icludes also the time eeded to geerate the additioal determiistic test patters. The full overview about the all possible hybrid BIST solutios for the three systems is preseted i Figure 2 represetig the memory cost as the fuctio of the total. Based o these curves for a arbitrary memory costrait the correspodig total testig time ca be foud. The three costraits preseted i Table 3 are also highlighted i Figure 2. It ca be see that the memory cost will icrease very fast whe reducig the legth of the test sequece. It ca be explaied by the fact that i the begiig of the pseudoradom sequece early all test patters are efficiet, ad early each patter that is excluded from the pseudoradom part should be icluded ito the determiistic part. Memory Total Figure 2. Memory usage as the fuctio of the total for all three systems A compariso of the curves of the memory cost as the fuctio of the total for the best ad for the worst iitial pseudoradom sequeces is depicted for the system S2 i Figure 3. This illustrates the importace of choosig best possible pseudoradom sequece for testig the system. S1 S2 S3 Memory Total The best The worst Figure 3. Memory usage as the fuctio of the total for the best ad the worst iitial pseudoradom sequeces 5. Coclusios We have preseted a ew approach for the hybrid BIST i multi-core systems where the hybrid BIST idea is exteded with the cocept of test patter broadcastig, where the determiistic test set of each core is applied i parallel to all other cores i a similar way as the pseudoradom test patters. For this ew architecture we have formulated the tas to miimize the total test time of the hybrid BIST at give memory limitatios for storig determiistic test patters. We have proposed a straightforward algorithm for calculatig a possible combiatio betwee pseudoradom ad determiistic test sequeces, where we eglect the optimal solutios for idividual cores i favour of fidig a ear-optimal solutio for the whole system. The described procedure does t guaratee miimal, however, the procedure is simple (similar to the greedy algorithm) ad fast. The latter is demostrated also by correspodig experimetal results. We have also aalyzed the impact of pseudoradom test quality for the overall test solutio ad the result was illustrated with the experimetal results as well. Although the curret wor covers oly combiatorial circuits, it ca easily be exteded also for full-sca sequetial circuits ad ca be cosidered as a future wor. The method proposed ca be used first, as a cheap practical solutio, ad secod, as a quicly computable referece for compariso with more sophisticated optimizatio algorithms to be developed i future. Refereces [1] G. Jerva, Z. Peg, R. Ubar, Test Cost Miimizatio for Hybrid BIST, IEEE It. Symp. o Defect ad Fault Tolerace i VLSI Systems (DFT ), pp , Yamaashi, Japa, October 2. [2] G. Jerva, P. Eles, Z. Peg, R. Ubar, M. Jeihhi, Test Time Miimizatio for Hybrid BIST of Core-Based Systems, IEEE Asia Test Symposium 23 (ATS 3), Xia, Chia, November 23 (accepted for publicatio).

6 [3] Y. Zoria, A distributed BIST cotrol scheme for complex VLSI devices, Proceedigs of the IEEE VLSI Test Symposium (VTS), pp. 4-9, Atlatic City, NJ, April [4] R. Chou, K. Saluja, ad V. Agrawal, Schedulig Tests for VLSI Systems Uder Power Costraits, IEEE Trasactios o VLSI Systems, Vol. 5, No. 2, pp , Jue [5] M. Sugihara, H. Date, H. Yasuura, Aalysis ad Miimizatio of Test Time i a Combied BIST ad Exteral Test Approach, Desig, Automatio & Test I Europe Coferece (DATE 2), pp , Paris, Frace, March 2. [6] K. Charabarty, Test Schedulig for Core-Based Systems Usig Mixed-Iteger Liear Programmig, IEEE Trasactios o Computer-Aided Desig of Itegrated Circuits ad Systems, Vol. 19, No. 1, pp , October 2. [7] V. Iyegar, K. Charabarty, E. J. Mariisse, Test Wrapper ad Test Access Mechaism Co-Optimizatio for System-o-chip, Joural of Electroic Testig; Theory ad Applicatios (JETTA), Vol. 18, o. 2, pp , April 22. [8] E. Larsso, Z. Peg, A Itegrated Framewor for the Desig ad Optimizatio of SOC Test Solutios, Joural of Electroic Testig; Theory ad Applicatios (JETTA), for the Special Issue o Plug-ad-Play Test Automatio for System-o-a-Chip, Vol. 18, o. 4/5, pp , August 22. [9] G. Jerva, Z. Peg, R. Ubar, H. Kruus, A Hybrid BIST Architecture ad its Optimizatio for SoC Testig, IEEE 22 3rd Iteratioal Symposium o Quality Electroic Desig (ISQED'2), pp , Sa Jose, CA, March 22. [1] G. Jerva, P. Eles, Z. Peg, R. Ubar, M. Jeihhi, Hybrid BIST Time Miimizatio for Core-Based Systems with STUMPS Architecture, IEEE It. Symposium o Defect ad Fault Tolerace i VLSI Systems (DFTS'3), pp , Cambridge, Mass, USA, November 23. [11] R. Ubar, M. Jeihhi, G. Jerva, Z. Peg, Test Time Miimizatio for Hybrid BIST with Test Patter Broadcastig, 21 th Norchip Coferece, Riga, Latvia, November 23 (accepted for publicatio).