FPGA Implementation of the Ternary Pulse Compression Sequences

Transcription

1 FPGA Implemetatio of the Terary Pulse Compressio Sequeces N.Balaji 1, M. Sriivasa rao, K.Subba Rao 3, S.P.Sigh 4 ad N. Madhusudhaa Reddy 4 Abstract Terary codes have bee widely used i radar ad commuicatio areas, but the sythesis of terary codes with good merit factor is a oliear multivariable optimizatio problem, which is usually difficult to tackle. To get the solutio of above problem may global optimizatio algorithms like geetic algorithm, simulated aealig, ad tuelig algorithm were reported i the literature. However, there is o guaratee to get global optimum poit. I this paper, a ovel ad efficiet VLSI architecture is proposed to desig Terary Pulse compressio sequeces with good Merit factor. The VLSI architecture is implemeted o the Field Programmable Gate Array (FPGA) as it provides the flexibility of recofigurability ad reprogramability. The implemeted architecture overcomes the drawbacks of o guarateed covergece of the earlier optimizatio algorithms. Idex Terms Pulse compressio, Terary sequece, VLSI architecture, Sidelobe eergy, FPGA I. INTRODUCTION Pulse compressio codes with low autocorrelatio sidelobe levels ad high merit factor are useful for radar [1], chael estimatio, ad spread spectrum commuicatio applicatios. Pulse compressio ca be defied as a techique that allows the radar to utilize a log pulse to achieve large radiated eergy but simultaeously obtaiig the rage- resolutio of a short pulse. Theoretically, i pulse compressio, the code is modulated oto the pulsed waveform durig trasmissio. At the receiver, the code is used to combie the sigal to achieve a high rage resolutio. Rage-resolutio is the ability of the radar receiver to idetify ear by targets. The mai criterio of good pulse compressio is the Meritfactor ad discrimiatio. Merit factor is used to measure whether coded sigal is a good or poor. This Mauscript received December 30, 007. N.Balaji is with the Electroics ad commuicatio Egieerig Departmet, VNR Vigaa Jyothi Istitute of Egg. & Tech., Hyderabad, Idia (phoe: ; fax: ; arayaamb@rediffmail.com). M.sriivasa Rao is with the Electroics ad commuicatio Egieerig Departmet, VNR Vigaa Jyothi Istitute of Egg. & Tech., Hyderabad, Idia (phoe: ; fax: ; srmuduuru@yahoo.com). Dr. K.Subba Rao is with the Electroics ad commuicatio Egieerig Departmet, Uiversity College of Egg., Osmaia Uiversity, Hyderabad, Idia ( kakarlasubbarao@yahoo.com). meas that a code with high Merit factor is a good code while a code with low Merit factor is a poor code. Let S = [x 0,x 1, x, x 3..x N-1 ] (1) be a real sequece of legth N. The aperiodic autocorrelatio fuctio (ACF) of sequece S of legth N is give as, N - k-1 s s ; 0 k N -1 A( k) = = 0 N+ k-1 s = 0 + k s -k ; - N + 1 k 0 II. MERIT FACTOR (MF) Golay defied the merit factor (MF) as the ratio of mailobe eergy to sidelobes eergy of Autocorrelatio (AC) fuctio of sequece S. The MF mathematically is defied as: A(0) MF = (3) N-1 A(k) k 0 The deomiator term represets the eergy i the sidelobes. The merit factor MF must be as large as possible for good sequece. III. NON BINARY PULSE COMPRESSION CODES. A. Polyphase Code Waveforms cosistig more tha two phases are called polyphase codes. The phase of sub pulse alterate amog multiple values rather tha 0 0 ad The sequece ca be writte as () i( 1) φ = π (4) p Where p is the umber of phases, = 0, 1,...p -1 ad i= modulo p B. Terary Code Terary Code is the code that ca be used to represet iformatio ad data. However terary code uses 3 digits for represetatio of data. Therefore terary code may

2 also be called as 3-alphabet code. This code cosists of 1, 0, ad -1. IV. Need for the Proposed Architecture The problem of obtaiig log sequeces with peaky autocorrelatio [] has log bee a importat problem i the field of radar, soar ad system idetificatio. It is viewed as the problem of optimizatio [3-4]. The sigal desig problem for radar applicatio is suggested by sequeces like biary, Polyphase, terary ad quequeary sequeces. There has bee extesive work o terary sequeces for obtaiig good Meritfactor values [5-9]. This work was based o global optimizatio techiques such as geetic algorithm, eugeic algorithm ad SKH (Simo-Kroecker-Hammig) algorithm. But all these optimizatio algorithms have serious drawbacks of o guarateed covergece, slow covergece rate ad require large umber of evaluatios of the objective fuctio. The Hardware Implemetatio architectures for Pulse compressio sigal processig systems available i the literature have the capability of oly the geeratio of pulse compressio sequeces with limited speed [10-11]. With a little additioal hardware, the proposed architecture ca geerate good Terary Pulse Compressio sequeces with FPGA clock rate. Hece i this paper we proposed a efficiet real time Hardware solutio for idetificatio of the Terary Pulse compressio sequeces. V. Proposed Architecture As the mai lobe eergy r (0) of a give Terary sequece of legth N is N from equatio 3, for the merit factor calculatio of a Terary sequece, we eed to calculate the side lobe eergy of a Terary sequece. Sice Meritfactor is the mai criterio for good pulse compressio sequeces, therefore the Terary sequece havig miimum sidelobe eergy ca be cosidered as the best Terary Pulse compressio sequece. The proposed VLSI architecture for idetificatio of the good terary pulse compressio is show i the Fig (1). This architecture geerates 3 N Terary sequeces of legth N. For all these 3 N sequeces it calculates the sidelobe eergy values, idetifies ad holds the sequece with miimum sidelobe eergy. The sequece geerator is a sychroous couter of legth N which geerates 3 N sequeces with 0 s ad 1 s. These geerated sequeces are modified with the help of the sig coversio uit to get the Terary Pulse Compressio sequece elemets. As the terary sequece cosists of 0, +1 ad -1, the sig coversio uit coverts the bit 1 to 01, 0 to 00 ad -1 to 11. The remaiig hardware blocks are useful for computig, idetifyig ad holdig the lowest side lobe eergy value of a Terary pulse compressio sequece. The output register of figure 1 holds the good terary pulse compressio sequece. This sequece is represeted by +1 s, -1 s ad 0 s. To covert this represetatio of the sequece to pure terary sequeces of 0, +1 ad -1 we eed to iterface a little additioal hardware to FPGA. For lower sequece legth the proposed architecture geerate all the 3 N sequeces, idetifies ad holds the best terary sequece amog the N sequeces. I order to reduce the computig time ad complexity for larger sequeces of legth N, the sequece geerator of Fig(1) ca be modified to geerate k bits dyamically ad remaiig (N-k) bits will be the fixed bits which ca be take from a already idetified best sequece of legth (N-k). VI. Techology, tools ad Results The architecture show i figure 1 has bee authored i VHDL for 16-bit ad 3-bit Terary Pulse compressio sequeces ad its sythesis was doe with Xilix XST. Xilix ISE Foudatio 9.1i has bee used for performig mappig, placig ad routig. For Behavioral simulatio ad Place ad route simulatio Modelsim6.0 has bee used. The Sythesis tool was cofigured to optimize for area ad high effort cosideratios. The targeted device was Sparta-3 xa3s1500fgg676-4 with detailed specificatios at [1]. The good 3-bit ad 31-bit Terary Pulse compressio sequeces implemetatio reports preseted i figure ad figure3 respectively. From the device utilizatio Summary the same Sparta-3 FPGA is useful for the implemetatio of higher legths of the Terary Pulse Compressio sequece. The behavioral simulatio waveforms for the good 3-bit terary Pulse compressio sequece are show i figure 4. The behavioral simulatio waveforms for the good 31-bit terary Pulse compressio sequece are show i figure 5. From figure 4 it ca be see that terary sequece based o the lowest sidelobe eergy is ( ) ad its sidelobe eergy is 18. Therefore meritfactor of this sequece is From figure 5 it is see that Terary sequece based o the lowest sidelobe eergy is ( ) ad its sidelobe eergy is 30. Therefore meritfactor of this sequece is

3 Figure 1. VLSI architecture for the idetificatio of good Terary pulse compressio sequece. Desig Summary: Number of errors: 0 Logic Utilizatio: Total Number Slice Registers: 869 out of 66,560 1% Number used as Flip Flops: 80 Number used as Latches: 589 Number of 4 iput LUTs: 1,711 out of 66,560 % Logic Distributio: Number of occupied Slices: 1,453 out of 33,80 4% Number of Slices cotaiig oly related logic: 1,453 out of 1, % Number of Slices cotaiig urelated logic: 0 out of 1,453 0% Total Number of 4 iput LUTs: 1,85 out of 66,560 % Number used as logic: 1,711 Number used as a route-thru: 114 Number of boded IOBs: 66 out of 784 8% IOB Latches: 51 Number of MULT18X18s: out of 104 1% Number of GCLKs: 3 out of 8 37% Total equivalet gate cout for desig: 107,015 Additioal JTAG gate cout for IOBs: 3,168 Timig Summary: Miimum period: 5.44s (Maximum Frequecy: MHz) Maximum output required time after clock: 6.141s Figure : Desig Implemetatio summary of the good 3-bit legth Terary Pulse Compressio sequece.

4 Desig Summary: Number of errors: 0 Logic Utilizatio: Total Number Slice Registers: 1,164 out of 66,560 1% Number used as Flip Flops: 378 Number used as Latches: 786 Number of 4 iput LUTs:,415 out of 66,560 3% Logic Distributio: Number of occupied Slices:,17 out of 33,80 6% Number of Slices cotaiig oly related logic:,17 out of,17 100% Number of Slices cotaiig urelated logic: 0 out of,17 0% Total Number of 4 iput LUTs:,677 out of 66,560 4% Number used as logic:,415 Number used as a route-thru: 6 Number of boded IOBs: 8 out of % IOB Latches: 53 Number of MULT18X18s: 30 out of 104 8% Number of GCLKs: 3 out of 8 37% Total equivalet gate cout for desig: 147,68 Additioal JTAG gate cout for IOBs: 3,936 Timig Summary: Miimum period: Maximum output required time after clock: 5.44s (Maximum Frequecy: MHz) 6.141s Figure 3: Desig Implemetatio summary of the good 31-bit legth Terary Pulse Compressio sequece. Figure 4: Behavioral simulatio result of a good 3-bit Terary Pulse compressio sequece. Figure 5: Behavioral simulatio result of a good 31-bit Terary Pulse compressio sequece.

5 VII. CONCLUSION I this paper we have proposed ad implemeted a efficiet VLSI architecture for the idetificatio of the good Terary Pulse Compressio sequeces based o Meritfactor. The architecture implemeted overcomes the drawbacks of o guarateed covergece ad slow covergece rate of the earlier optimizatio algorithmic based approaches for idetifyig the good terary pulse compressio sequeces. From the above results it is clear that this architecture is givig better meritfactor of for a 31-bit sequece legth tha the algorithmic based approach claimed i [8]. It was also observed that the proposed architecture is givig good meritfactor values for higher legths. This shows the superiority of the architecture. ACKNOWLEDGMENT The authors are thakful to Dr.C.D.Naidu, Dr.P.Sudhakara Rao Professors of ECE Departmet of VNR VJIET for their costat techical support ad ecouragemet. The authors are also thakful to the maagemet of their respective orgaizatios. REFERENCES [1] Golay M J E, Sieves for low autocorrelatio biary sequeces, IEEE Tras. If. Theory,1977 IT-3:43-51 [] Barker R H, Group sychroizatio of biary digital systems, I Commuicatio theory (ed.) W Jackso (Lodo: Butterworths),1953. [3] Berascoi J 1987, Low autocorrelatio biary sequeces: statistical mechaics ad cofiguratio space aalysis, J. Phys. 48: [4] De Groot C, Wurtz D, Hoffma K H 199 Low autocorrelatio biary sequeces: exact eumeratio ad optimizatio by evolutioary strategies Optimizatio 3: [5] Mohrir, P.S.: Terary Barker Codes, Electro.Lett., 1974, 10, (), pp [6] Mohrir, P.S.: Sigal desig (sequeces with prescribed autocorrelatio), It. J. Electro., 1976, 41, (4), pp [7] Moharir, P.s., Varma S.k., ad VekatRao, K: Terary Pulse Compressio sequeces, J.IETE, 1985, 31, (), pp [8] Sigh,R, Mohrir, P.S., ad Maru, V.M: Eugeic Algorithm-based search for terary Pulse compressio Sequeces, J.IETE,1996,4, (1), pp [9] Moharir P S, Maru V M, Sigh R, S-K-H algorithm for sigal desig, Electro. Lett : [10] Day R., Germo R., O'Neill B., A Pulse compressio Radar Sigal Processor, IEE Colloquim o DSP Chip's i Real Time Istrumetatio ad Display Systems, /1-4/5 [11] Day, R.H. Germo, R. O'Neill, B.C, A real time digital sigal processig solutio for radar pulse compressio,iee Colloquium o Digital Filters: A Eablig Techology,1998 6/1-6/5 [1] Xilix, Sparta-3 Field Programmable Gate array data sheets (