A Comparative Study on LUT and Accumulator Radix-4 Based Multichannel RNS FIR Filter Architectures

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1 A Comparative Study o LUT ad Accumulator Radix-4 Based Multichael RNS FIR Filter Architectures Britto Pari. J #, Joy Vasatha Rai S.P *2 # Research Scholar, Departmet of Electroics Egieerig, MIT campus, Aa Uiversity, Cheai, Tamil adu, Idia (Mobile: ) brittopari@yahoo.co.i Assistat Professor, Departmet of Electroics Egieerig, MIT campus, Aa Uiversity, Cheai, Tamil adu, Idia (Mobile: ) 2 joy_mit@aauiv.edu * Abstract - I this paper, a comparative study of two architectures proposed for multichael recofigurable FIR filter are performed i terms of complexity ad speed. The proposed architectures, viz, dual port memory based LUT multiplier ad accumulator based radix-4 multiplier architectures, are desiged to reduce the complexity ad to improve the speed of operatio of multiplier used i multichael recofigurable FIR filter. Both the architectures accepts residues of give biary iput i which the 3-bit biary iput is coverted ito three residues usig biary to Residue Number System (RNS) coverter, ad the processed i three FIR sub filters costructed i direct form. The recofigurable structure is achieved by combiig Power of Two (PoT) FIR sub modules ad alterig the filter taps based o select sigals. The proposed desigs ca be realized up to 2-taps ad has bee tested for 4, 8, 6 ad 2 taps. The architectures have bee realized i Verilog HDL ad sythesized usig Altera FPGA device Stratix II EP2S5F672C5. The performace compariso of two architectures shows that dual port memory based LUT multiplier architecture sigificatly reduces the area by 2% ad accumulator based Radix-4 multiplier icreases the speed by 9% regardless of the umber of taps. Keywords: Multichael FIR filter, Residue umber system, Look-up Table, Recofigurable Architecture, Power of Two. I. INTRODUCTION Large samplig array size is feasible with the advacemet of recet DSP techology, ad ca be used i variety of applicatios such as commuicatio ad multimedia i which the iformatio from sigle chael may be erroeous. So multichael sigal processig is essetial as far as reliability ad efficiet processig of those sigals are cocered. The sampled multichael data are processed i FIR filter through time multiplexed mechaism to achieve resource optimizatio []. With the advet of software defied radio (SDR), the research has bee cocetrated o recofigurable realizatio of FIR filters [2][3] maily due to the eed of high flexibility ad low complexity[4][5][6][7]. The digit-based recofigurable architecture preseted i [3] provides a flexible ad low power solutio with a wide rage of precisio ad tap legth of FIR filters. Covetioally, the recofigurable FIR filters are desiged based o programmable multiply-accumulate (MAC) architecture [6], systolic architecture [7] ad Programmable Shift Method (PSM) [5]. The performaces of the desigs are aalyzed i terms of hardware complexity, power cosumptio ad throughput. The programmable MAC architectures [6] cosume low power with reduced supply voltage ad it requires large area. Eve though systolic based architecture reduces the complexity, it icreases the latecy whe the order of the filter icreases. [7] The PSM based recofigurable architecture achieves less complexity ad sigificat speed due to the presece of programmable shifters [5]. Although the researchers addressed the problem of reducig the hardware complexity ad low power, speed of operatio is vital while desigig the chael filters i SDR. Sice the filter has to be operated at high samplig frequecy i frot ed of SDR to meet the speed costrait, the PSM based recofigurable architecture is ot a sigificat method i the desig of chael filters i SDR. The speed of operatio ad parallelism of digital filters is improved whe RNS umber system is used [8][9]. RNS umber system requires coversio from biary umber to residue umbers usig a set of moduli. This leads to efficiet implemetatio of arithmetic operatios i which the carry propagatio is miimized by decomposig those operatios ito smaller oes. Several researchers [][][2] have attempted to implemet the RNS based digital filters. The -bit or 2-bit adder based implemetatios [3] for residue coverters chages the moduli sets used i ROM based approach [4]. The adder based implemetatio helps i achievig improvemet both i area ad speed. ISSN : Vol 6 No 2 Apr-May

2 The direct implemetatio of N-tap FIR filter requires N MAC operatios, which are expesive to implemet i hardware due to its logic complexity ad area requiremet. Memory based structures are well-suited for the implemetatio of may digital sigal processig (DSP) algorithms, which ivolve multiplicatio with a fixed set of coefficiets. There are two basic variats of memory based techiques. Oe of them is based o distributed arithmetic (DA) for ier- product computatio ad the other is based o the computatio of multiplicatio by look-up-table (LUT). I the LUT-multiplier-based approach [4], multiplicatios of iput values with a fixed co-efficiets are performed by a LUT cosistig of all possible pre-computed product values correspodig to all possible values of iput while i the DA based approach, LUT is used to store all possible values of ier-products of a fixed N poit bit-vector. If the ier-products are implemeted i a straightforward way, the memory-size of LUT multiplier based implemetatio icreases expoetially with the wordlegth of iput values, while that of the DA based approach icreases expoetially with the ier-productlegth. Attempts have bee made to reduce the memory space i DA-based architectures usig offset biary codig (OBC) ad group distributed techique [7].A decompositio scheme [6] is oe of the techiques used for reducig the memory size of DA based implemetatio of FIR filter. But, it is observed that the reductio of memory size achieved by such decompositios is accompaied by the icrease i latecy as well as the icrease i the umber of adders ad latches. I this paper proposed two ew multichael FIR filter architectures wherei the speed of operatio icreases or complexity of hardware reduces. Hardware complexity is reduced by maipulatig the odd multiples of the fixed coefficiet i the LUT desig[4], whereas the speed of operatio is icreased by reducig the partial products required for accumulator based radix-4 multiplier[8]. I the proposed architectures, a multichael FIR filter is implemeted through time divisio multiplexig mechaism with the help of two differet architectures such as accumulator based radix-4 multiplier ad dual port memory based LUT multiplier ad their performaces are aalyzed. The use of time divisio multiplexig mechaism eables to optimize the resources utilized. The iputs are i residue format ad coefficiets are i fixed poit biary represetatio. The three residues are processed i the FIR sub filters which are implemeted usig proposed architectures, where the umber of taps ca be programmable The performaces of the proposed architectures are aalyzed with recofiguratio i terms of area ad speed by varyig the umber of taps. The rest of the paper is orgaized as follows. I Sectio II, prelimiaries about RNS umber system, radix multiplier ad LUT multiplier are described. Sectio III describes the details of architecture desig ad tells how recofiguratio based multichael FIR filter is implemeted. The performace of the desigs is aalyzed ad discussed i Sectio IV. Fially, Sectio V cocludes the paper i brief. II. PRELIMINARIES This sectio provides brief techical backgrouds o RNS umber system, accumulator based radix-4 multiplier ad LUT based multiplier which is backgroud for the proposed architectures. A. Residue Number System The process of carry propagatio is elimiated by decompositio of a iteger ito smaller parts (residues) thereby performig parallel idepedet operatios. This method of decompositio is kow as Residue Number System.(RNS) The residue umber system [8] always has a set of relative prime umbers {m, m 2,... m r }. Let X be a ordered set of residues {x, x 2, x r },where x i = X mod m i. The iteger should be i the dyamic rage {, M}, where M is the product of relative prime umbers i moduli set. I residue arithmetic [9][2][8][9], the choice of moduli sets ad the coversio of residue to biary umbers are importat issues. The residue umber system used i our work is based o the set of moduli (2 -, 2, 2 +)[9]. This allows the process of residue additio usig biary adder. By splittig 3-bit biary iput iteger ito three equal sized parts ad the performig modulo additio, the coversio of biary to RNS is obtaied. The three residues, (2 -).(2 ).(2 +) are -bit biary itegers except for the residue correspodig to modulo 2 + which is a (+)- bit iteger. The 3-bit biary represetatio of X is X = X... X X... X X... X k 2 k k The RNS represetatio of X ca be calculated through modulo arithmetic operatios. Hece the three residues ca be writte as x p + k = 2 x 2 = k ISSN : Vol 6 No 2 Apr-May

3 3 = p2 k 2 + x () where = k2 + k 2 p ad p 2 = k2 + k 2 + The RNS to biary coverter geerates the 3-bit biary iteger output from the FIR sub-filters output residues y, y 2, ad y 3 that ca be implemeted usig ROM-less adder based coverter as described i [3].The equatios eeded for RNS to biary coversio are give below Z = y Y where Y A B = A= (( y + ( y y ).2 ) + (2 y ) + (2 )) / B = (( y + ( y y ).2 ) + y + 2(2 y )) / 2 where y ad y 3 are the least sigificat bits of y ad y3 respectively. B. Accumulator Based Radix-4 Multiplier Parallelism is ehaced usig high speed multipliers which i tur reduce the umber of subsequet stages. The speed of the operatio is icreased by usig Booth s bit pair recodig algorithm by reducig the umber of partial products. The origial versio of Booth algorithm (Radix-2) for -bit umbers has umber of partial products, whereas i Booth s bit pair recodig algorithm (radix-4) partial products are reduced as /2 for -bit umbers. This algorithm recodes the pair of three bits of the multiplier ad geerates the partial products simultaeously. Thus there is a reductio i the total umber of partial products. I this work, accumulator based radix-4 multiplier is used ad it geerates the umber of partial products as /2 for (x)-bit multiplicatio. The partial products are shifted ad accumulated usig carry lookahead adder (CLA) that accumulates partial products. Hece, it is cocluded that by reducig the partial products with the help of accumulator based radix-4 multiplier the speed of the operatio is icreased. The multiply ad accumulate (MAC) architecture executes the multiplicatio operatio ad accumulates the result for every clock cycle. The iputs of MAC are oe of the three residues obtaied from biary to RNS coverter ad the filter coefficiet represeted i fixed poit biary. The architecture of accumulator based radix-4 multiplier is show i Fig.. (2) Fig. Block diagram of accumulator based radix-4 multiplier ISSN : Vol 6 No 2 Apr-May

4 C. Dual port Memory based LUT Multiplier Let X be a iput which is multiplied with fixed coefficiet H. If the legth of X is assumed to be a usiged biary umber L, 2 L values of X is possible, ad hece, the product P= (H. X) cotais 2 L possible values. Therefore, the LUT cosistig of pre-computed product values correspodig to all possible values of X requires a memory uit of 2 L words for the covetioal implemetatio of memory-based multiplicatio. The dual port memory based LUT multiplier proposed i [4] shows that it is eough to store oly (2 L/2- ) words correspodig to the odd multiples of H i the LUT. Oe of the possible product words is zero, while all the rest (2 L- ) are eve multiples of H which could be derived by left-shift operatios from of the odd multiples of H. By resettig the LUT output, address correspodig to () ca be obtaied. The cocept behid memory based multiplicatio [4] is give i Table I. This multiplier cosists of memory with the size of eight words of (w+4) bit width ad a 3-to-8 lie address decoder, a NOR-cell, a shifter, a 4-to-3 bit ecoder to map the 4-bit iput operad to 3-bit LUT-address ad a cotrol circuit for geeratig the cotrol word ad RESET sigal for the shifter ad the NOR-cell respectively. The 8-bit iput biary umber[x 7,x 6,x 5, x ] is split ito two 4-bit umbers ad these are give to two separate 4 to 3-bit the ecoder which produces three address bits [d 2 d d ] for dual port memory per the relatio d = ( x. x).( x. x2).( x + x2 + x3) (3a) d = ( x. x2).( x + ( x. x3)) (3b) d2 = x. x3 (3c) Similarly address bits [d 5 d 4 d 3 ] is geerated from x 4, x 5, x 6 ad x 7. The address bits are give to the two differet decoders that covert them ito eight word-select sigals {w i, i 7}. Hece the dual port memory ca be accessed through two ports (decoders) of eight word select sigals each. They are used to select the correspodig value from memory which is a multiple of the co-efficiet i bit-iverted form. The, cotrol circuit performs the umber of shifts o the memory output to obtai the eve multiples. Three sigals s, s ad RESET are geerated accordig to the relatio s = x + ( x + x2) (4a) s = ( x + x) (4b) RESET = ( x + x).( x2 + x3) (4c) If the iput combiatios are (), (), () ad (), the output of LUT is shifted oce. The iputs equals to () ad () requires two shifts ad the iput () requires three shifts. Whe the iput word is (), the the reset operatio is performed by settig the RESET bit as give i the logical relatio (4c). The detailed diagram of dual port memory based LUT multiplier is show i Fig.2. It is obtaied by two 4-bit multipliers alog with a shift-adder. The shift-adder left-shifts the output of the first shifter correspods to most sigificat half of iput by four bits ad adds the result to the output of the other shifter. Fig.2. Dual port Memory based LUT Multiplier ISSN : Vol 6 No 2 Apr-May

5 TABLE I LUT Iput ad Product Values for Word Legth L=4 address d 2 d d stored value iput x 3 x 2 x x product value o. of shifts cotrol s s H H 2 x H 2 2 x H x H 3 3H 3H 2 x 3H 2 2 x 3H 2 5H 7H 5H 2 x 5H 7H 2 x 7H 9H 9H H H 3H 3H 5H 5H III. MULTICHANNEL RNS BASED RECONFIGURABLE FIR FILTER A. Proposed Sigle Chael RNS based Recofigurable FIR filter As we kow that the structure of the FIR filter has the multipliers i the form of MAC structure ad delay blocks as the mai buildig blocks. The performace of the DSP algorithms etirely depeds upo multipliers i terms of critical path. Both the accumulator based radix-4 multiplier architecture which icreases the speed of the operatio ad dual port memory based LUT multiplier architecture which reduces the complexity are proposed for Sigle chael Recofigurable FIR filter. With the help of accumulator based radix-4 multiplier, the umber of partial products is reduced to /2. The 3-bit pair recodig geerates the partial product set of, ±M, ±2M, where M is the multiplicad. By meas of dual port memory based LUT multiplier, the umber of memory locatios eeded to store partial products is reduced from 2 L to 2 (L/2)-. Hece the memory size is greatly reduced as compared to covetioal LUT based multiplicatio, which leads to reductio i complexity. Let X() ad Y() be the iput ad output sequeces of the FIR filter respectively. Cosider a N-tap FIR filter that ca be formulated as Y N ( ) h X ( k) = k = k where h k is the k th coefficiet of the filter impulse respose. Subsequetly, the FIR filter is partitioed ito r sub filters, each correspods to oe residue xi for a give moduli set{m, m 2, m r }. Hece, the sub filter iput is i its residue format as give i equatio () ad is deoted as, x = X i k m i i =, 2, r (6) The output of the sub filter is calculated by the equatio (7) as, (5) ISSN : Vol 6 No 2 Apr-May

6 y N ( ) h x ( k) i = k = k i The 3-bit data X is decomposed ito set of three residues ad as i equatio(), it ca be oted that the decomposed set of residues are processed i three sub filters ad all the three filters use the same set of filter coefficiets represeted i fixed poit biary. The results of FIR sub filters i RNS form are coverted back ito biary form. The ROMless -bit adder based coverter, derived from ew CRT algorithm [3], is used for the coversio of RNS back to biary. It improves the hardware complexity ad speed sice it ca be implemeted usig fast parallel adders ad multiplexers. B. Proposed Multichael RNS based Recofigurable FIR filter I the covetioal structure of multichael FIR filter [2], show i Fig.3, dedicated filters are used for each chael. This results a icrease i the speed of processig, at the expese of icreased hardware complexity with reduced throughput. For efficiet utilizatio of hardware resources, proposed multichael recofigurable FIR filter architecture shares the logic resources betwee multiple sample streams through time divisio mechaism. So eve though the umbers of chaels icrease the logic area remais approximately costat. I this work, the iput data from multichael is trasferred based o time-multiplexed mechaism ad shares the same sigle chael recofigurable FIR filter. I multichael recofigurable FIR filter, the samplig frequecy of the FIR filter is the ratio of output of clock frequecy by the umber of clock cycles required for processig the sampled iput data at the output. For example, if the samplig frequecy for a sigle chael FIR filter is f s, a M-chael filter, process M sample streams, each with a samplig frequecy of f s /M. (7) Cosider the geeral trasfer fuctio of FIR filter, i Fig.3 Covetioal Structure of Recofigurable FIR filter Y( z) = X( z) hz (8) i k = where h, h, h 2,, h - are the filter coefficiets ad the z -i represets the delay elemets. Now the equatio (8) ca be decomposed ito Power of two sub modules i which the umber of coefficiets is the icreasig powers of two as give i equatio (9). H ( z) = h + z... + h H ( h + h z ) + z 2 ( / 2) z ) ( h + h z The sub modules ca be described as, ( 2 ) = h, ( 2 ) 2 H h hz + h z 2 5 = +, ( 2 ) + h z 3 6 ) z ( / 2) ( h / h z + / 2 H = h + hz + hz + hz ad so o. For N-tap FIR filter with umber of Coefficiet the equatio (9) ca be writte as, + (9) ISSN : Vol 6 No 2 Apr-May 24 74

7 H ( z) = H (2 ) + H (2 ) z 2 + H (2 ) z H (2 ) z H (2 ) z H (2 m ) z m (2 ) where N=2 m+ - taps, for m=,,2,3 It ca be cocluded from equatio () that for ay N-tap filter, the sub modules ca be combied with respective delay elemets. The recofigurable FIR filter structure is implemeted i the proposed multichael m FIR filter structure as show i Fig.4. Here the selectio of filter tap is based o the ecoder output from 2 outputs by the m select lies. This system provides flexibility by way of selectig the umber of taps for the required applicatio. () Fig.4 Multichael Recofigurable FIR sub-filter IV. RESULTS AND DISCUSSION The proposed architectures are desiged by parameterizable Verilog cores. A key advatage of hardware descriptio laguages (HDLs) is that all the statemets are executed i cocurret maer. The performaces of both sigle chael ad multichael recofigurable architectures were sythesized o the FPGA device Altera Stratix II EP2S5F672C5. A. Sigle chael RNS based Recofigurable FIR filter The proposed Recofigurable RNS based FIR Filter architectures are implemeted usig two methods: (i) accumulator based radix-4 multiplier ad (ii) Dual port Memory based LUT Multiplier, ad sythesized usig Altera FPGA device Stratix II EP2S5F672C5. The performace results of RNS FIR filter architectures are aalyzed i Table II. From RNS based FIR filter structures, it ca be observed that the icrease i the umber of taps liearly icreases delay ad reduces the frequecy. While comparig the performace results, it is foud that the speed of the operatio is icreased i accumulator based Radix-4 multiplier by reducig the partial products ad parallelism of RNS structure, but low complexity was achieved usig New LUT multiplier based implemetatio, because the memory size is reduced to early half of the covetioal LUT based multiplicatio. For a 4-tap recofigurable FIR filter, H(z) is split ito H(2 ), H(2 ) ad H(2 2 ) accordig to equatio() as a sub module for variable tap implemetatio from tap to 4. Similarly 8-tap ca be split ito H(2 ), H(2 ),H(2 2 ) ad H(2 3 ). I the same way 6-tap ad 2-tap recofigurable FIR filter are implemeted. ISSN : Vol 6 No 2 Apr-May 24 74

8 TABLE II Performace results of RNS based sigle chael FIR filter usig Altera Stratix II EP2S5F672C5 Performace measures Dual port Memory based LUT ACC-Radix4 No of taps 4-tap 8-tap 6-tap 2-tap 4-tap 8-tap 6-tap 2-tap No of iput bits No of Logic Elemets Delay(s) Frequecy(MHz) TABLE III Compariso of proposed recofigurable RNS filter with other architectures No. of taps Pramodkumar [7] Frequecy[MHz]* Yoo et al [6] Frequecy[MHz] * Dual port Memory based LUT Multiplier Frequecy[MHz] * ACC-RADIX-4 Frequecy[MHz] * * Note: Device used: Xilix Virtex-E XCV2E Table III compares the sythesis results of the 8 tap ad 6 tap recofigurable RNS based architectures with existig architectures proposed i [6] ad [7] sythesized usig the FPGA device Xilix Virtex-E XCV2E. Both the proposed architectures provide highest frequecy of operatio compared to the existig architectures. Hece it ca be oted that the proposed recofigurable RNS based architectures achieves high speed due to the parallelism of RNS. A. Multichael RNS based Recofigurable FIR Filter Time divisio multiplexed multichael recofigurable FIR filter is sythesized usig the FPGA device, Altera Stratix II EP2S5f672C5 ad the performaces are aalyzed i Table IV. Due to Time Divisio Multiplexig (TDM), logic resources are optimized. The proposed multichael RNS based recofigurable FIR filter results are also compared with the proposed sigle chael RNS based recofigurable FIR filters, usig Cadece RC compiler with.8µm CMOS techology as give i Table V. From Table IV ad Table V, it is see that TDM multichael RNS FIR filter implemetatio is highly efficiet i the utilizatio of logic resources, further it ca be cocluded that area is almost idepedet of the umber of chaels. TABLE IV Performace aalysis of Multichael Recofigurable FIR filter Performace measures Dual port Memory based LUT ACC-Radix4 No of taps 6-tap 2-tap 6-tap 2-tap No. of Chaels Total Logic Elemets Delay(s) Power(mw) Freq(MHz) ISSN : Vol 6 No 2 Apr-May

9 TABLE V Sythesis results of Cadece RC compiler for RNS based multichael Recofigurable 2-tap FIR filter Parameter Proposed desig with sigle chael RNS-LUT Proposed desig with multichael RNS-Accradix-4 RNS-Acc-radix- 4 RNS-LUT No of chaels Area(mm 2 ) Power(mw) V. CONCLUSION I this paper a efficiet high speed time divisio multiplexed multichael recofigurable RNS based FIR filter architectures have bee discussed which ca be effectively used for implemetig ay N-tap filters. The N-tap Recofigurable FIR filter thus implemeted combies PoT (2 m ) sub modules thereby icreasig the flexibility. The results of RNS based recofigurable FIR filter architectures are aalyzed ad compared with respect to area ad speed, ad show better performace i terms of area with dual port memory based LUT multiplier ad improvemet i speed of operatio with accumulator based Radix-4 multiplier. Comparig the results, the area gets reduced i LUT based RNS FIR Filter sice half the memory was reduced by maipulatig the odd multiples of the fixed coefficiet, ad the speed of operatio was icreased i RNS FIR Filter usig Accumulator based radix-4 multiplier due to the reductio i the partial products. These architectures were sythesized ad compared i various platforms like Altera, Xilix ad Cadece. The results of the proposed recofigurable RNS architectures were also compared with existig architectures ad shows improved performace i terms of frequecy. Thus the proposed recofigurable architectures achieve high speed ad low complexity ad the reprogrammability of FPGA techology make the architectures a viable alterative to the developmet of recofigurable hardware for real time sigal processig applicatios. REFERENCES [] Digital Sigal Processig solutio: Desigig for Optimal Results High-Performace DSP usig Virtex-FPGAs, Xilix corporatio, pp. 99-3, 25 [2] David V. Aderso, ad ErhaÖzalevli, A Recofigurable Mixed-Sigal VLSI implemetatio of Distributed Arithmetic Used for Fiite Impulse Respose Filterig, IEEE Trasactios o Circuits ad Systems-I: Regular Papers, Vol. 55, No. 2, March 28. [3] Kua-hug, ad Tzi-Dar, A low power digit based Recofigurable FIR Filter, IEEE Trasactios o circuits ad systems, Vol. 53, Aug 26. [4] Pramod Kumar Meher, New Approach to Look Up Table Desig ad Memory-Based Realizatio of FIR Digital Filter, IEEE Trasactios o circuits ad systems irregular papers, Vol. 57, No. 3, March 2. [5] R.Mahesh, ad A.P Viod, New Recofigurable Architectures for implemetig FIR Filter with low complexity, IEEE Trasactios o computer aided desig of itegrated circuits ad systems, Vol. 29, Feb 2. [6] T. Solla, ad O. Vaiio, Compariso of programmable FIR filter architectures for low power, i Proc. of 28th Europea Solid State Circuits Coferece, pp , September 24 26, 22 [7] Pramod Kumar Meher, FPGA Realizatio of FIR Filters by Efficiet ad Flexible Systolizatio Usig Distributed Arithmetic, IEEE Trasactios o sigal processig, Vol. 56, No. 7, July 28. [8] Y.wag, Residue to biary coverters based o ew Chiese remaider theorems, IEEE Trasactios o Circuits ad Systems II, pp , Mar 2. [9] B.Viakota ad V.V Bapeswara Rao, Fast coversio techiques for Biary Residue umber system, IEEE Trasactios o Circuits ad Systems, Vol. 4, No. 2, Dec 994. [] Naresh R. Shabhag ad Raymod.E.Sifred, A sigle chip pipelied 2-D FIR filter usig Residue Arithmetic, IEEE Joural of solid state circuits, vol.26, No.5, May 99 [] Adreas Lidahl, ad Lars Begtsso, Low Power FIR filter usig combied residue ad radix-2 siged digit represetatio, DSD'5, May 25 [2] W. J. Jekis, Techiques for residue-to-aalog coversio for residue ecoded digital filters, IEEE Trasactios o Circuits ad Systems Vol. CAS-25, pp , July 978. [3] Yuke Wag, Xiaoyu Sog, Mostapha Aboulhamid, ad Hog She, Adder Based Residue to biary Number Coverters for (2 -, 2, 2 +), IEEE Trasactios O Sigal Processig, Vol. 5, No. 7, July 22. [4] D. Gallaher, F. Petry, ad P. Sriivasa, The digital parallel method for fast RNS to weighted umber system coversio for specific moduli(2 -; 2 ; 2 +), IEEE Trasactios o Circuits ad Systems II, vol. 44, pp ,Ja [5] A. Croisier, D. J. Esteba, M. E. Levilio, ad V. Rizo, Digital filter for PCM ecoded sigals, U.S. Patet , Dec. 4, 973. [6] H. Yoo ad D. V. Aderso, Hardware-efficiet distributed arithmetic architecture for high-order digital filters, i Proc. IEEE It. Cof. Acoustics, Speech, Sigal Processig(ICASSP), Mar. 25, vol. 5, pp. v/25 v/28. [7] Xilix Icorporatio, The Role of Distributed Arithmetic i FPGA-based sigal Processig, Xilix applicatio otes, Sa Jose, CA. [8] Youg-Ho Seo ad Dog-Wook Kim, A New VLSI Architecture of parallel multiplier Accumlator Based o Radix-2 Modified Booth Algorithm, IEEE Trasactios o VLSI Systems, Vol.8, No.2, Feb 2. ISSN : Vol 6 No 2 Apr-May

10 [9] Chip-Hog Chag, Radix-8 Booth Ecoded Modulo Multipliers with Adaptive Delay for High Dyamic Rage Residue Number System, IEEE Trasactios o Circuits ad Systems I: Regular Papers, 2 [2] Shuagchig Che ad Shugag Wei Performace Evaluatio of Siged-Digit Architecture for Weighted-To-Residue ad Residue-to-Weighted Number Coverters with Moduli Set (2 -, 2, 2 + ), IPSJ Digital Courier, Vol. 2, Jue 26. [2] Liu Mig, Ya Chao, The Multiplexed Structure of Multi-chael FIR Filter ad its Resources Evaluatio, Iteratioal Coferece o Computer Distributed Cotrol ad Itelliget Evirometal Moitorig, IEEE 22. ISSN : Vol 6 No 2 Apr-May