Enhanced LUT For Modified Distributed Arithematic Architecture - FIR Filter

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1 N Vivek et al It. Joural of Egieerig Research ad Alics RESEARCH ARTICLE OPEN ACCESS Ehaced LT For Modified Distributed Arithematic Architecture - FIR Filter N Vivek*, Prof K Ausudha** *(Deartmet of Electroics Egieerig, Podicherry iversity, Puducherry) ** (Deartmet of Electroics Egieerig, Podicherry iversity, Puducherry) ABSTRACT This aer resets Ehaced LT for Modified Distributed Arithmetic Architecture for efficiet imlemet of fiite imulse resose (FIR) filter. I this techique cosists of shift registers, Look Table (LT) ad accumulator. Based o this techique multiliers i Fir filter are relaced with LT. Multilics are erformed usig shift oer. Performace aalysis of various filter orders with filter coefficiets (with Kaiser Widow techique) are sythesized usig Verilog HDL. Keywords-Fiite Imulse Resose (FIR), Modified Distributed Arithmetic (MDA), Look Table (LT),Cofigurable Logic Blocks (CLBs) I. INTRODCTION Digital Fiite Imulse Resose (FIR) filters are frequetly used i most Digital Sigal Processig (DSP) systems by virtue of stability ad easy imlemet, esecially i the realm of commuic ad multimedia alics. I this sese, great effort has to be ut i desigig efficiet architectures for digital sigal rocessig fuctios such as FIR filters, which are widely used i sigal rocessig, telecommuics ad etc. The filters are major determiats of the erformace ad ower cosumtio of the whole system. Sice field rogrammable gate arrays (FPGAs) cotai a very high umber of Cofigurable Logic Blocks (CLBs), they become more feasible for imlemetig secific DSP fuctios such as FIR filters. The roblem of desigig FIR filters are sufferig from a large umber of multilics, which leads to excessive area ad ower cosumtio. May works have bee focused o desigig alterative algorithm such as Distributed Arithmetic (DA) Other works have develomet o otimizig multilics by decomosig them ito simle oers such as additio, subtractio ad shift or sharig commo subexressios. I literature, several multiliers-less schemes had bee roosed. These methods ca be classified i two categories accordig to how they maiulate the filter coefficiets for the multily oer. The first tye of multilier-less techique is the coversio-based aroach, i which the coefficiets are trasformed to other umeric reresets whose hardware imlemet or maiul is more efficiet tha the traditioal biary rereset. Examle of such techiques are the Caoic Sig Digit (CSD) method, i which coefficiets are rereseted by a combi of owers of two i such a way that multilic ca be simly imlemeted with adder/subtractios ad shifters, ad the Demster-Mcleod method, which similarly ivolves the rereset of filter coefficiets with owers of two but i this case artial results arraged i cascade to itroduce further savigs i the usage of adders. The secod tye of multilier-less method ivolves use of memories (RAMs, ROMs) or Look- Tables (L) to store re-comuted values of coefficiet oers. These memory-based methods ivolve Costat Coefficiet Multilier method ad the very-well kow Distributed Arithmetic method The aer is orgaized as follows: Sectio II ad Sectio III give the itroductio of Basic FIR filter ad Distributed Arithmetic. Sectio IV exlais the realiz usig Distributed Arithmetic ad Sectio V deals with Modified Distributed FIR Filter ad its Realiz. Results are aalyzed i Sectio VI. Sectio VII cocludes the roosed work. II. BASIC FIR FILTER (N-TAP) I sigal rocessig, a fiite imulse resose (FIR) filter is a filter whose imulse resose is of fiite dur, because it settles to zero ifiite time. This is i cotrast to ifiite imulse resose (IIR) filters, which may have iteral feedback ad may cotiue to resod idefiitely. The basic N-ta Filter show i Figure1, Figure 1 Basic FIR filter (N-ta) 1220 P a g e (1)

2 Pricial author al. It. Joural of Egieerig Research ad Alic Where, x[] is the iut sigal, y[] is the outut sigal, a i is the filter coefficiets. For FIR Filter of N order filter has Coefficiets N+1 Multiliers N+1 Adders N III. DISTRIBTED ARITHMETIC Distributed Arithmetic is oe of the most well kow methods of imlemetig FIR filters. A FIR filter of legth K (bit size) is described as (2) Where h[k] is the filter coefficiets ad x[k]is the iut data. For simlicity it ca be writig as x 0 [k] =x [-k] i equ (2) as (3) Where X 0 [k] is the B-bit two comlemet biary umber to reset data. O substitutig equ () i (3) we get (o solvigfurther)... (5) We have. I equ.5 we observe the filter coefficiets are restored i LT ad addressed by. This way the MAC blocks of FIR filters are reduced to access (multilier-less circuit) ad summ with LT. IV. FIR FILTER REALIZATION SING DISTRIBTED ARITHMETIC The basic block Diagram of Distributed Arithmetic for ta Fir Filter is show below i Figure [2] Figure2: Block diagram of DA Fir Filter A Iut buffers: I the Block Diagram shows the Iut buffers, as it stores the iut values as the order that LSB values are take i for first cycle ad so o. Durig First iter least sigificat bit take ad stored i register ad it set it to the further LT stage ad for ext iter the cycle reeats for N bits. For examle: X1=1101, X2=0010 X3=0010, X=1111 X1[0] X2[0] X3[0] X[0] =1001 X1[ X2[ X3[ X[ =0111 X1[2] X2[2] X3[2] X[2] =1001 X1[3] X2[3] X3[3] X[] =1001 Where X1, X2, X3, ad X are the iuts of Fir Filter B Look P Table (LT) I this aer, for desigig the LT ROM is used to store the filter coefficiets as show i the table [. Table 1: Formula for gettig Filter Coefficiets used i LT b h [N- b h [N- b h [0] Coefficiet Value 2] h[0]b b N-1 b N-2 b 0 h[0]b h[n- b N h[0]+ +h[n- As the umber of addresses icreases, fuctios also icreases. Hece comlexity will also icrease. Here addresses cotai four bits ad sixtee fuctios. If addresses have bit the LT will have 255 differet combis. To desig a LT of 255 differet fuctios is comlex ad it will occuy more area. C Scalig uit: Scalig accumulator reduces the size, elimiates the multilier ad erforms the oers serially. It requires adder, register ad right shifter each of -bit size.firstly iut a which is comig from LT is added with iut b which is iitially zero. It is stored i register ad before shiftig, the LSB bit is stored i register because i order to save the shifted bit. The right shifted by oe bit or divided by 2. The ext iut a comig from LT at ext clock cycle is added with reviously right shifted outut. It is agai stored i register ad right shifted by oe bit ad so o P a g e

3 Pricial author al. It. Joural of Egieerig Research ad Alic V. MODIFIED DISTRIBTED FIR FILTER A ig Techique: For Desigig of ta Fir DA filter we eed LT with addresses i order to reduce the address, this aer reduces the address usig artitioig techique. The Basic block diagram of modified Distributed Fir Filter is show i Figure []. Figure 3: Modified Distributed FIR Filter ( ta filter) B Modified Look P Table (LT) I this aer for the redesigig of LT we used ROM to store the filter coefficiets usig the formula as show i the Table[. b h [ 0] b h [ b h [N -2] b h [N- b hn[ ] Coefficiet Value h[0]b b 0 b 1 b N-2 b N-1 b N h[0]b h[n-b N h[0]+ +h[n- the shifted bit. The right shifted by oe bit or divided by 2. The ext iut a comig from LT at ext clock cycle is added with reviously right shifted outut. It is agai stored i register ad right shifted by oe bit ad so o. VI. V REALIZATION OF TAP, TAP AND TAP MDA FIR FILTER This Paer maily deals with the memory utiliz ad o of LT s of FIR Filter of Ehaced LT for Modified Distributed Arithmetic. The Table [2] shows with Various Filters with Orders of, ad Filter. Table 2: Comariso of, ad TAP MDA filter with LT s ad Memory Locs No N Me N Me N Me N Me Fi o. mor o. mor o. mor o. mor lte of y of y of y of y r L Loc L Loc L Loc L Loc s s s s - Ta Ta Ta Table 1: Formula for gettig Filter Coefficiets used i LT As the umber of addresses icreases, fuctios also icreases. Hece comlexity will also icrease. Here addresses cotai four bits ad sixtee fuctios. If addresses have bit the LT will have 255 differet combis. To desig a LT of 255 differet fuctios is comlex ad it will occuy more area. C Scalig uit: Scalig accumulator reduces the size, elimiates the multilier ad erforms the oers serially. It requires adder, register ad right shifter each of -bit size.firstly iut a which is comig from LT is added with iut b which is iitially zero. It is stored i register ad before shiftig, the LSB bit is stored i register because i order to save Figure5: Modified DA FIRFilter VII. RESLTS AND ANALYSIS The erformace aalysis of Modified Distributed Fir filter of, ad filter is doe i Family of Sarta 3E ad the Device XC3S100E, ackage of CP P a g e

4 Pricial author al. It. Joural of Egieerig Research ad Alic Table 3: Delay erformaces of, ad TAP MDA filter without artitio erformace Aalysis -- Delay without artitio with 2- artitio with artitio with artitio Figure 7: Proosedof Ehaced Modified Distributed Arithmetic FIR Filter Figure 6: Modified Distributed Arithmetic FIR Filter Table 5: Delay erformaces of, ad ta MDA Filter of Proosed Model erformace Aalysis -- Delay without artitio with artitio without artitio 2 with 2- artitio with artitio Partiti o VIII. CONCLSION I this aer, the multilier-less FIR filter is imlemeted usig Ehaced LT with Modified Distributed Arithmetic which cosists of Look Table is ivolved usig Verilog HDL.Coversio of Floatig oit Filter coefficiets to Fixed oit Filter coefficiets i L used by FDA Tool usig Mat Lab, a Ehaced LT with efficiet Modified Distributed Arithmetic FIR Filter is roosed. Therefore by relacig the ehaced LT ad iut buffers with the roosed model, reduces the area by memory address Locs. The reduced Number of logic levels of this work offers the great advatage i the reductio of delay. REFERENCES [ M.Keerthi,,S.NagakishoreBhavaam,Jeeva Reddy K, Distributed Arithmetic for FIR Filter Imlemet o FPGA, Iteral Joural Of Egieerig Research & Techology (IJERT), Vol.1, Issue.9, 1-, November 2012 [2] Zhou, Yaju, ad Pigzheg Shi, Distributed Arithmetic for FIR Filter imlemet o FPGA, Proc. IEEE o Iteral Coferece i Multimedia Techology (ICMT), 2011 o, , [3] Yaju Zhou, igzheg Shi, Distributed Arithmetic for FIR Filter Imlemet O FPGA, IEEE Iteral Coferece o Commuics, Circuits ad Systems(ICCCAS), , July [] Naredra Sigh Pal, Harjit Pal Sigh, R.K.Sari, Sarabjeet Sigh, Imlemet of High Seed FIR Filter usig Serial ad Parallel Distributed Arithmetic Algorithm Iteral Joural of Comuter Alics, Volume 25 No.7, July 2011 [5] R, Nathiya R, Realiz Of Fir Filter sig Modified Distributed Arithmetic Architecture, A Iteral of Joural Sigal & Image Processig(SIPIJ) Vol.3, No.1, February P a g e

5 Pricial author al. It. Joural of Egieerig Research ad Alic [6] JiafegXie, Jiaju He, Guazheg Ta, FPGA Realiz of FIR filters for highseed admedium-seed by usig modified distributed arithmetic architectures, Microelectroics joural, 1(2010) [7] Partrick Loga, Ali Miri, Area-Efficiet Fir Filter Desig o FPGAs usig Distributed Arithmetic, IEEE Iteral Symosium o Sigal Processig ad Iform Techology, : 2-252, [] Meher P K, Chadrasekara S et al, FPGA Realiaz of FIR Filters by efficiet ad flexible Systoliz usig Distributed Arithematic, IEEE Tras. o Sigal Processig, Vol. 56,o. 7, ,Jul 200. [9] S.A White, Alics of the Disributed Arithematic to Digital Sigal Processig :A tutorial review, IEEE ASSP Mag., vol.,o.3,.5-19,jul.199. [10] Jug Pil Choi,Seug-cheol Shi ad Ji- Gyu Chug, Eficiet Rom Size Reductio For Distributed Arithematic, i Proc.IEEE It. Sym.Cricuits Syst.(ISCAS),May 2000,Vol. 2,. v/125-v/ P a g e