An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic Λ

Transcription

1 An Efficient VLSI Architecture Parallel Prefix Counting With Domino Logic Λ Rong Lin y Koji Nakano z Stehan Olariu x Albert Y. Zomaya Abstract We roose an efficient reconfigurable arallel refix counting network based on the recently-roosed technique of shift switching with domino logic, where the charge/discharge signals roagate along the switch chain roducing semahores results in a network that is fast and highly hardware-comact. The roosed architecture for refix counting N bits features a total delay of ( log N + N ) Λ T d, where T d is the delay for charging or discharging a row of two refix sum units of eight shift switches. Simulation results reveal that T d does not exceed ns under.8-micron CMOS technology. Our design is faster than any design known to us for N». Yet another imortant and novel feature of the roosed architecture is that it requires very simle controls, artially driven by semahores, reducing significantly the hardware comlexity and fully utilizing the inherent seed of the rocess. Index Terms: Secial-urose arallel architectures, digital signal rocessing, VLSI design, domino logic, comuter arithmetic. Introduction Due to the high degree of miniaturization ossible today in VLSI technology, the size and comlexity of designs that can be imlemented in hardware has increased dramatically. This has made it technologically feasible and economically viable to develo high-seed alications-secific architectures featuring a sectacular erformance increase over their general-urose counterarts []. The main goal of this work is to resent a secial urose architecture for fast and hardware-comact comutation of a arallel binary refix counter. Our design is based on the recently-roosed technique of shift switching with domino logic [6, 8]. Λ Work suorted by NSF grants CCR-99 and MIP-9687, by ONR grant N-97--6, and by ARC grant y Deartment of Comuter Science, SUNY at Geneseo, Geneseo, NY, USA z Deartment of Electrical and Comuter Engineering, Nagoya Institute of Technology, Showa-ku, Nagoya 66, JAPAN x Deartment of Comuter Science, Old Dominion University, Norfolk, VA 9-6, USA Deartment of Electrical and Electronic Engineering, University of Western Australia, Perth, AUSTRALIA Reconfigurable bus systems enhanced with shift switches have been recently roosed to solve a number of fundamental comutational roblems [,, 6, 7, 8]. Such systems have the following features: () When secial digital signals called state signals are roagating through a shift switch array, modulo oerations can be erformed directly, simlifying the traditional aroach to basic arithmetic comutation; and () During the rocess the state signals are inverted, alternatively, in two mutually inverted forms (n and ), minimizing the loads of transistors and maximizing the seeds of circuits. By alying recharged CMOS domino logic techniques to ass-transistor-based shift switched buses we can obtain a domino charge/discharge chain featuring the interesting roerty that the charge/discharge signals can roagate along the chain and always roduce a semahore to indicate the end of the rocess [6]. This makes it ossible to construct a network of rocessing elements to comute arallel binary refix sums fast and in a highly hardware-comact fashion. The roblem of arallel binary refix counting is fundamental in arallel rocessing, for its solution is the rincile ingredient in arithmetic exression evaluation, storage and data comaction, rocessor assignment, and routing, among many others []. We first roose a arallel refix counting network of I/O size N (that is, with N inut bits, for N = k = n Λ n). This involves a two-level construction containing a total of N + N cascaded basic shift switches, with N ass-transistor-based shift switch lus N trans-gate-based shift switches. Each ass-transistorbased switch is associated with a simle rocessing element (PE, for short): for each row of switch units there is a row rocessing element referred to as PE r. In fact, both the PE s and the PE r s, are simle control units, receiving corresonding semahores, and either sending control signals to tri-state drivers, or sending select signal to the MUX, or sending recharge/evaluation enable signals to start a recharge/evaluation rocess. Thus, the entire network can be erceived as an alication-secific circuit. We then go on to modify this architecture by relacing the PE s and the PE r s by a few simle combinational and sequential circuits, consisting of two registers and of two simle switches synchronized by the clock and the semahore

2 in each node of the refix counting network. We have simulated and tested the modified architecture. The SPICE circuit simulation (on.8-micron CMOS technology at a - V suly and MHz clock) has shown less than ns delay for each of the row recharge and row discharge oerations. Our refix sum design achieves a total delay of ( logn+ N ) Λ Td, where T d is the delay required to charge or discharge a row of two refix sum units (in our simulations T d» ns). Since it is not realistic to comute the refix sums of a large array of binary numbers, we assume that N <. Under this assumtion, the roosed architecture is about % faster than any architecture known to us, including a tree of adders, or a rocessor with the same structure as ours but with each shift switch substituted by a half adder (half-adder-based rocessor, for short). Another imortant feature of the roosed design is that it has a comact VLSI area, requiring an area about :7Λ(N + N)ΛA h which is almost linear in the inut size. Here, A h is the area equivalent of a half adder. This area is significantly smaller than both the half-adder-based rocessors (about %), and the tree of half adders rocessors, which require an area of about (N log N :N + ) Λ A h. The area for the control devices necessary in any such an architecture is omitted. Yet another imortant feature of our architecture is that the N-refix sums are comuted and outut row by row,with a simle control mechanism driven by semahores roduced at the end of the row s domino charging/discharging. This simlifies the hardware requirements, and the full inherent seed of the comutation can be utilized. Precharged CMOS shift switches and refix sums units Figure illustrates a ass-transistor-based schematic of basic shift switch S < ; >. Once the switches are recharged (high) and reset by control Y, the discharging signals X() and X () from the shift in ort will ull-down the data ath to yield, resectively, shift out R and Q. To imrove the efficiency of discharging, we cascade a small number of the n-switches four, to be more recise to form a refix sums unit as illustrated in Figure. Here, the discharging rocess now yields the following (modulo ) results: u =(X + a) mod, v =(X + a + b) mod, w =(X+a+b+c) mod, z =(X+a+b+c+d) mod = R, a = b X+a c, b = b X+a+b c, c = b X+a+b+c c, z = b X+a+b+c+d c. The comlete rocess is comosed of two hases that we describe next: A. The recharge hase. Referring to Figure that we use as illustration, the following should occur in the recharge hase:. E, a tri-state enable signal is set to, i.e. the outut of each tri-state internal bus driver is in Hi-Z; Figure. Illustrating the nmos asstransistor-based schematic of the shift switch S<; >: (X();Y;R(); Q). Figure. Illustrating the refix sums unit. The inut bit of each PE associated with the switch is loaded into the (state) register. This will reset each switch to the corresonding state;. The recharge and evaluation signal rec/eval is set to, which starts recharging all switches (outorts including s) of the unit in arallel. When the recharge is done, the semahores q = and R = are roduced. If a row contains more than one switch unit, then the units are cascaded in a chain form. B. The evaluation hase. In this hase the following should occur (s before, refer to Figure ):. Set the recharge and evaluation signal rec/eval to ;. When the discharging state signal X = (or X = ) arrives, its bit ulls down the reset data ath along the unit to roduce for each unit, as described above, the bits u; v; w; z as well as a ; b c d and to roduce the semahores q = and R = (or R = );. If the signal E from PE r is, read the outut bits u; v; w; z;. If the signal E from PE r is, each PE triggers a register-load oeration to load the values a ; b c d otherwise, there is no loading;. The recharge and evaluation signal rec/eval is set back to, i.e. start recharge again and kee in recharge hase until

3 the next evaluation begins. If a row contains more than one switch unit, the discharging rocess can roagate from one switch unit to another automatically. Note that the PEs of each switch unit discussed here can be simly driven by the semahore of the unit, in other words, all oerations can be driven by the semahore after initialization. The arallel refix counting architecture Refer to Figure for the block diagram of a comlete refix counting network with an inut size of N = 6. The mesh consists of n = 8 rows, each featuring two cascaded switch units, an n-switch and a -switch, as described in Section. To simlify the network control, we use an additional column of trans-gate-based shift switch array on the left art of the mesh. does not require two hases. The beginning of each row consists of a row rocessing element PE r which receives a semahore from the revious row and controls a -inut multilexer and an inut state signal generator consisting of two tri-state buffers. The algorithm is selled out as follows:. Initial stage. fcomutes and oututs the least significant bits of the refix countsg Ste. All PEs load their inut bits into their registers; Ste. Each refix sum unit starts the initial recharge hase; Ste. PE r sets select signal to, such that, the right inut (i.e. ) of each MUX is selected; Ste. PE r sets Er = and each row begins domino discharging; Ste. PE r sets E = (i.e. no outut and register loading, refer to the evaluation hase in Section ; Ste 6. When a semahore value of is received by the i-th PEr i times, it sets select signal to ; Ste 7. The i-th PEr sets E = (i.e. to outut and load register);. Main stage Consists of log N iterations of the following Ste 8. PE r sets select signal to such that the right inut (i.e. ) of each MUX is selected; Ste 9. PE r sets Er =, and each row begins domino discharging; Ste. PE r sets E = (i.e. no outut and register loading); Ste. PE r sets select signal to ; Ste. PE r sets Er =, each row begins domino discharging; Ste. PE r sets E = (i.e. outut and register loading). Figure. The arallel refix counting network. Let the inut of the column switch array be a sequence of (-tye) state signals, b; b; :::; b7, and let the outut be a sequence of regular signals, ; ; :::; 7. Clearly, we have i =(b+b+ + bi) mod. for all» i» 7. Note that this is slower than the recharged switch array and generates no semahores. However, the comutation The algorithm can be interreted as follows: In the initial stage (Stes through ) each row comutes the least significant bit (LSB) of the sum of bits in the row. The results (called the arity-bits of the rows) then are refix summed by the column switch array, which takes about i stes of semahore (row) roagation time (waiting time) to get the i-th refix sum initially comuted, the i-the row starts to comute the LSBs of the global refix sums for the row (Stes 6 and 7). When the rocessing of the initial stage is comleted, each row begins executing the main stage. In the stage, the rocess is similar to that in the initial stage excet that there is no waiting for the refix sum of the arity-bits of the lower rows (the waiting takes lace in the initial stage), the data items are always available and the comutations are for the remaining bits of the refix sums. In fact, the column switch array involves a ielined rocess to roduce the bits of the global refix counts of the rows.

4 Simulations and tests erformed In our test imlementations we use a modified refix sum unit as shown in Figure. The PEs are removed, the recharge-discharge and I/O controls are erformed correctly by the sequential circuit which consists of two registers and two simle switches synchronized by the clock and the semahore (i.e. Cin/Cout). It is easy to see that the unit is functionally the same as the one shown in Figure. We also modify the overall refix network architecture corresondingly as shown in Figure. The algorithm of the comutation is the same as described in Section, excet that all oerations done by the PEs and by the PE r s are now being erformed by simle combinational and sequential logic circuits lus reconfiguration switches. Their brief descrition is given below. It is worth noting that in our simulation, T d is no more than ns, and the total delay of the refix comutation is no more than 8ns. This total delay takes no more than 6 instruction cycles since under the VLSI technology we assumed, an instruction cycle is about to 8 ns. Comared with the software comutation of the refix sums, which requires at least 6 instruction cycles, the seed-u of the roosed rocessor is significant. Since the comutation of the refix sums of a large array of binary numbers, say N is not very realistic, we assume that N <. Under this assumtion, our simulation results show that our rocessor is at least % faster than any rocessor known to us, including the tree of adders [], or the rocessor with the same structure as ours but with each shift switch relaced by a half adder (half-adder-based rocessor for short). Since each nmos transistor-based shift switch is about 7% of a half-adder, the total area can be secified as :7 Λ (N + N) Λ A h, where A h is a half-adder area equivalent (note that registers and basic controls devices are not counted because they are necessary in any scheme to accomlish the comutation). This area is about % smaller than that of both half-adder-based rocessors, and of the tree of halfadders which require an area of (N log N :N + ) Λ A h. Note that the half-adder-based rocessor requires a significantly larger number of control devices because it does not generate semahores, even if it uses the traditional domino logic technique. Concluding remarks Figure. The modified refix sums unit. We have simulated the refix sums unit. The SPICE circuit simulation (on.8-micron CMOS technology at a - V suly and MHz clock) has shown less than ns delay for each of row recharge and row discharge oerations based on the circuit of Figure. We refer the reader to the analog trace shown in Figure 6. More simulations and tests are in rogress. Based on the simulation results we can conclude that. The initial stage takes about Td+ N N Λ T d, where T d is the delay of charge or discharge of a row of two refix sum units;. The main stage takes (log N )ΛT d time. Notice that T d denotes two domino charge and discharge rocesses of a row. Note that the register loadings are overlaed with charge and discharge oerations in all stages excet the initial stage;. The total delay can be secified as ( log N+N N )ΛT d. The main contribution of this aer was to roose a arallel refix counting network of size N (i.e. with N- inut bits, for N = k = n Λ n. Our design is a two-level architecture involving a total of N + N cascaded simle shift switches, with N ass-transistor-based shift switches along with trans-gate-based shift switches. The resulting network achieves a delay of ( log N + N )ΛT d, where where T d is the delay incurred in charging or discharging a row of two refix sum units. Our simulation results show that under.8-micron CMOS technology T d is not more than ns. Our architecture is also area-comact and is constructed by using CMOS, domino logic techniques on buses with shift switches. The rocessing elements require a very simle asynchronous control, being driven by semahores roduced at the end of each rows domino discharging rocess. This greatly simlifies the hardware requirements, and allows the full inherent seed of the comutation to be utilized. Finally, the alication of the roosed binary refix counter can be easily extended using a ielined technique for larger binary counter. For examle, with the available of a 6-bit refix counter, for counting u to 7-bit, we may

5 roduce the refix counts for the first set of 6 bits and then rocess in ieline the second set of remaining 6 bits. We then send each rocessor (receiver) two results: The total of the revious set (i.e. the refix count value of the last bit of the revious set, if there is any, otherwise ) and the refix count value of the corresonding bit. The sum of these two values, clearly is the refix count of the corresonding bit. References [] K. Bondalaati, and V. K. Prasanna, Reconfigurable Meshes: Theory and Practice, Proc. Reconfigurable Architecture Worksho, RAW 97, Orlando, Florida, Aril 997. [] I. S. Hwang, and A. L.. Fischer, Ultrafast comact - bit CMOS adders in multi-outut domino logic, IEEE Journal of Solid-State Circuits., (989), [] R. H. Krambeck, C. M. Lee, and H.S. Law, High- Seed Comact Circuits with CMOS, IEEE Journal of Solid-State Circuits, SC-7, No., June, 98. [] R. Lin, Reconfigurable Buses with Shift Switching - VLSI Radix Sort, Proc. International Conference on Parallel Processing, St. Charles, Illinois, 99, Vol III, -9. [] R. Lin, and S. Olariu, Reconfigurable buses with shift switching concet and alications, IEEE Transactions on Parallel and Distributed Systems, 6, (99), 9-. [6] R. Lin, Shift switching and novel arithmetic schemes, Proc. 9th Asilomar Conference on Signals, Systems and Comuters, Pacific Grove, CA, November 99. [7] R. Lin and S. Olariu, Efficient VLSI architecture for Columnsort, IEEE Trans. on VLSI Design, 999. [8] R. Lin and S. Olariu, Reconfigurable shift switching arallel comarators, VLSI Design, in ress, 998. [9] A. Mukherjee, Introduction to nmos & CMOS VLSI System Design, Prentice-Hall, Englewood, NJ, 986. [] E. E. Swartzlander, Jr., Comuter Arithmetic, IEEE Press, Vol. and, 99. [] N. Weste and K. Eshraghian, Princiles of CMOS VLSI design, a systems ersective, Second Edition, Addison-Wesley, 99. /Q (Voltage:v ) /R (Voltage:v ) /R (Voltage:v ) /PRE (Voltage:v ) Figure. The modified arallel refix counting network. Prefix: MHz Analog Trace Legend /Q /Q:v /R /R:v /R /R:v /PRE /PRE:v e-9 e-9 6e-9 8e-9 e-8.e-8.e-8.6e-8.8e-8 e-8 t (Time:sec ) Figure 6. The analog trace of the refix sum circuit in Figure.