There are two basic types of FET s: The junction field effect transistor or JFET the metal oxide FET or MOSFET.

Transcription

1 Page 61 Field Effect Transistors The Fieldeffect transistor (FET) We know that the biolar junction transistor or BJT is a current controlled device. The FET or field effect transistor is a voltage controlled device. The outut current of the FET is controlled by an inut voltage, not an inut current. There are two basic tyes of FET s: The junction field effect transistor or JFET the metal oxide FET or MOSFET. We will look at the variations and limitations of both tyes of devices. Introduction to the JFET rain The hysical construction of the JFET is significantly different than the BJT. The diagram to the right is the first ste in making an nchannel JFET. It is a single iece of ntye silicon semiconductor, with a terminal fused to each end. The lower end is called a source is called a drain & the uer end n tye silicon Figure 1 The beginnings of an nchannel JFET. The suly voltage the drain to the source. forces conventional current to flow from

2 Page 62 Electronic Fundamentals II The JFET To comlete our JFET, we will add tye material as shown in Figure 2. It will be in the shae of a collar and surrounds the original ntye silicon. As you can see, there is a channel of ntye material that asses through the collar, hence the name nchannel JFET. The third terminal, called the gate, is attached to the collar. rain tye silicon fused in channel rain Remember that the JFET is made from one solid iece of intrinsic silicon that has been doed to achieve the configuration shown in Figure 2. Figure 2 The n Channel JFET Where the ntye and tye materials meet, a diode junction forms. A deletion layer forms in a similar fashion to the n junction that we studied last term. This n junction has an imortant function in the oeration of the JFET. The Channel JFET rain The channel JFET is made in a similar fashion to the nchannel variety, however in this case, the channel is tye material and the gate ring is n tye material as shown in Figure 3. As with the n tye transistor, all the voltages and currents switch olarity when working with this device. Figure 3 The Channel JFET

3 Page 63 The JFET Oeration Overview The Schematic Symbols The schematic symbols are shown to rain rain the left. Note that the gate arrow oints out for the channel and in for the n channel. nchannel JFET Channel JFET The circle is otional as with the BJT. The oeration of the JFET is relatively simle. Figure 4 shows a cross section of the JFET. The voltage source S generates the current through the channel. The voltage source is used to control this current. n rain S How it Works Controlling I The overall oeration of the JFET is based on the varying width of the channel to control the drain current. Figure 4 nchannel JFET Cross Section In Figure 5, the voltage S is alied between the drain and the source and sets u a drain current (I ) as shown. The gatesource voltage ( ), reverse biases the gatesource diode. Just as in a simle diode, the deletion region grows as the reverse bias across the n junction is increased. This reduces the cross sectional area of the conducting nchannel, making it narrower, and thereby increasing the resistance and controlling the drain current I. Increasing will further constrict the channel and will cause I to dro. As increases (becomes more negative) I decreases.

4 Page 64 Electronic Fundamentals II The JFET Oeration Overview I at Maximum I is Reduced I is Further Reduced I is Arox A rain B rain C rain rain = I 1 S =1 I 1 S =2 I S 1 =5 I 1 S A eletion Layer eletion Layer enlarged eletion Layer enlarged further Figure 5 The Relationshi between eletion Layer has enlarged and comletely chocked off I and I is zero. The maximum drain current I is flowing. B C is increased to 1. This causes the deletion layer to enlarge into the channel. This reduces the size of the channel, which reduces I. is increased to 2. This causes the deletion layer to enlarge further into the channel which further reduces I is increased to 5. This causes the deletion layer to enlarge and comletely choke off the channel. This causes I to be reduced to near zero. The value of that causes I to be reduced to this near zero value is called the gatesource. cutoff voltage (off) Note : varies for different JFETS (off)

5 The JFET Oeration Overview Another Way to control I S = 1 S = 4 A rain B rain C rain S = 5 Page 65 =7 S rain I I I I = = = = Figure 6 The effects of varying S with constant A In Fig. 6 (A) is. A small deletion layer exists around the gate. The deletion layer exists because of the relationshi between and S. The gate (tye) is more negative than the drain (ntye). This means that the n junction between the gate and the n tye channel is reverse biased and the deletion layer will grow as wide as necessary to reach equilibrium. This deletion layer extends into the channel and reduces its size. B In Fig. 6 (B) remains at. Note that S is now 4. This further increases the reverse bias on the gate diode. The deletion layer increases into the channel and reduces the current I. At the same time, increasing S to 4 increases the current I. Now we have two forces working against each other. Increasing S will increase the current I while, at the same time, the deletion layer is increasing to reduce the current I. The forces are not yet equal. S is the stronger force at this oint, and I will increase to a new higher value.

6 Page 66 Electronic Fundamentals II The JFET Oeration Overview S = 1 S = 4 =5 S A rain B rain C rain S = 7 rain I I I I = = = = Figure 6 The effects of varying S C In Fig 6 (C) remains at. Note that S is now 5. The two forces are now equal in magnitude. The value of S at which this occurs is called the Pinchoff voltage ( P ) In Fig 6 () remains at. Note that S is now 7. The two forces continue to be equal in magnitude. Increasing S will try to increase I, but the enlarging of the deletion layer into the channel will resist the increase. I will remain relatively constant. Further increases in will not increase I S. Figure 7 shows the drain curve for the descrition above. The art of the curve to the left of P is called the ohmic region. As S increases from to, the drain current increases. P with constant (ma) I I SS Ohmic Region Constant Current Region = Here, the JFET is acting like a resistor, a linear increase in S causes a linear increase in current I =5 BR Figure 7 Shorted rain Curve showing the constantcurrent region and the ohmic region S

7 The JFET Oeration Overview Page 67 Constant Current Region As S increases above the value of P, the value of drain current levels off at a relatively constant value. (ma) I I SS Ohmic Region Constant Current Region = The region of oeration between P and BR is called the constantcurrent region. is the voltage measured from the gate to the source. =5 BR Figure 7 Shorted rain Curve showing the constantcurrent region and the ohmic region S When =, the otential difference between the gate and the source is. We essentially have shorted the gate to the source. This guarantees that =. When =, the drain current will be at its maximum ossible value. This shorted gate drain current is called I SS and it is the maximum value of I. The value of ISS is listed on the sec sheet and is measured under the following conditions: = and = S P Any value of JFET drain current cannot be greater than ISS. ISS can be comared with IC(sat) in a BJT circuit. It is the maximum ossible current that can flow in the drain circuit.

8 Page 68 Electronic Fundamentals II The JFET Oeration Overview I rain Curves (ma) Figure 8 shows the drain curves for I = through = 5. SS Note that as increases in a negative direction, the value of I decreases toward. = = 1 = 2 = 3 = 4 = 5 As S =5 becomes more and more BR Figure 8 Normal rain Curves negative, the oint is reached where the channel becomes blocked off by the deletion layer. I is now aroximately. In Figure 8, this haens when = 5. The value of that reduces I to this near value is called the gatesource cutoff voltage ( (off) ) At (off), current through the device stos. For conduction to occur, the value of must be between = and (off) The Relationshi between P and (off) This relationshi always exists: (off) & P will always have the same magnitude and oosite olarity. As an examle: If is 5, then P (off) will be 5. Since these two values are always equal magnitude and oosite olarity, only one will generally be listed on the device sec. sheet.

9 Page 69 The JFET Oeration Overview efinitions source cutoff voltage (off) The value of that reduces I to arox.. For the JFET, (off) is always equal in magnitude and has the oosite olarity as P. Pinchoff oltage P The value of drainsource voltage ( S) that allows maximum JFET current (I ) measured at = For the JFET P = (off) Shorted gatedrain currenti SS The maximum ossible value of I. Ohmic Region The ortion of the JFET oerating curve that lies below P.. Constantcurrent Region The ortion of the JFET oerating curve (between P and BR) where the drain current remains constant for fixed values of. JFET Biasing JFETs are always reverse biased. This means that the junction is always reverse biased. gate source In the exlanation for Figure 6, we said that even when the gate is shorted to the source and =,thegate source junction is still reverse biased. We never allow the gate source junction to become forward biased because the junction is not designed to handle any significant current.

10 Page 61 JFET Biasing Electronic Fundamentals II The JFET Oeration Overview Since the gate is always reverse biased, the reverse current will be near zero. This means that JFETs have an extremely high gate inut imedance that is tyically in the high megohm range. The data sheet for the MPF12 (the JFET that you have in your kit,) lists the maximum gate reverse current I S = 2 na under the following conditions. T = 25 O C S = = 15 Using Ohm s Law Imedance = 15 2nA = 7.5 G The advantage of this extremely high inut imedance is that it draws almost zero current from the source. This means that the JFET is almost no load on the source at all. The JFET is heavily used in integrated circuits since it has such a low current requirements. It runs cool, and this is a big advantage in an IC where thousands of FETs are etched into one small iece of silicon. The dc Biased JFET Circuit We know that the JFET is a voltage controlled device the outut characteristics are controlled by the inut or gate voltage.

11 Page 611 The JFET Oeration Overview We know that the size of the channel is controlled by the amount of reverse bias alied to the gate sourcejunction. This is what makes the device voltage controlled. It is the magnitude of that controls the drain current I. For the BJT hfe is a measure of how effectively the inut current controls the outut current. For the JFET Transconductance is a measure of how effectively the inut voltage controls the outut current. The outut current (I ) can be defined in terms of the circuit inut voltage by the formula: I SS (off) ( I = I SS 1 _ (off) = the shorted gatedrain current rating of the device = the gatesource voltage = the gatesource cutoff voltage Note: The value of ISS and (off) are comonent values and are constants for a given JFET. The value of is the only variable on the right side of the equation. This means that I is strictly a function of and if changes I will also change. ( 2 Ex demonstrates the use of the above equation

12 Page 612 Electronic Fundamentals II The JFET Oeration Overview Plotting The Transconductance Curve Plotting the transconductance curve for a secific JFET is a grah of all ossible combinations of and I for a secific device. The rocess for lotting the transconductance curve for a given JFET is as follows: 1. Plot a oint on the x axis that corresonds to the value of (off). 2. Plot a oint on the y axis that corresonds to the value of I S. 3. Select 2 or 3 values of the between and (off). For each value of selected, determine the corresonding values of I using the equation. 4. Plot the oints from ste 3, and connect all the lot oints with a smoother curve. Ex shows this rocess It is imortant to be able to lot the transconductance curves for the JFET. These curves are used in both the dc and ac analyses of any amlifier using the JFET. Most JFET sec. sheets list 2 values of (off) and I SS. These are the maximum and minimum values. When a range of values are given, we must use the two minimum values to lot one curve and the two maximum values to lot the second curve.

13 The JFET Oeration Overview The Maximum & Minimum Transconductance Curves Page 613 For the MPF12 in your kit the following values are given: (off) (off) = 2 (min) I assumed SS = 2 ma (min) = 8 (max) I = 2 ma (max) SS Using the rocedure on the revious age, the maximum and minimum curve are lotted for the MPF12 in Figure 9. Ex shows the comlete rocess for finding the Max. & Min. Transconductance Curves. () I Figure 9 Transconductance curves Max. & Min. curves for the MPF12 We have been working with the nchannel JFET in all examles. The nchannel JFET is much more commonly used than the channel JFET. All of the rinciles for the nchannel JFET aly to the channel JFET. As with nn and n BJTs simly reverse the olarity of the voltages and currents. Comarison of JFET and the BJT Remember that: The JFET is a voltage controlled device The BJT is a current controlled device (ma) 2

14 Page 614 Electronic Fundamentals II The JFET Oeration Overview Review of the dc Biased BJT I B = 1 A Keeing it very simle, we said I C = hfei B= 1mA earlier that if IB is 1 A in a BJT I E = 1.1 ma that has an hfe of 1, then IC will be 1 times IB or 1 ma as shown I B = 2 A in Figure 9(a). If we assume a linear relationshi between IBand I C, then Figure 9(b) and 9(c) are also true. If we were to grah this simle relationshi shown above, we would get the grah in Figure 1. This relationshi would continue until the transistor becomes saturated. At that oint, further increases in I will not increase I. B In reality, the relationshi is not totally linear. Figure 11 shows a more tyical curve. Note that there is some nonlinearity in the curve which can cause some distortion in the outut. Remember that for the BJT: the outut current IC is controlled by the inut current I B I =h I =2mA C FE B I = 2.2 ma E I B = 5 A I C =hfei B=5mA I E = 5.5 ma C Figure 9(a) Figure 9(b) Figure 9(c) I C (ma) I C (ma) 1 1mA 1 A h FE = ma 2mA 2 A h FE = ma 5mA 5 A h FE = ma Figure 1 BJT IC vs IB I B ( A) The BJT is a current controlled device Figure 11 I B ( A) A more tyical BJT IC vs IB

15 The JFET Oeration Overview Review of the dc Biased BJT Page 615 There is a reason that we are doing all this. We are about to examine the relationshi between the inut and outut side of the BJT. I C (ma) h fe = Figure 12 (a) The Base Side A base current of 3 A roduces a collector current of 3 ma Active Region at Midoint bias ICcontrolled by IB I C = hfei B= 3mA BB I B ( A) I B = 3 A Figure 12 B h FE = 1 C E R C 2k CE 6 CC 12 I = 3 A I = 3. ma = 6. B C CE I C (ma) I C(sat) () CE CE(off) Figure 12 (b) TheCollector side The load line A collector current of 3 ma roduces a Q oint at midoint bias Figure 12 (a) shows the comarison of base current versus collector current. Note that a 3 A base current roduces a3ma collector current when is 1. h FE Figure 12 (b) shows what is going on in the collector circuit. The 3 ma collector current roduces a Q oint in the middle of the load line and is 6. CE Note that the outut characteristics are controlled by the inut current. Now we will use the same tye of analogy using the MPF12 JFET that you have in your kit.

16 Page 616 Electronic Fundamentals II The JFET Oeration Overview Active Region at Midoint bias = I (ma) Figure 13 (a) The Side A of 4.9 roduces a drain current of 3 ma This articular JFET has : (off) = 8 I = 2 ma The Side SS I =3 ma 4.9 G R 2k S S 6 Figure 13 ( ( I = I SS 1 _ 12 (off) 2mA 1 _ = = By Calculation _ 8 2 2mA ( = 3.3 ma ( ( ( 2 I (ma) R S () Figure 13 (b) The rain Side The load line A drain current of 3 ma roduces a Q oint at midoint bias Figure 13 (a) shows an MPF 12 that has a (off) of 8 and an ISS of 2 ma. The transconductance curve has been lotted and aears in Fig. 13 (a). This curve is a comarison of to I. Note that, for this articular JFET, a of 4.9 will roduce a drain current of 3 ma. Note that the transconductance curve is not linear. We will see later that this can cause distortion at the outut when an ac signal is alied. The rain Side Figure 13 (b) shows the load line for this circuit. It is very similar to the load line for the BJT. Ideally, we want the Q oint in the centre of the load line, but we will find that this can be somewhat difficult to achieve.

17 Page 617 The JFET Biasing Methods Biasing Methods For the JFET, we are going to study four different biasing methods Bias, Self Bias, oltage ivider Bias and Current Bias. We will see that each method gets rogressively better at controlling the Q oint of the device. Controlling the Q Point The manufacturing sread for JFETs is much worse than they are for biolar transistors. For this reason, the Q oint can be much harder to control with the JFET. With the 2N394 junction transistor, we saw a beta range of between 1 and 3.This is a3to1sread in range. With the MPF12 JFET we have a I This is a 1 to 1 sread in range. SS range of 2mA to 2 ma. This large range of values of ISS from device to device is what makes the Q oint hard to control.

18 Page 618 Electronic Fundamentals II The JFET Biasing Methods Bias bias is the JFET counterart to base bias with the BJT. A gate bias circuit is shown in Figure 14. The gate suly voltage ( GG) is used to ensure that the gate source junction is reversed biased. Since there is no gate current, there is no voltage droed across R G, and the value of is found as = GG R R L S (similar to CE in base bias) is found as: S = IR R G GG Figure 14 Bias Examles 12.4 and 12.5 exlain gate bias. It is very imortant that you understand both of these examles. Why do we need the resistor R R G We said reviously, that the there is no gate current through R G. Since resistors are usually used to dro a voltage, then why do we need it? R G GG Figure 15(a) Why we need R G R L Figure 15 (b) shows RG removed and relaced with a wire. Now any ac signal from the generator is shorted to ground through the dc source GG. The resistor allows the ac develo across it, making it aear at the gate of the FET. GG R R L R G Figure 15 (b) Removing RG shorts the ac to ground through GG

19 The JFET Biasing Methods Page 619 Self Bias Self Bias is one of the more oular methods of biasing the JFET. = G G R Note that R now goes to ground. G R G S R S R L Note also that RS has been added. Rs hels to roduce the required to Figure 16 Self Bias bias the JFET. In this circuit, the drain current and the source current are the same since all of the drain current asses through the channel and leaves via the source. I S= I This drain current all also asses through RS and a voltage dro will aear across it. =IR S S Note that is the otential measured from the gate () to the source (). The gate is at zero volts since it is at ground otential rough R G. Remember that there is no gate current. Since the source end is at a ositive otential ( = I R ), then is defined by: S S = I R S The negative resistor. is develoed by the current through the source Examle 12.6 and 127 are an examle of Self Bias Calculations.

20 Page 62 Electronic Fundamentals II The JFET Biasing Methods Self Bias Rules for Plotting the Bias Line To lot the dc bias line for self bias, follow this rocedure: 1. Plot the minimum and the maximum transconductance curves for the JFET used in the circuit. 2. Choose any value of and determine the corresonding value of I using the formula: I = 3. Plot the oint determined above and draw a line from this oint to the origin of the grah. 4. The oints where the line crosses the two transconductance curves defines the limits of the Q oint for any of this tye of JFET used in the circuit. RS

21 The JFET Biasing Methods Page 621