Self-Driven Phase Shifted Full Bridge Converter for Telecom Applications

Transcription

1 Self-Driven Phase Shifted Full Bridge Converter for Telecom Alications SEVILAY CETIN Technology Faculty Pamukkale University 7 Kinikli Denizli TURKEY scetin@au.edu.tr Abstract: - For medium ower alications, hase shifted full bridge (PSFB) converter is widely used because of its inherent zero voltage switching (ZVS) turn on feature for rimary switches, oeration at constant switching frequency and simle control rocedure. Using the synchronous rectifier (SR) for secondary side to coe with the high conduction loss is very common esecially in the low outut voltage alications. Two methods are ossible to drive SRs; one is self-driven method using directly secondary side voltage to generate driving signal and the other is active method. Obviously generating driving signal directly from secondary side of ower transformer is easier and has advantage when isolation is requirement and where weight/ower density is imortant. In this work, a self-driven and synchronous rectified PSFB converter for a server adater is roosed. A detailed erformance analysis of self-driver to generate reliable control signals for arallel connected SRs is evaluated. Finally, an exerimental setu oerating at 8kHz and rated 1kW (1V-83A) has been carried out to verify the roosed theoretical analysis and evaluations. Key-Words: - Self-driver, Phase Shifted Full Bridge DC-DC converter, efficiency, synchronous rectifier. 1 Introduction Recently, research in ower converters area has focused on high ower density due to the advantage of cost reduction, limited sace and weight requirements in some alication area like telecom/data centre, electric vehicle/aircraft [1]. Besides, in data centre alication, increasing energy consumtion due to more energy demand and rising energy rice require high efficiency ower conversion. Therefore high efficiency ower conversion is getting more imortant key arameter in converter design in order to save energy and reduce cooling size. Phase shifted full bridge (PSFB) converter is used widely for data centre or telecom alications due to its high conversion efficiency, high ower density, simle control structure and low electromagnetic interface (EMI) []-[1]. PSFB converter is usually used as second stage dc-dc conversion with low outut voltage and high outut current of a two stage systems such as server adater. In these systems, total conversion losses are dominated by rectifier conduction losses at the secondary side. Therefore, synchronous rectifier (SR) is very common way to coe with high conduction losses. In [4], a design evaluation which uses arallel connected SRs in order to obtain best efficiency has been roosed and 99% efficiency has been achieved at 5 khz oeration frequency. However, active gate driver design for arallel connected SRs increases comlexity and makes systems heavy and costly. Self-driving method using directly ower transformer to generate driving signals is more attractive comared to active gate drive method because of its simlicity and easy imlementation. In [11], a self-driving method for low outut voltage and high outut current alications is roosed. In the method, outut current is sensed with a current transformer and added ower conversion circuit delivers sensing current to a DC voltage source. Here, added extra circuit increases comlexity and cost of driver circuit. Otimum design consideration and analysis of synchronous rectified PSFB converter are given in [] and [7]. In this design, using comlex self-driver circuit [1] to drive SRs makes circuit design more comlicated comared to active method. Another method using auxiliary winding to generate driving signals is given in [13], this method is very simle and also rovides conduction of both SRs when rimary voltage is zero during dead time comared to conventional self-driver method using directly secondary voltage of the ower transformer. The erformance of roosed self-driver was evaluated with different transformer designs and validated by a rototye ISBN:

2 rated 5W. However, a detailed erformance analysis taken into consideration of arallel connected SRs, arasitic inductance on the gate line, body diode conduction interval was not evaluated. In this aer, a synchronous rectified PSFB converter design aroach in order to obtain high efficiency for a server adater is resented. Parallel connected SRs are used for centre taed rectifier at the secondary side to reduce high conduction losses. A self-driven circuit is considered to avoid the need for an additional active control circuitry on the secondary. The self-driver method roosed in [13] is alied to generate control signals for the arallel connected SRs. Here, a resonance between large gate caacitance and arasitic inductance on the gate line due to long interconnects to the gate terminals of the SRs can influence the quality of driving signals. Therefore, a detailed erformance analysis taken into account of the ringing on the gate voltage and the body diode conduction is resented. Finally, an exerimental setu has been built for a server adater alication oerating at 8kHz and rated 1kW outut ower to validate roosed theoretical erformance analysis. The rest of aer is organized as follows: Section II gives oeration of ower stages of PSFB converter, Section III evaluates the detailed SR selfdriver analysis, Section IV gives the exerimental results. Section V rovides conclusions and future work. Figure 1 The schematic diagram of PSFB converter with center taed rectifier. Figure Oerational key waveforms of PSFB converter. The Oeration of Phase Shifted Full Bridge DC-DC Converter The schematic diagram of PSFB Converter with a centre taed rectifier is shown in Figure 1. Here, S 1 -S 4 are the rimary side switches and they include antiarallel diodes and arasitic caacitors. SR 1 and SR reresent the arallel connected synchronous rectifier in order to reduce conduction losses. L M is the mutual inductance, L s is the equivalent inductance which is the sum of total leakage inductance and additional inductance connected series to rimary side. TR is the high frequency ower transformer with n turns ratio, L o and C o are outut filter comonents, V in is the inut voltage source and V o is the outut voltage. Stage 1: (t o -t 1 ):In this stage, V in inut voltage is alied to across the rimary of the transformer and rimary current increases linearly from I 1 to I -k. Power is transferred from the inut to the outut. Stage : (t 1 -t ):At the beginning of this mode, S 1 is turned-off so the outut caacitor of the S 1 and S 4 is charged and discharged, resectively. Then converter starts to work in freewheeling mode; rimary side of transformer is short circuited by conduction S 4 MOSFET and antiarallel diode of oosite side S MOSFET. Therefore, there is no ower transfer from the inut to the outut in this interval. The outut current continues to flow through the SR 1 and L o at the secondary side. Thus rimary current sloe in freewheeling mode is determined by outut side. At the end of this stage rimary current reaches i value and the oeration of converter changes for the active stage. Stage 3: (t -t 3 ): At t=t, S is turned-off and S 4 is turned on so outut caacitor of S and S 3 is charged and discharged, resectively. The antiarallel diode ISBN:

3 of S 3 conducts after the outut caacitor of S 3 discharges comletely. Then negative inut voltage, -V in, is alied to the rimary by the change of freewheeling mode to the active mode. During this stage both SR1 and SR are turned on for outut current commutation. Therefore, secondary side of transformer is short circuited and there is no ower transfer from the inut to the outut in this interval. At the beginning, charge/discharge interval is very short so it can be neglected. Thus, rimary current can be written as equal to the reflected outut current for this mode. At the end of this stage rimary current is changed from I to I 1 and the half of one switching eriod is comleted. Remain half cycle oerates with same rincile roosed above but with a changed direction of rimary current and voltage. 3 Self Driven Procedure In this work, a self-driver roosed in [13] is used for arallel connected SRs. The circuit schematic of the self-driven circuit and its oerational waveforms are given in Figure. 3. Here, L e reresents the sum of the leakage inductance of auxiliary winding and stray inductance on the gate line. R g is the series resistor, R is the arallel resistor to the gate terminal of SR, C GS is the equivalent gate-source caacitance of each SR. D 1 and D diodes rovide for low conduction loss during turn-off. G 1 and G are the gate terminal of the arallel connected SRs and S oint is the source terminal. The auxiliary winding is imlemented directly on the ower transformer and reflected rimary voltage to the auxiliary winding is used for the driving voltage. Here, it is suosed that auxiliary winding voltage is constant and equal to the V g or -V g to kee analysis simle. When auxiliary voltage is ositive, uer side caacitor is charged and lower side one is discharged. When lower side caacitor voltage is about zero, v GS is clamed to V D and SR1 is turned on. When there is a voltage transition of the transformer, same current charges the lower side caacitor and discharges the uer side caacitor. Thus SR is turned on and gate of SR1 is clamed to V D1. Figure. 3 The self-driven circuit roosed in [13] and its oerational waveforms. During dead time, discharge of one caacitor charges the other caacitor and both caacitor voltage level can be ket at the same voltage level by using equal arallel balance resistors. Thus gate voltage of both SRs can be ket above the threshold voltage with a roer design while transformer voltage is zero. To evaluate erformance of the self-driver for multile connected SRs, ringing analysis and the body diode conduction analysis is resented below Gate Voltage Ringing Analysis The auxiliary winding leakage inductance and trace inductance due to long interconnections to the gate terminal of the SRs can cause a resonance with large gate caacitance because of the multile arallel connected SRs. Figure 4 defines the simulated resonance situation and shows the ringing occurred at the different stages of the driver oeration. Here, the eak value of the gate voltage should be ket at the reliable value when auxiliary winding has voltage. During dead time, the gate voltage shouldn t turn back to the zero where it should be above threshold voltage at the turn-on and turn-off transitions. The ringing analysis can be evaluated searately while the auxiliary winding has a voltage and for the dead time interval. ISBN:

4 Auxiliary winding has a voltage: The equivalent circuit when auxiliary winding has a voltage is given in Figure 5. The oerational waveforms for this mode are given in Figure 3 for the interval of t - t 1. The gate voltage exressions for each SR can be written as follows according to the equivalent circuit analysis. In the analysis, it is suosed that v (t )=v GS (t )=V th, v g (t )=V g. The maximum value of the gate voltage can be ket at the reliable level by the using of the following exressions. Figure 4 SR gate voltage ringing without daming. In the design of the driver, eak value of the gate voltage of each SR should be lower than maximum gate voltage rate given in datasheet. During the turnoff, the minimum value of the gate voltage should be equal to the voltage dro of the diode which is anti-arallel to the gate terminals. The eak value of the gate voltage can be calculated and lotted as function of R g and R for different L e as shown in Figure 6. Figure 6(a) shows that low leakage inductance or high series gate resistance limits the gate voltage ringing and gate voltage level stays at the same level for different L e above 1.8Ω of R g due to well daming with bigger gate resistors. Decreasing the arallel resistors connected to the gate terminal imroves the gate voltage behaviour while ringing is not well damed by using.1ω of R g as shown in Figure 6(b). However, R value cannot change ringing situation very much so R g and L e are the most imortant key arameters for ringing daming. Figure 5. The equivalent circuit diagram of self driver when the auxiliary winding has a voltage. Vg R v (t) = v (t ) + R + R 1 α (t t ) e ( cosh( (t t ) α 4 β) α 1 sinh( (t t ) α 4 β)) 4 α β g (1) (a) Vg R v GS(t) = v G S(t ) R + R g 1 α (t t ) e ( cosh( (t t ) α 4 β) () α 1 sinh( (t t ) α 4 β)) 4 α β R R C g GS e α = (3) R L C e GS + R + L R g β = (4) L C R e GS Fig. 6. The gate voltage eak value as function of (a) R g and (b) R for different L e values. During the dead time: The equivalent circuit of the gate driver during the dead time is given in Figure 7 and its oerational waveforms between t and t 3 are shown in Figure 3. In this time interval, uer side caacitor starts to discharge and its (b) ISBN:

5 discharge current charges the lower side caacitor. The voltage exressions for this time interval can be written according to the equivalent circuit analysis. The revious interval (t 1 -t ) reresents the steady state oeration of the gate voltage and it is suosed that v (t )=V g -V Rg -V D1, v GS (t )=-V D1 at the beginning of the dead time. Here, V Rg and V D1 reresent the voltage dro of R g and D 1, resectively. The gate voltages exressions for each SR can be written as follows, Figure 7. The equivalent circuit diagram of the self driver during dead time. (Vg VRg V D1)R v (t) = v (t ) R + R 1 α (t t ) e ( cosh( (t t ) α 4 β) α 1 sinh( (t t ) α 4 β) 4 α β g (4) Body diode of the SR conducts when the gate voltage is below the threshold voltage due to delay caused by the resistance and the inductance on the gate line. Thus, conduction of the body diode increases the conduction losses and also creates the extra reverse recovery losses. The obtained equations during the dead time give the gate voltage waveforms to determine turn-on and turn-off delay time. Calculated and lotted rising and falling edge delay times as function of R g for different L e are shown in Figure 8. In the calculations, threshold voltage, V th, for IRFP411Pbf MOSFET is V and five MOSFETs in arallel are used for each SR to extract delay times as function of R g and R. Figure 8(a) shows that increasing L e and R g on the gate line increases rising edge delay time as exected. At the turn-off transition, larger L e shortens the falling edge delay time for same R g as shown in Figure 8(b). However, resonance between C gs and L e cannot be damed comletely for low R g values so falling edge delay time looks short for lower L e values and looks long for larger L e values due to increasing resonance frequency. Here, rising of R g resistor also slows down the discharge of the gate-source caacitance and leads to long delay time for falling edges. v (t) v (t ) (V V V )R g Rg D1 = + G S G S R + R 1 α (t t ) e ( cosh( (t t ) α 4 β) α 1 sinh( (t t ) α 4 β)) α 4β g (5) v (t ) = v G S(t ) Vth (6) In this mode, effects of the driver arameters on the ringing analysis are similar to analysis roosed when auxiliary winding has voltage. The voltage level of the each SR should be above the threshold voltage, V th, after determined turn on delay time, t don and before determined turn off delay time, t doff. Here, turn on delay and turn off delay time should be chosen as short as ossible in order to reduce body diode conduction loss. (a) 3.. Body Diode Conduction Analysis (b) Figure 8. (a) Turn-on and (b) turn-off delay times as function of R g for different L e. ISBN:

6 The imact of the arallel resistors on delay time is calculated and lotted in Figure 9. The rising edge is long for low R values due to limited caacitor charge current and short while R increases as shown in Figure 9(a). Due to the short circuit behaviour of the gate-source caacitance during the turn-on transition, rising edge delay time is not affected very much by the R variation. However, falling edge is affected seriously as shown in the Figure 9(b). The falling edge delay time is very long for low R values and gate voltage cannot dro to the zero under 5Ω. However, increasing R value shortens the falling edge delay time and body diode conduction eriod as well due to extension of caacitor discharge time. Therefore R value should be selected as high as ossible. shown in Figure 1. 4V DC inut voltage is used as inut source. Figure 1. The rototye circuit schematic of synchronous rectified PSFB converter. Measured gate-source voltage waveform for each SR can be shown in Figure 11. The eak value of the gate voltages is accetable; there is no overvoltage which can destroy the switches. The voltage level during dead time is also above the threshold voltage, V. (a) Figure 11. The gate control voltage of each SR. Figure 1 shows extended rising and falling edges of the control signals for SR. At the turn on transition, the gate voltage reaches threshold voltage, V th, in 97ns and at the turn-off transition, gate voltage reaches zero in 134ns after gate voltage dros V th. Therefore body diode conducts before gate voltage reaches threshold voltage at the turn-on transition and after gate voltage dros threshold voltage during turn-off transition. These conduction eriods are very short and measured around %3.3 of the conduction eriod of SR. (b) Figure 9. (a) Turn-on and (b) turn-off delay times as function of R for different L e. 4 Exerimental Results The exerimental setu is built to validate theoretical analysis roosed above. A synchronous rectified PSFB converter for server adater alication with 1V outut voltage, oerating at 8kHz switching frequency and rated 1kW was designed. The exerimental rototye circuit is (a) ISBN:

7 (b) Figure 1. Extended (a) rising and (b) falling edge of the gate control signals. The efficiency comarison for the diode rectified and the synchronous rectified PSFB converter is shown in Figure 13. The measured efficiency of synchronous rectified PSFB converter is 1% higher than diode rectified PSFB converter at full load condition. Figure 13. The efficiency comarison of diode rectified and synchronous rectified PSFB converter. 5. Conclusion A self-driven synchronous rectified PSFB converter design aroach for server adater is roosed. To reduce conduction loss, arallel connected SRs for the centre taed rectifier on the secondary side is discussed. A detailed erformance analysis of a self-driver for arallel connected SRs is roosed in order to obtain the quality and the reliable driving signals. In the analysis, ringing of the gate drive voltage caused by the inductance on the gate line and also body diode conduction are discussed. Finally, analysis is verified by an exerimental setu. In the measurement, obtained driving signals rovide SR conduction in the most of total conduction eriod. Acknowledgement: This work is suorted by Tubitak under grant number of 114E1. References: [1] J. W. Kolar, U. Drofenik, J. Biela, M. Heldwein, H. Ertl, T. Friedli, S. Round, PWM Converter Power Density Barriers, IEEJ Trans. Industrial Alication, Vol.18, No.4, 8, [] C. Zhao, X. Wu, P. Meng, and Z. Qian, Otimum Design Consideration and Imlementation of a Novel Synchronous ectified Soft-Switched Phase-Shift Full-Bridge Converter for Low-Outut-Voltage High- Outut-Current Alications, IEEE Trans. On Power Electronics, Vol.4, No., 9, [3] U. Badstuebner, J. Biela, D. Christen, J. W. Kolar, Otimization of a 5-kW Telecom Phase- Shift DC DC Converter With Magnetically Integrated Current Doubler, IEEE Trans. On Power Electronics, Vol. 58, No.1, October 11, [4] U. Badstuebner, J. Biela, and J.W. Kolar, An Otimized, 99 % Efficient, 5kW, Phase-Shift PWM DC-DC Converter for Data Centers and Telecom Alications, Alied Power Electronics Conference and Exosition (APEC), 1 Twenty-Fifth Annual IEEE, 1-5 February 1, Palm Srings, California, [5] J.W. Kim, D.Y. Kim, C.E. Kim, and G.W. Moon, A Simle Switching Control Technique for Imroving Light Load Efficiency in a Phase- Shifted Full-Bridge Converter with a Server Power System, IEEE Trans. On Power Electronics, Vol. 9, No.4, Aril 14, [6] B. Gu, C.Y. Lin, B. Chen, J. Dominic, and J.S. Lai, Zero-Voltage-Switching PWM Resonant Full-Bridge Converter With Minimized Circulating Losses and Minimal Voltage Stresses of Bridge Rectifiers for Electric Vehicle Battery Chargers, IEEE Trans. On Power Electronics, Vol. 8, No. 1, October 13, [7] C. Zhao, X. Wu, W. Yao, and Z. Qian, Synchronous Rectified Soft-Switched Phase- Shift Full-Bridge Converter with Primary Energy Storage Inductor, Alied Power Electronics Conference and Exosition, 4-8 February 8, Austin/TX, [8] J. Biela, U. Badstuebner, and J.W. Kolar, Design of a 5-kW, 1-U, 1-kW/dm3 Resonant DC DC Converter for Telecom Alications, IEEE Trans. On Power Electronics, Vol. 4, No.7, 9, [9] J. Biela, U. Badstuebner, and J.W. Kolar, Imact of Power Density Maximization on Efficiency of DC DC Converter Systems, IEEE Trans. On Power Electronics, Vol. 4, No.1, 9, [1]M. Xu, Yu. Ren, J. Zhou, and F. C. Lee, 1-MHz Self-Driven ZVS Full-Bridge Converter for 48- V Power Pod and DC/DC Brick, IEEE Trans. On Power Electronics, Vol., No.5, 5, [11]X. Xie, J. C. P. Liu, F. N. K. Poon, and M. H. Pong, A Novel High Frequency Current- Driven Synchronous Rectifier Alicable to Most Switching Toologies, IEEE Trans. On Power Electronics, Vol. 16, No.5, , Setember 1. [1]J M. Zhang, X.G. Xie, D.Z. Jiao, and Zhaoming Qian, A High Efficiency Adater with Novel Current Driven Synchronous Rectifier, Telecommunications Energy Conference, 3-3 Oct. 3, Yokohoma, ISBN:

8 [13]P. Alou, J. A. Cobos, O. García, R. Prieto, J. Uceda, A New Driving Scheme for Synchronous Rectifiers: Single Winding Self- Driven Synchronous Rectification, IEEE Trans. On Power Electronics, Vol. 16, No.6, 1, ISBN: