Design and Implementation of a Novel Multilevel DC-AC Inverter

Transcription

1 This article has been acceted for ublication in a future issue of this journal, but has not been fully edited. Content may change rior to final ublication. Citation information: DOI 1.119/TIA , IEEE Design and Imlementation of a Novel Multilevel DCAC Inverter ChengHan Hsieh, TsorngJuu Liang, Fellow, IEEE, ShihMing Chen, and ShihWen Tsai Abstract In this aer, a novel multilevel DCAC inverter is roosed. The roosed multilevel inverter generates seven levels AC outut voltage with the aroriate gate signals design. Also, the low ass filter is used to reduce the total harmonic distortion of the sinusoidal outut voltage. The switching losses and the voltage stress of ower devices can be reduced in the roosed multilevel inverter. The oerating rinciles of the roosed inverter and the voltage balancing method of inut caacitors are discussed. Finally, a laboratory rototye multilevel inverter with 4 V inut voltage and outut 22 V rms /2 kw is imlemented. The multilevel inverter is controlled with sinusoidal ulsewidth modulation (SPWM) by TMS32LF247 digital signal rocessor (DSP). Exerimental results show that the maximum efficiency is 96.9% and the full load efficiency is 94.6%. Index Terms multilevel, DC to AC inverter, DSP, MPPT I. INTRODUCTION As a result of high technology develoment, the demand and the quality of electric ower is higher than before. Because of the advancement of semiconductor, the secification of ower device and ower conversion technique is romoted. One of the ower converter which can transform DC to AC is called inverter. Inverter is the intermedium which transmit ower to other electrical equiment such as uninterrutible ower suly, servo motor, airconditioning system, and smart grid comose of renewable energy shown in Fig. 1. To satisfy different demands and characteristic of loads, the outut frequency and voltage have to change with different loads [1][3]. In recent years, the amount of ower equiment is increasing. Therefore, the harmonic ollution of ower system become more serious. Several standards and regulations have been formulated to limit quality of harmonics and ower factor of electric equiment such as IEEE Std and UL 1741, etc. [4][6]. Furthermore, the industry demand higher ower alications, the secification of ower device is higher. Although IGBT has features of high ower rating and high voltage stress, it cannot oerate at high frequency. And the design of IGBT gate driver is comlicated. MOSFET is the aroriate comonent to oerate at high frequency, but ower rating is not as good as IGBT. To solve the roblem, many different toology of multilevel use low rating comonent at high ower alication. The urose of multilevel toology is to reduce voltage rating of ower switch. Therefore, it usually use at high ower alication. By combining outut voltages in multilevel form, it has advantages of low dv/dt, low inut current distortion, and lower switching frequency. As a result of advantages of multilevel toology, several toologies have emerged in recent years [7], [8]. A novel multilevel inverter is designed and imlemented in this aer. The major feature of the roosed toology is the reduction of ower comonents. The sinusoidal ulsewidth modulation (SPWM) is used to control roosed circuit by TMS32LF247 digital signal rocessor (DSP). Renewable Energy A. Circuit Configuration Converter Inverter Load Fig 1. Block diagram of renewable system II. POWER STAGE Fig. 2 shows the roosed novel toology used in the sevenlevel inverter. An inut voltage divider is comosed of three series caacitors,, and. The divided voltage is transmitted to Hbridge by four MOSFET, and four diodes. The voltage is send to outut terminal by Hbridge which is formed by four MOSFET. The roosed multilevel inverter generates seven levels AC outut voltage with the aroriate gate signals design. B. Oerating Princiles The required seven voltage outut levels ( 1/3V dc, 2/3V dc, V dc, ) are generated as follows: 1) To generate a voltage level = 1/3V dc, is turned on at the ositive half cycle. Energy is rovided by the caacitor and the voltage across Hbridge is 1/3V dc. and is turned on and the voltage alied to the load terminals is 1/3V dc. Fig. 3 shows the current ath at this mode. 2) To generate a voltage level = 2/3V dc, and are turned on. Energy is rovided by the caacitor and. The voltage across Hbridge is 2/3V dc. and is turned on and the voltage alied to the load terminals is 2/3V dc. Fig. 4 shows the current ath at this mode. 3) To generate a voltage level = V dc, and are turned on. Energy is rovided by the caacitor,, and. The voltage across Hbridge is V dc. and is turned on and the voltage alied to the load terminals is V dc. Fig. 5 shows the current ath at this mode. 4) To generate a voltage level = 1/3V dc, is turned on at the negative half cycle. Energy is rovided by the caacitor and the voltage across Hbridge is 1/3V dc (c) 215 IEEE. Personal use is ermitted, but reublication/redistribution requires IEEE ermission. See htt:// for more information.

2 This article has been acceted for ublication in a future issue of this journal, but has not been fully edited. Content may change rior to final ublication. Citation information: DOI 1.119/TIA , IEEE and is turned on and the voltage alied to the load terminals is 1/3V dc. Fig. 6 shows the current ath at this mode. 5) To generate a voltage level = 2/3V dc, and are turned on. Energy is rovided by the caacitor and. The voltage across Hbridge is 2/3V dc. and is turned on, the voltage alied to the load terminals is 2/3V dc. Fig. 7 shows the current ath at this mode. 6) To generate a voltage level = V dc, and are turned on. Energy is rovided by the caacitor,, and, the voltage across Hbridge is V dc. and is turned on, the voltage alied to the load terminals is V dc. Fig. 8 shows the current ath at this mode. 7) To generate a voltage level =, and are turned on. The voltage alied to the load terminals is zero. Fig. 9 shows the current ath at this mode. Table I lists the switching combinations at different outut levels. V dc 2/3V dc 1/3V dc Fig. 4. Switching combination of outut voltage level 2/3V dc. 1/3V dc V dc V dc 1/3V dc V ab Load 1/3V dc Fig. 2. Proosed sevenlevel inverter toology. 2/3V dc 1/3V dc V dc Fig. 5. Switching combination of outut voltage level V dc. 2/3V dc 1/3V dc Fig. 3. Switching combination of outut voltage level 1/3V dc. V dc 2/3V dc 1/3V dc Fig. 6. Switching combination of outut voltage level 1/3V dc (c) 215 IEEE. Personal use is ermitted, but reublication/redistribution requires IEEE ermission. See htt:// for more information.

3 This article has been acceted for ublication in a future issue of this journal, but has not been fully edited. Content may change rior to final ublication. Citation information: DOI 1.119/TIA , IEEE V dc 2/3V dc 1/3V dc Fig. 7. Switching combination of outut voltage level 2/3V dc. Outut voltage TABLE I SWITCHING COMBINATIONS REQUIRED TO GENERATE THE SEVENLEVEL OUTPUT VOLTAGE WAVEFORM Switching combinations 1/3V dc on off off off on off off on 2/3V dc on off off on on off off on V dc on on off off on off off on 1/3V dc off on off off off on on off 2/3V dc off on on off off on on off V dc on on off off off on on off V dc off off off off on off on off 2/3V dc 1/3V dc Fig. 8. Switching combination of outut voltage level V dc. V dc 2/3V dc 1/3V dc Fig. 9. Switching combination of outut voltage level. B. Toology Comarison Table II resents the number of comonents required to imlement a sevenlevel inverter using the roosed toology and three reviously ones [9], [1]: that can be considered as the standard multilevel configurations, the diodeclamed inverter, the caacitorclamed inverter, and the cascaded multicell inverter. Table II shows that the new toology achieve the reduction in the number of ower devices. Table III shows the voltage stress comarison between different tye inverters. TABLE II COMPONENTS COMPARISON BETWEEN FOUR DIFFERENT SEVENLEVEL INVERTERS sources caacitors Clamed caacitors Power switches Proosed Diodeclamed Caacitor Clamed Cascaded multicell Diodes 4 1 TABLE III VOLTAGE STRESS COMPARISON BETWEEN FOUR DIFFERENT SEVENLEVEL INVERTERS sources caacitors Power switches Proosed Diodeclamed Caacitor Clamed Cascaded multicell 2 2 /3 /3 /3 /2 /3 /3 /3 /3 Diodes 2/3 3/2 N/A N/A (c) 215 IEEE. Personal use is ermitted, but reublication/redistribution requires IEEE ermission. See htt:// for more information.

4 This article has been acceted for ublication in a future issue of this journal, but has not been fully edited. Content may change rior to final ublication. Citation information: DOI 1.119/TIA , IEEE III. VOLTAGE BALANCING CIRCUIT BASED ON RSCC Since the voltage deviation causes larger harmonics distortion in the outut voltage, voltage balancing circuits are indisensable for the caacitors in the multilevel inverters [11][15]. By using resonant switching caacitor converter, the voltage balance of inut caacitors is achieved. Fig. 1 shows the circuit configuration of a unit of the RSCC. The duty cycle of every switch is equal to 5%. The voltage of is higher than the voltage of. Since the average current of is higher than that of at one switching cycle, most of the charges flow from to. After few switching cycles, the voltage of and are equal. Fig. 11 shows the waveforms of the RSCC. S b1, S b3 S b2, S b4 i r v Cr i C1 DV V dc L r C r i r S b1 S b2 S b3 S b4 i C1 i C2 Fig. 1. Circuit configuration of RSCC. IV. APPLICATION OF SPWM In this aer, several triangular carriers are distributed by hase disosition technique. The advantage of hase disosition technique are uncomlicated to realize and less total harmonic distortion [16], [17]. These carriers comare with a reference sine waveform v sin to get signal of switches. The eaktoeak value of triangular carrier Vˆtri is.the frequency of carrier is switching frequency of inverter. The eak value of reference Vˆ sine sin wave is, and the modulation index m A is defined as: According to (1), the relationshi between the eak value of outut sine wave and m A can be exressed as: Fig. 13 shows the reference sine wave, carriers, and control signals of switches. The method to determine switch signals in Fig. 12 are as follow: (a) v sin < and v sin > v tri2 is turned on (b) v sin > v tri4 is turned on (c) v sin < v tri8 is turned on (d) v sin > v tri8 is turned on (e) v sin > and v sin < v tri1 is turned on (f) v sin < v tri3 is turned on (g) v sin > v tri6 is turned on (h) v sin < v tri6 is turned on Vˆ sin v tri2 m A Vˆsin 3 Vˆ tri V m V o A dc v sin (1) (2) i C2 t 1 t 2 t 3 t 4 t 5 t 6 Fig. 11. Waveforms of RSCC. t 7 v tri4 Vˆtri v tri8 v tri6 Fig. 12 shows the configuration of roosed sevenlevel inverter with RSCC. To aly RSCC at sevenlevel configuration, two switches S b5 and S b6, resonant inductor L r, and resonant caacitor C r are added. In this alication, switches S b1, S b3, and S b5 are turned on at the same time; S b2, S b4, and S b6 are turned on at the same time. The duty of each switch is equal to 5%. v tri3 v tri1 RSCC S1 Sb1 S3 Lr1 Sb2 C1 D1 D3 S5 S7 Vdc Cr1 Sb3 Sb4 C2 Load Lr2 Cr2 Sb5 C3 S4 D2 S6 S8 Sb6 D4 Sb1 Sb3 Sb5 S2 Sb2 Sb4 Sb6 Fig. 12. The roosed multilevel inverter with RSCC. q 1 q 2 q 3 q 4 q 5 q 6 q 7 q 8 2 Fig. 13. Reference sine wave, carriers, and control signals of switches (c) 215 IEEE. Personal use is ermitted, but reublication/redistribution requires IEEE ermission. See htt:// for more information.

5 This article has been acceted for ublication in a future issue of this journal, but has not been fully edited. Content may change rior to final ublication. Citation information: DOI 1.119/TIA , IEEE V. PI CONTROL USED IN MODIFIED SPWM Modified SPWM based on PI control is used in this aer [18], [19]. Fig. 14 shows the block diagram of PI control. The block diagram can be exressed in S domain as: K u( s) [ K i ] e( s) s from (11), the equation can be transformed in Z domain as: Ki u( z) [ K ] e( z) 1 1 z (11) (12) then transform (12) become difference equation is exress as: u[ n] K e[ n] K e[ n] K e[ n 1] u[ n 1] (13) Fig. 15 shows system configuration and control block. System detects outut voltage first, and comares this signal with a builtin reference. Then, the system feedbacks an error to PI controller. Finally, the PI controller exorts a control signal to gate driver. K v ref e u u i K i /s Antiwindu Inverter u e e[n3] K1 eriod e[n] K eriod Fig. 16. Schematic of modified SPWM. v ref [n] is defined as the reference outut voltage, [n] is the feedback of outut voltage, and e[n] is error between reference outut and feedback outut which is exressed as (14): e[ n] v [ n] v [ n] ref o (14) let K 1 =K K i, K 2 =K, then made e[n] multilied by K 1 and e[n 3] multilied by K 2. Then add the revious outut signal u [n3]. Finally, it can get the outut of PI controller after rocess by the antiwindu. u' [ n] K1 e[ n] K2 e[ n 3] u'[ n 3] (15) Fig. 14 Block diagram of PI control. VI. EXPERIMENT RESULTS A TMS32LF247A DSP is used to verify the roosed sevenlevel inverter. Table IV shows the characteristics of the inverter. Fig. 17 shows the rototye of the sevenlevel inverter. This rototye consist of detect, gate driver, DSP, RSCC, and sevenlevel inverter. Load TABLE IV THE SPECIFICATION OF THE PROPOSED INVERTER voltage V dc 4 V SPWM Outut voltage Rated outut ower P o Switching frequency f s 22 V rms 2 kw 18 khz u Antiwindu u PI Control e v ref Fig. 15. Sevenlevel inverter with control algorithm. The main idea of modified SPWM is to record the revious error of outut voltage, and generate a suitable correction at the latest cycle. Because the frequency of carrier is 18 khz and the frequency of outut sine wave is 6 Hz, the number of times of switching is 3 times. Fig. 16 shows schematic of modified SPWM. Fig. 17. Exerimental setu for the rototye (c) 215 IEEE. Personal use is ermitted, but reublication/redistribution requires IEEE ermission. See htt:// for more information.

6 This article has been acceted for ublication in a future issue of this journal, but has not been fully edited. Content may change rior to final ublication. Citation information: DOI 1.119/TIA , IEEE Fig. 18 resents the outut voltage waveform v ab showing the desired seven voltage levels and outut waveform. The seven voltage levels in the figure are 133 V, 267 V, 4 V, V. Fig. 19 and 2 show the outut waveform harmonic sectrum calculated by ower analyzer YOKOGAWA WT3 with a rorietary FFT rogram, and the high frequency comosition is attenuated by LC low ass filter. V C2 v gs1 v ab V C2 (5 V/div), (2 V/div), (1 A/div) Fig. 21. Waveforms of v C2,, and at 1 W V C2 v gs1 (2 V/div), v ab, (5 V/div), (5 A/div), Fig. 18. Waveforms of v gs1, v ab,, and at 5 W V C2 (5 V/div), (2 V/div), (1 A/div) Fig. 22. Waveforms of v C2,, and at 2 W Multilevel structure is usually used in inductive loads such as motor. Thus, this aer alies the roosed toology in inductive load. Fig. 23 shows the test block diagram. The inductor and the resistor are connected in series, and PF is set at.95. Fig. 24 shows the outut voltage and current at 4 VA. The THD of outut voltage is 3.3%. Inductive load Fig. 19. Outut voltage harmonic sectrum of vab calculated by FFT. DC source RSCC Multilevel inverter LC filter L i R i Fig. 23. Test block diagram of inductive load. Fig. 2. Outut voltage harmonic sectrum of calculated by FFT. Fig. 21 shows caacitor voltage V C2, outut voltage, and outut current at 1 W. In this figure, the caacitor voltage is 133 V. Thus, the function of voltage balancing is achieved. Fig. 22 shows caacitor voltage V C2, outut voltage, and outut current at 2 W. The THD of outut voltage is.9%. (5 V/div), (5 A/div) Fig. 24. Waveforms of and at 4 VA. The efficiency at different outut ower is showed in Fig. 25. The outut ower is from 2 W to 2W. The highest efficiency is 96.9% at 8 W, and the lowest is 94.6% at 2 W. The efficiency is always above 94.5% (c) 215 IEEE. Personal use is ermitted, but reublication/redistribution requires IEEE ermission. See htt:// for more information.

7 This article has been acceted for ublication in a future issue of this journal, but has not been fully edited. Content may change rior to final ublication. Citation information: DOI 1.119/TIA , IEEE η(%) Po(W) Fig. 25. The efficiency of the roosed inverter. VII. CONCLUSION A novel sevenlevel inverter is designed and imlemented with DSP in this aer. The main idea of the roosed configuration is to reduce the number of ower device. The reduction of ower device is roved by comare with traditional structures. Finally, a laboratory rototye of sevenlevel inverter with 4 V inut voltage and outut 22 V rms /2 kw is imlemented. Exerimental results show that the maximum efficiency is 96.9% and the full load efficiency is 94.6%. vol. 57, no. 7, , 21. [13] Suroso and T. Noguchi, New Generalized Multilevel CurrentSource PWM Inverter with NoIsolated Switching Devices, in Proc. IEEE PEDS, , 29. [14] J. Selvaraj and N. A. Rahim, Multilevel Inverter For GridConnected PV System Emloying Digital PI Controller, IEEE Trans. on Industrial Electronics, vol. 56, no. 1, , 29. [15] N. A. Rahim, K. Chaniago, and J. Selvaraj, SinglePhase SevenLevel GridConnected Inverter for Photovoltaic System, IEEE Trans. on Industrial Electronics, vol. 58, no. 6, , 211. [16] N. Vazquez, H. Loez, C. Hernandez, E. Vazquez, R. Osorio, and J. Arau, A Different Multilevel CurrentSource Inverter. IEEE Trans. on Industrial Electronics, vol. 57, no. 8, , 21. [17] K. A. Tehrani, I. Rasoanarivo, H. Andriatsioharana, and F. M. Sargos, A new multilevel inverter model NP without claming diodes, in Proc. IEEE IECON, , 28. [18] G. Ceglia, V. Grau, V. Guzman, C. Sanchez, F. Ibanez, J. Walter, A. Millan, and M. I.Gimenez, A New Multilevel Inverter Toology, in Proc. Devices, Circuits and Systems, vol. 1, , 24. [19] D. A. B. Zambra, C. Rech, and J. R. Pinheiro, Comarison of Neutral PointClamed, Symmetrical, and Hybrid Asymmetrical Multilevel Inverters, IEEE Trans. on Industrial Electronics, vol. 57, no. 7, ,21 REFERENCES [1] R. Gonzalez, E. Gubia, J. Loez, and L. Marroyo, Transformerless SinglePhase MultilevelBased Photovoltaic Inverter, IEEE Trans. on Industrial Electronics, vol. 55, no. 7, , 28. [2] S. Daher, J. Schmid, and F. L. M. Antunes, Multilevel Inverter Toologies for StandAlone PV Systems, IEEE Trans. on Industrial Electronics, vol. 55, no. 7, , 28. [3] W. Yu, J. S. Lai, H. Qian, and C. Hutchens, HighEfficiency MOSFET Inverter with H6Tye Configuration for Photovoltaic Nonisolated AC Module Alications, IEEE Trans. on Power Electronics, vol. 26, no. 4, , 211. [4] R. A. Ahmed, S. Mekhilef, and W. P. Hew, New multilevel inverter toology with minimum number of switches, in Proc. IEEE TENCON, , 21. [5] M. R. Banaei and E. Salary, New Multilevel Inverter with Reduction of Switches and Gate Driver, in Proc. IEEE IECC, , 21. [6] N. A. Rahim, K. Chaniago, and J. Selvaraj, SinglePhase SevenLevel GridConnected Inverter for Photovoltaic System, IEEE Trans. on Industrial Electronics, vol. 58, no. 6, , 211. [7] K. Hasegawa and H. Akagi, A New DCVoltageBalancing Circuit Including a Single Couled Inductor for a FiveLevel DiodeClamed PWM Inverter, IEEE Trans. on Industrial Alications, vol. 47, no. 2, , 211. [8] T. Ito, M. Kamaga, Y. Sato, and H. Ohashi, An Investigation of Voltage Balancing Circuit for DC Caacitors in DiodeClamed Multilevel Inverters to Realize High Outut Power Density Converters, in Proc. IEEE ECCE, , 21. [9] A. Shukla, A. Ghosh, and A. Joshi, FlyingCaacitorBased Choer Circuit for DC Caacitor Voltage Balancing in DiodeClamed Multilevel Inverter, IEEE Trans. on Industrial Electronics, vol. 57, no. 7, , 21. [1] C. L. Xia, X. Gu, T. N. Shi, and Y. Yan, NeutralPoint Potential Balancing of ThreeLevel Inverters in DirectDriven Wind Energy Conversion System, IEEE Trans. on Energy Conversion, vol. 26, no. 1,. 1829, 211. [11] K. Sano and H. Fujita, VoltageBalancing Circuit Based on a Resonant SwitchedCaacitor Converter for Multilevel Inverters, IEEE Trans. on Industrial Alications, vol. 44, no. 6, , 28. [12] J. Rodriguez, S. Bernet, P. K. Steimer, and I. E. Lizama, A Survey on Neutral Point Clamed Inverters, IEEE Trans. on Industrial Electronics, (c) 215 IEEE. Personal use is ermitted, but reublication/redistribution requires IEEE ermission. See htt:// for more information.