FAULT CURRENT CALCULATION IN SYSTEM WITH INVERTER-BASED DISTRIBUTED GENERATION WITH CONSIDERATION OF FAULT RIDE THROUGH REQUIREMENT

Transcription

1 FAULT CURRENT CALCULATION IN SYSTEM WITH INVERTER-BASED DISTRIBUTED GENERATION WITH CONSIDERATION OF FAULT RIDE THROUGH REQUIREMENT Dao Van Tu 1, Surachai Chaitusaney 2 1 PhD, Electrical Engineering, Hanoi University of Sicence and Technology, Hanoi, Vietnam, tudvhtd@gmail.com 2 PhD, Electrical Engineering, Chulalongkorn University, Bangkok, Thailand, surachai.c@chula.ac.th Abstract Received Date: May 28, 213 The challenge of fault current calculation in a system with inverter-based distributed generation is emhasized by the fault ride through requirement announced in recent grid codes. This aer rooses an algorithm to calculate fault current in such a system. The algorithm adats the conventional fault calculation technique with the utilization of a ower flow-based algorithm. The accuracy of the roosed algorithm is tested by a Matlab/Simulink simulation on a simle system. Keywords: Fault calculation, Fault ride through requirement, Inverter-based distributed generation, Newton-Rahson, Power flow. I. Introduction There have been considerable efforts directed to the develoment of solution models and algorithm for synchronous, induction, and doubly-fed induction generators with great success and wide alication [1]-[4]. However, comaratively fewer solutions have been develoed for inverter-based distributed generation (IBDG) which is a ackage of a distributed generation (DG) and inverters or static ower converters. In addition, most ublications concerning IBDGs have not received high unanimity. Some authors roosed a model and an algorithm to cature the fault resonse of IBDG during the fault eriod but they did not concern the control system of the IBDG [5]. Such algorithm is not convenient to build a calculation tool for setting rotective devices that needs the flexibility for many fault cases. The fault resonse in the time-variant curve fashion of an IBDG has a similar limitation [6]-[8]. Some authors derived IBDG models for fault calculation with dee insight views on the transfer functions of the control system [9]. Unfortunately, those models are suitable for an inverter-only microgrid instead of a grid with arallel oerations of the IBDG and the utility source. In addition, desite being required, according to standard the [1], to hysically fast disconnect IBDGs from the grid in a fault event, fault current calculation in systems with IBDG is reasonable to calculate the fault current to catch u with the fault ride-through (FRT) requirements in some new grid codes [11]-[12]. These grid codes require an IBDG to have a caability of assing through a fault signed by voltage at the oint of common couling (PCC). As such, the IBDG continues to feed current during a fault instead of fast shutting down and isolating itself. Therefore, the growing need of both DG owners and distribution comanies for more comlete studies has motivated the develoment of solutions to calculate the fault current in the system with IBDGs with consideration of fault ride through requirement. ASEAN Engineering Journal Part A, Vol 2 No 2, ISSN X.14

2 The objective of this aer is to roose an accurate fault current calculation method in a system with IBDGs, serving for DG imact evaluation and rotective device settings of both utility and DG rotection systems. The rest of this aer is organized as follows. Section II briefly introduces the fault ride through requirement for a grid connected distributed generation. Then, fault resonse of an IBDG is firstly analyzed in Section III in order to model this generator for a fault calculation method. Based on this model, Section IV rooses an adative algorithm to calculate the fault current in distribution networks with IBDGs with consideration of the fault ride through requirement. This algorithm is validated in Section V by using a time-variant simulation on a simle ower system. II. Fault Ride Through Requirement Generating lants should make a contribution to network suort in not only normal oeration but also transient states as an uward tendency. To carry out that mission, generating lants must be connected in an event of network disturbances and contribute a dynamic suort to the utility system if ossible. The way of assing through the fault or other disturbances, which cause the voltage change at the oint of common couling (PCC), without being disconnected from the network, is called fault ride through caability. Most grid codes are issued for transmission networks. Some of them, e.g. from Ireland [11] and Germany [12], have secific fault ride through (FRT) requirement for distribution networks to which DGs enveloed by this aer are connected. The FRT and the dynamic network suort requirements are briefly summarized in this section aiming to bring the research closer to the industrial ractice. There is usually a distinction between synchronous machine-based DG (SBDG) and other DG tyes. For instance, German grid code clarifies DG into two tye: tye-1 and tye-2 generating unit. A tye-1 generating unit is an SBDG which is connected directly to the network. All others generating lants, e.g. wind turbines, PV systems, fuel cells, are tye-2 generating units. General requirements of FRT caability in distribution networks are as the following technical terms. to remain connected to the network in the event of network faults. to feed a reactive current into the network to suort the network voltage during a network fault. the reactive ower absorbed from the medium-voltage network after the fault have to be less than the absorbed reactive ower rior to the fault. These terms are detailed as FRT curves for all generators and dynamic network suort requirement for tye-2 generator units. 2.1 Fault Ride Through Curves The first term is detailed in the fashion of FRT curves, e.g., curves for tye-2 generator units from Irish grid code in Figure 1. If voltage at the PCC dros to a value above the borderline, the DG must remain connected to the network. For instance, wind farm ower station tyes B, C, D, and E must remain connected during the first 625 ms if even voltage dros at value of 15%. For the next duration from 625 ms to 1 ms, if the voltage recovers linearly from 15% to 4%, the wind farm must not be disconnected from the network. After this duration, if the voltage dros at the value less than 8%, the wind farm can be disconnected. ASEAN Engineering Journal Part A, Vol 2 No 2, ISSN X.15

3 Voltage, % Time, ms Irish tye A Irish tye B, C, D, E Dynamic Network Suort Figure 1. FRT curves from Irish grid code [11] The renewable-based generating lants with tye-2 generating units are being required to lay a role more actively in ower systems to which they are connected. One of them is about network suort in an event of a voltage dro of more than 1% of the effective value of the generator voltage so that not only remaining connection but also injecting reactive current is required. For instance, Irish and German grid codes require a renewable-based DG to rovide reactive current at the low voltage side of the generator transformer with a contribution of at least 2% of the rated current er ercent of the voltage dro. It can be assumed that the renewable-based DG sulies a reactive current I G of 1% of the rated current I G,rated as given by (1). G G, rated VG 2 I I (1) where VG is the angle of the generator terminal voltage. The maximization of reactive current shall continue for at least 6 ms or until the distribution system voltage recovers within the normal oerational range of the distribution system. III. Model of an IBDG during Fault This section firstly analyzes the resonse of an IBDG during fault with consideration of fault ride through requirement. Based on this analysis, a convenient model of the IBDG is roosed for a fault calculation algorithm in the next section Resonse of an IBDG during Fault A tyical structure of an IBDG consists of a control system, whose inuts are voltages and currents at the inverter terminal and the PCC, a modulation generator, an inverter, and a filter circuit as shown in Figure 2 [13]-[16]. The rimary energy is converted into electrical energy in the fashion of dc voltage directly by PV cells, storage batteries, or indirectly by a ackage of ower generators and rectifiers. The inverter converts this dc voltage into an ac voltage at the aroriate frequency and magnitude, as secified by the ower system. The inverter is controlled by signals from a Pulse-width Modulation (PWM) or a Sace Vector Pulse-width Modulation (SVPWM) generator. The IBDG in this aer is controlled by a selected control system as follows. Under normal condition, the ower controller estimates the reference current to control at the IBDG ASEAN Engineering Journal Part A, Vol 2 No 2, ISSN X.16

4 terminal so that the ower outut is around the reference value P ref +jq ref. After assing through the current limiter, this reference current is used in the current controller to estimate the reference signal for the PWM generator to control the firing angle of the thyristors inside the inverter. There are two cases that may occur: Case 1: The reference current after the ower controller is under the limit of the current limiter (I thres ) Case 2: The reference current exceeds the limit I thres. PWM Current controller abc dqo θ abc U PWM, ref abc I inv, ref dq I inv, ref, lim V dc L f (IBDG current) Cf Current limiter + Three-hase three-leg inverter dq I inv, ref P ref Power controller I inv Q ref I inv,dq I,dq V,dq LC filter dqo θ abc P ref +jq ref I inv,abc I,abc PLL Bus Grid V,abc Figure 2. Control system with fault ride through caability of an IBDG In Case 1, the current is controlled so that the outut ower is around P ref +jq ref ; whereas, the current must be limited in Case 2 in order to rotect the ower electronic devices from thermal damage. The limited current I inv,sat is designed to satisfy the network suort requirement. This means, I inv,sat lags the voltage at the IBDG terminal by an angle ranging from to /2. As assumed in [17], the IBDG only resonds to the ositive-sequence of the IBDG terminal voltage. Thus, the IBDG current is symmetrical even the hase voltages are unsymmetrical. In other words, the IBDG contributes balanced hase currents under both balanced and unbalanced fault conditions. Regarding the absolute value of I inv,sat, the common maximum value is 2.u. in IBDG rating. However, most DG oerators refer the rated current I rated if the IBDG is required to suort the maximum reactive current to the system. The limited current I inv,sat is thus given by (1) Model of an IBDG for Fault Calculation An IBDG can be simly reresented as a constant ower or current source deending on the estimated reference current I inv,ref. When a fault occurs, an IBDG is modeled as a constant PQ source in the ositive-sequence network. The comarison between I inv,ref and I thres in the ositive-sequence values instead of hase values is accetable because the control system filters out other comonents before ushing them to the current limiter. If the reference current I inv,ref given by (2), which is estimated by the exected ower (P ref +jq ref ) and the ositive-sequence voltage at the IBDG terminal during fault (V G ), exceeds a threshold value I thres, the IBDG is switched to constant current mode I inv,sat. I P jq (2) ref ref inv, ref jc * f VG VG Providing that the dynamic network suort requirement is considered, the IBDG is controlled to inject a fully reactive current I inv,sat into the utility system to satisfy the DSOs ASEAN Engineering Journal Part A, Vol 2 No 2, ISSN X.17

5 requirement. Consequently, the IBDG is only modeled by the deendant current source in arallel with the filter caacitor C f as shown in Figure 3. The limited current is defined by (3) where /2. In case of fully reactive suort, = /2. I inv,sat = I rated V - ) Bus Fault I inv,sat Cf Bus k Grid V Figure 3. Model of an IBDG under fault condition inv, sat inv, sat V I I (3) Although the FRT requirement requires the reactive current injected to Bus, the current controlled before the caacitor C f as shown in Figure 3 can be accetable. This is because the difference between current before and after the C f is small. The inclusion of C f in the model is to reflect more accurately the oeration of the IBDG. IV. Fault Calculation Algorithm The flow chart of the adative fault calculation can be reresented by Figure 4 (a). This algorithm is based on the conventional technique which is short of taking the IBDG into account. The adatation comes from the stage of calculating the ositive-sequence voltages as exlained by Figure 4 (b). After estimating all sequence currents at the faulted bus based on the sequence network connection, sequence voltage at all buses are determined indeendently based on the corresonding sequence network. Line currents are then calculated from the three sequence comonents based on the suerosition method. The adated section comared to the conventional fault calculation technique is detailed in Figure 4 (b). This algorithm starts with forming a sequence network connection, which is circuited from ositive, negative, and zero-sequence networks and based on what the fault tye is. Unlike the conventional technique, the sequence network connection here is modified so that the ositive-sequence network is not relaced by an equivalent imedance; whereas, the circuit consisting of the equivalent zero-sequence imedance Z kk, the equivalent negative-sequence imedance Z 2 kk, and the fault imedance Z f, is relaced by an equivalent imedance Z eq. In case of a three-hase fault, only ositive-sequence network is used and Z eq is equal to Z f. Another examle is illustrated in Figure 5 where Z eq is determined by (4). Z eq 2 kk kk 3 f Z Z Z Z Z Z 2 kk kk 3 f System reresentations such as lines and transformers are similar to those in the conventional method. However, all loads of the system should be reresented by constant imedances based on the refault voltages in order to reflect the effect of voltage on load demand during fault. The IBDG is modeled as a PQ source in the first iteration and occuies in only the ositive-sequence network as modeled in Fig. 4. The model is switched to a current source (3) if one of the two conditions (5) and (6) occurs. (4) ASEAN Engineering Journal Part A, Vol 2 No 2, ISSN X.18

6 Positive, negative and zero-sequence networks Modified sequence network connection Power flow algorithm Positive voltages Voltage and current at the fault oint Line currents (a) Differenene Same as the conventional fault calculation Same as the conventional fault calculation Modified Seq.network connection Formation of admittance matrix Y bus Initial solution New current source? No Power mismatch calculation Test for convergence No Jacobian matrix calculation Udate solution (b) Mark the bus with new current source Yes Udate Y bus Yes Positive-sequence voltages End rogram. Figure 4. Adative fault calculation Transmission system Synchronous gen. IBDG I inv,sat Positive sequence network Slack bus Bus k + Slack bus P ref + jq ref C f N L Bus 1 V k 1 I k Equivalent imedance Z eq Negative-seq. + Zero-seq. + network network 2 I k 2 V k I k 3Z f V k Figure 5. Modified sequence network connection for a double line-to-ground fault I ref I thres (5) V PCC < V limit (6) where I ref is the reference current exected at the outut of the IBDG and given by (2); I thres indicates the threshold current of the control system of the IBDG as detailed in [17], V PCC indicates the ositive-sequence voltage at the PCC of the IBDG, and V limit indicates the voltage limit acceted for a normal condition. The admittance matrix Y bus of the modified sequence network connection is erformed similarly to the Y bus formulation in a ower flow algorithm. Newton-Rahson iteration technique is emloyed to comute ositive-sequence comonents of bus voltages. The Jacobian matrix is comuted based on the formulated Y bus. At IBDG bus, the diagonal elements are adated as follows. The Kirchhoff Current Law at Bus can be exressed as (7). n I Y V (7) q1 q q ASEAN Engineering Journal Part A, Vol 2 No 2, ISSN X.19

7 On the other hand, the current I can be comuted by using (8). I P jq inv, sat I V (8) where is the hase of the current source reresenting the IBDG; V is the olar form of the voltage at Bus ; P +jq is the entering ower estimated at Bus (not including IBDG ower). Assuming that the hase of I inv,sat lags V by an angle, this relation can be exressed as (9). (9) Substituting (7) for I and (9) for in (8), and searate the real and imaginary arts, the estimated active and reactive ower at Bus are given by (1) and (11), resectively. n inv, sat q q cos q q cos q1 P V V Y V I (1) n inv, sat q q sin q q sin q1 Q V V Y V I (11) Obviously, the IBDG reresentation as a current source causes the diagonal elements of submatrices J 2 and J 4 to be changed as shown in (12)-(13). Diagonal elements of the submatrix J 2 : P V n inv, sat q q q q (12) q 2V Y cos V Y cos I cos Diagonal elements of the submatrix J 4 : Q V n inv, sat q q q q q 2V Y sin V Y sin I sin (13) After switching an IBDG to a current source, the algorithm restarts because the bus admittance matrix needs udating with C f and the Jacobian matrix needs changing in the diagonal elements. The maximum number of restarting is equal to the number of IBDG in the system. Direct results from the algorithm are ositive-sequence voltages at all buses including the faulted bus k. The circuit comrising Z kk, Z 2 kk, and Z f is firstly solved with the known V 1 k to obtain all sequence comonents of the fault current I k, I 1 k, and I 2 k at the fault bus k. From this stage, calculation of negative and zero-sequence voltages at all buses is in a similar way to the conventional fault calculation because the IBDG does not articiate in these sequence networks. Combining with the ositive-sequence voltages that have been obtained from the algorithm, bus sequence voltages are used to comute line sequence currents. Lastly, these line sequence currents are suerosed to generate line currents during fault. ASEAN Engineering Journal Part A, Vol 2 No 2, ISSN X.2

8 V. Case Study This section utilizes the roosed algorithm in Section III to test a simle system with an IBDG. The accuracy of the result is validated by a simulation using Matlab/Simulink. The simulation illustrates the fault ride through caability of the IBDG during fault. 5.1 Tested System The simle system has one IBDG connected to Bus 4, which is a low voltage bus of a ste u transformer. The system is deicted by a single-line diagram in Figure 6. System arameters are as follows. Grid: V 1 = 6 kv, Z sc,grid = Ω, Z line1 =.72 + j2.7 Ω, Z line2 =.5 Z line1, P load + jq load = 1 + j.5 MVA Transformer:.8 MVA, 6kV/38V, Yn/D11, R =.2.u, X =.8.u (in transformer rating). IBDG: S nom =.55 MVA, P ref =.5 MW, Q ref = MVAr, I thres = 1.5.u., I inv,sat = 1.u., (in IBDG rating), C f = 9 μf, L f =.85 mh. = IBDG I inv (IBDG current) L f P ref +jq ref Δ C f 4 38V/6kV 3 Line 1 2 Line 2 P load +jq load 6 kv 1 Trans. system 5.2. Results from the Simulation Figure 6. Simle system with an IBDG The Simulink is emloyed to simulate the system in Figure 6. At time t=2 s, a double line-to-ground fault occurs at Bus 3 through a ground imedance Z f =.2 Ω. The following sections exlain the system model and refault conditions before showing the fault current results obtained from a Simulink simulation Power System Model in Simulink The IBDG has a selected control system in Figure 2. Four main elements inside the Simulink model are line, transformer, transmission system, and load. They are reresented as follows. A line is simly reresented by an imedance. This imedance is simulated by a resistor in series with a reactor in the Simulink. Their arameters are in Ohm and Henry, resectively. In order to convert the reactance X of the reactor into the corresonding inductance L, the ower frequency f=5 Hz should be used. Therefore, lines 1 and 2 are simulated by (R line1 =.72 Ω; L line1 = 8.6e3 H) and (R line2 =.36 Ω; L line2 = 4.3e3 H), resectively. The transformer in this ower system is a two winding transformer. The low voltage winding is connected in delta and the high voltage one is connected in grounded-wye. The YnD11 connection indicates that the voltage at the delta winding leads the resective one at the wye winding by 3 degrees. The arameters in transformer rating of each winding is R=.1.u. and L=.4.u. The transmission system is assumed to be infinitive. This means, the short-circuit ASEAN Engineering Journal Part A, Vol 2 No 2, ISSN X.21

9 imedance of the system is Z sc,grid = Ω. In another word, voltage at Bus 1 is remained 1.u. during both normal oeration and fault condition. Load is reresented by a constant imedance to reflect the change of load ower following the change of voltage. The voltage used to convert the constant ower model into constant imedance is generally the nominal voltage. However, the voltage obtained from a ower flow rogram under refault condition can model the load with higher accuracy than using the nominal voltage Prefault Condition Voltages at Buses 2, 3, and 4 are obtained from a ower flow rogram for the refault condition. Load under this condition is modeled as a constant ower of 1+j.5 MVA. Results in hase-hase rms value are as follows. Bus 2: V 2re = kv Bus 3: V 3re = kv Bus 4: V 4re = V Voltage at the load bus 3 is kvrms. The resective load imedance is j Ω. Thus, it is reresented in Simulink by a circuit comrising a resistor R load = Ω in series with an inductor L load =.38 H Double Line-to-Ground Fault (DLGF) In the case of a DLGF (hases B and C) through Z f =.2 Ω, a big di at hases B and C of the IBDG terminal voltage (Bus 4) occurs. The dro of voltage causes the reference current to increase until it reaches the limit I thres = 1, A (eak value) and asses the limit at time t = 2.6 s. The IBDG is switched to the current source mode causing the IBDG current becomes constant immediately after that with the value of I inv,sat = 1, A (eak value) as shown in Figure 7. The hase of the IBDG current lags the hase of the ositive-sequence comonent of the IBDG terminal voltage by 9. This lagging hase satisfies the FRT requirement in the case of fully reactive current suort. The voltage characteristics at Buses 4 and 2 are not in the same waveform as illustrated in Figure 8 because of the transformer connection of YnD11. Both voltages at Phases B and C at Bus 2, that is on the high voltage side of the transformer, decrease due to the fault. At Bus 4, which is on the low voltage side of the transformer, the voltage di at Phase B is bigger than that at hases A and C whose voltages are almost the same as 225 V. Thus, the hase shift caused by the transformer connection should be taken into consideration at the stage of forming the bus admittance matrix. The fault currents at the faulted bus in this case are shown in Figure 9 where the eak values of the current at Phases B and C are 1, and 1, A, resectively. Because the IBDG is controlled in current mode, the ower outut is no longer maintained the redefined value of.5 MW as shown in Figure 1. In addition, the 9 hase lagging of the IBDG current causes the active ower outut to become zero and the reactive one to increase to.34 MVAr. Table 1 summarizes results of voltages and currents obtained from the Simulink simulation of the DLGF case so as to easily comare with those from the roosed fault calculation algorithm which will be used later. ASEAN Engineering Journal Part A, Vol 2 No 2, ISSN X.22

10 IBDG current (A) Voltage at Bus 2 (V) Voltage at Bus 4 (V) ,748 A 1, A -15-1,784 A Fault instant Current source Time (s) Phase A Phase B Phase C Figure 7. Currents from IBDG during a DLGF Z f =.2 Ω V Fault instant Time (s) Phase A Phase B Phase C Figure 8. Voltages at Buses 2 and 4 during a DLGF Z f =.2 Ω Fault current (A) , A 1, A Fault instant Time (s) Phase A Phase B Phase C Figure 9. Fault current during a DLGF Z f =.2 Ω ASEAN Engineering Journal Part A, Vol 2 No 2, ISSN X.23

11 Power (MVA) Reactive ower Active ower.34 MVAr Fault instant Time (s) Figure 1. IBDG ower outut based on ositive-sequence comonents during a DLGF with Z f =.2 Ω Table 1. Peak voltages and currents obtained from Simulink Items Bus 2 Bus 3 Bus 4 Pos.-seq. voltages 2, , Phase A 4, , Phase B 1, IBDG current Fault current Pos.-seq. currents 1, Phase A 1, Phase B 1, , Results from the Proosed Algorithm It is assumed that all sequence imedances are identical for each system comonent. The comutation is erformed in er unit with: basemva = 1 MVA; base voltage on the high voltage side: basekv = 6 kv; base voltage on the low voltage side: basev = 38 V. In order to determine the equivalent imedance Z eq for utilizing the roosed algorithm, the system in Figure 6 is reresented in the fashions of negative and zero-sequence networks as in Figure 11. For easily comaring with the results from the simulation in Table 1, the load is also modeled as a constant imedance with resect to the refault voltage obtained from a ower flow rogram. The equivalent negative and zero-sequence imedances of the system viewed from Bus 3 are (.376 +j.979).u. and ( j.739).u., resectively. According to the sequence network connection in Figure 5, these two imedances and three times of the fault imedance (3Z f ) can be relaced by an equivalent imedance Z eq = j.423.u for the DLGF case. The equivalent imedance is connected to the faulted bus (Bus 3) in the ositive-sequence network as illustrated in Figure 12 for alying the roosed fault calculation algorithm. In this unbalanced fault case, the connection of YnD11 is taken into account by a comlex ta setting value a = e -j/6 for the ositive-sequence comonent and a = e j/6 for the negative-sequence comonent. The ta setting indicates that the ositive-sequence comonent of delta voltage leads the ositive-sequence comonent of Y voltage by 3 degrees; whereas, the negative-sequence comonent of delta voltage lags the one of Y voltage by 3 degrees. These ta setting values are inut in the data to formulate the bus admittance matrix Y bus of the modified sequence network connection in Figure 12. ASEAN Engineering Journal Part A, Vol 2 No 2, ISSN X.24

12 During the DLGF, the IBDG is switched to the current source mode with I inv,sat = A rms (or 1, A eak value) at the second iteration. The algorithm restarts and udates C f to the bus admittance matrix Y bus. The solution is reached after new 7 iterations. After the algorithm converges, the hase of I inv,sat automatically lags the ositive-sequence voltage at Bus 4 by 9 degrees. The ower outut during this fault case is no longer maintained at.5 MW. Currents at the faulted bus (Bus 3) are comuted from the ositive-sequence voltage at Bus 3 in a similar way to the conventional fault calculation. Peak values of fault current I F in Amere are obtained by multilying the corresonding er unit value by the base value of A. The summary of results from fault calculation for the DLGF is in Table 2. Obviously, the values of elements in Table 2 including fault currents, bus voltages, and currents contributed from IBDG are in close roximity comared with the results in Table 1 that comes from the simulation. For instance, the fault current at hase B at the faulted bus in Table 1 is 1,38162 A eak. This value is a little lower than 1, in Table 2. 4 C f Z trans 2 Z 2 line2 3 Z load Z 2 line C Z trans f Z line2 3 Z load Z line1 1 (a) Negative-sequence network (b) Zero-sequence network Figure 11. Sequence networks of the simle system with the installation of an IBDG P ref +jq ref I inv,ref I thres? I inv,sat C f Ye s N L 4 Z trans Z eq 1:e jπ/6 3 2 Z 1 line2 Load bus Z load Z 1 line1 1 Slack bus Figure 12. Modified sequence network connection for the test system Table 2. Results from the rogram using the roosed algorithm Voltages in eak value (V) Items Bus 2 Bus 3 Bus 4 Pos. voltage 2, , Phase A 4, , Phase B 1, Currents in eak value (A) Items IBDG current Fault current Zero. comonent Pos. comonent 1, Neg. comonent rad Phase A 1, Phase B 1, , ASEAN Engineering Journal Part A, Vol 2 No 2, ISSN X.25

13 VI. Conclusion This aer has roosed an adative algorithm for fault calculation in system with IBDG. The algorithm is then validated successfully by the comarison with the time-variant simulation of a simle system. Results obtained from the roosed algorithm and those from the simulation are close in roximity. The algorithm is convenient for calculating fault currents with all fault tyes. The estimated fault currents can be used to set arameters of rotective devices and to check their rotection caability. VII. References [1] P.M. Anderson, Power System Analysis, IEEE PRESS Power Systems Engineering Series, John Wiley & Sons Inc, New York, [2] H. Saadat, Power System Analysis, Second Edition, McGraw-Hill Comanies Inc, New York, 24. [3] P.M. Anderson, Analysis of faulted ower systems, IEEE PRESS Power Systems Engineering Series, John Wiley & Sons Inc, New York, [4] J. Morren and S.W.H de Haan, Short-circuit current of wind turbines with doubly fed induction generator, IEEE Transactions on Energy Conversion, Vol. 22, No. 1, , 27. [5] M.E. Baran and I.L. El-Markaby, Fault analysis on distribution feeders with distributed generators, IEEE Transactions on Power Systems, Vol. 2, No. 4, , 25. [6] R.A.N. Nimitiwan, G.T. Heydt, and Suryanarayanan, Fault current contribution from synchronous machine and inverter based distributed generators, IEEE Transactions on Power Delivery, Vol. 22, No. 1, , 27. [7] D. Turcotte and F. Katiraei, Fault contribution of grid-connected inverters, IEEE Electrical Power Conference,. 1-5, 29. [8] R.J Nelson, Short-circuit contributions of full-converter wind turbines, IEEE PES Transmission and Distribution Conference and Exosition (T&D),. 1-5, 212. [9] M. Brucoli, T.C. Green, and J.D.F. MacDonald, Modelling and analysis of fault behaviour of inverter microgrids to aid future fault detection, IEEE International Conference on System of Systems Engineering,. 1-6, 27. [1] IEEE Committee, IEEE Standard for Interconnecting Distributed Resources with Electric Power Systems, IEEE Standard , 28. [11] Distribution System Oerators - ESB Networks, Irish distribution code, 27. [12] Bundesverband der Energie-und Wasserwirtschaft ev, Guideline for generating lants connection to and arallel oeration with the medium-voltage network, 28. [13] S.H. Ko, S.R. Lee, H. Dehbonei, and C.V. Nayar, Alication of voltage- and current-controlled voltage source inverters for distributed generation systems, IEEE Transactions on Energy Conversion, Vol. 21, No. 3, , 26. [14] R. Strzelecki, G. Benyzek, Power electronics in smart electrical energy networks, Sringer-Verlag London Limited, London, 28. [15] M. Brucoli, Fault behavior and fault detection in islanded inverter-only microgrids, Doctoral Dissertation, Imerial College, London, 28. [16] A. Keyhani, M.N. Marwali, M. Dai, Integration of green and renewable energy in electric ower systems, John Wiley & Sons Inc, New Jersey, 21. [17] Dao Van Tu and S. Chaitusaney, Imacts of Inverter-based Distributed Generation Control Modes on Short-circuit Currents in Distribution Systems, The 7 th IEEE Conf. industrial electronics and alications, , 212. ASEAN Engineering Journal Part A, Vol 2 No 2, ISSN X.26