Low-Voltage, Voltage-Controlled Charge Pump Regulator Applying a Highly Efficient Minimization Ripple Technique

Transcription

1 54 SOERA et al.: OW-VOTAGE, VOTAGE-CONTROE CHARGE PUMP REGUATOR ow-voltage, Voltage-Controlled Charge Pum Regulator Alying a Highly Efficient Minimization Rile Technique J.. B. Soldera, A.. Vilas Boas and A. Olmos J.. B. Soldera, A.. Vilas Boas and A. Olmos, Motorola Freescale Brazil Semiconductor Technology Center (BSTC) Rod. SP-34, Km 8,7-A, Jaguariúna, S.P , Brazil, rjs, rab3, rao7@freescale.mot.com Abstract This aer resents a low-voltage, low-rile voltage-controlled charge um regulator intended to feed internal blocks in a chi to guarantee regular oeration when the ower suly voltage dros below some redefined value. The circuit was imlemented using an array of voltage doubler with system regulation imroved by a voltage-controlled oscillator in the feedback ath and alying a highly efficient voltage rile minimization technique. The circuit size is.556 mm when fabricated in a standard.5µm CMOS rocess and can suly loads consuming u to 8mA from.6v to.3v of ower suly. ndex Terms Voltage doubler, charge um, low-rile, voltage regulator.. NTROUCTON Nowadays, System On a Chi (SoC) can integrate several functions onto a single die to reduce cost and imrove the final roduct miniaturization. The demand now is for multi-rocessing units, microcontrollers, grahics, logic, memories (SRAM, Flash, and RAM), mixed signal, and so on. Process scaling down and alications requirements are driving SoC devices to oerate with low ower and low voltage, sometimes down to.6v. f one or more internal blocks can not work roerly at such low voltage, a higher than the external suly voltage must be generated internally to guarantee the correct oeration of the articular module as well as the chi as a whole. A voltage higher than the ower suly level can be generated multilying that suly voltage. This effect can be achieved connecting couler caacitors serially through diodes or switches as shown in Fig. Basically, for one multilying stage, the suly voltage is alied to the to caacitor late during the clock hase charging it at. Next, in the comlementary clock hase b, the suly voltage is alied to the bottom caacitor late roviding a total charged voltage of, disregarding charge loss in the circuit. The suly voltage can be multilied several times adding more stage cascading caacitors. An on-chi um generator based on an imroved voltage multilier technique using the Cockcroft-Walton cell has been develoed in []. The cell is comosed by serial caacitors charged by diodes. Fig. and 3 illustrate the classical multilier technique and the on-chi imlementation, resectively. An alternative voltage doubler toology emloying three charge ums has been roosed in []. The main charge um was imlemented with crosscouled NMOS transistors whereas two additional charge ums are required to bias a NMOS transmission gate and to level shift a control signal. Fig. 4 shows the basic charge um cell. The circuit is based on the switch caacitor technique and has been widely emloyed in most advanced charge ums. An imroved circuit with a seemed toology uses two charge ums for the doubler [3]. However, its alication has disadvantages since one charge um block is needed to boost the bulk voltage of the outut transistor. Additionally, in the second charge um, the bulk of the outut transistor is connected to a floating caacitor resulting in charge losses. Furthermore, careful latch u revention techniques are required. A solution with no charge losses in the junction, alying the bulk-switching concet and adding only two extra transistors without entailing a second charge um was roosed in [4]. n this work we resent an imroved aroach using only NMOS transistors without bulk biasing as well as free of charge losses requiring only one extra transistor to bias the gate outut transistor. n addition, a voltage-controlled oscillator in the feedback ath hels to imrove the system regulation. Moreover, a highly efficient minimization rile technique was alied. This aer is organized as follows. First, the regulation system design is described in Section. Next, in Section 3, the voltage doubler circuit trade-off is resented. The exerimental results are shown in Section 4. Finally, Section 5 summarizes the conclusions of this work. b b b b Fig.. Simle voltage doubler Fig.. Cockcroft-Walton multilier Fig. 3. ickson charge um

2 JOURNA NTEGRATE CRCUTS AN SYSTEMS, VO, NO. 4, ECEMBER b Fig. 4. Basic cross-couled voltage doubler VCO enable V bg Charge um R R C S : elay unit : Voltage doubler Fig. 5. Charge um regulator block diagram C Flash memory model. CRCUT ARCHTECTURE The roosed charge um circuit is a voltage regulator intended to rovide an internal suly voltage. n this articular case a voltage regulator for an on-chi flash memory is resented. n Fig. 5 C S is the charge uming storage caacitance whereas the flash memory is reresented by a sink current in arallel with a load caacitance C. The circuit starts to work whenever the external suly voltage falls below.5v. At such condition, the outut voltage something in between.v and.3v remains steady over a wide range of suly voltages, tyically from.6v to.5v. The charge um regulator allows for write/read/erase oerations on the flash memory even when the ower suly reaches.6v driving u to 8mA current over a temerature range from -4 o C to 35 o C. The charge um regulator contains three searate blocks: a charge um, a voltage controlled oscillator (VCO) and a low voltage detector circuit. The module oeration is based on a voltage doubler working as a charge um whose outut voltage is linearly either increased or decreased as a function of the oscillator frequency. Four voltage doublers comose the charge um being each one sequentially enabled to reduce the total outut voltage rile. The numbers of voltage doublers is carefully adjusted allowing to efficiently minimizing the rile. A delay ath is included to lag the clock signal for each doubler. When the outut voltage is below.5v the comarator turns on the oscillator; otherwise the comarator disables the oscillator. The.5V tri-oint value is obtained scaling down the outut voltage by a resistive voltage divider and comaring it to a bandga reference (V bg ). Hysteresis added to the comarator circuit revents for undesirable oeration when the suly carries noise. The circuit is designed to rovide a regulated outut voltage slightly higher than the tri-oint voltage, about.3v when ower suly is.6v. The most imortant regulator design considerations are: a) the feedback and um should ram u sufficiently fast as a system requirement, and b) the um and oscillator discharge currents cannot cause a rate of changing at the outut (u or down) faster than the feedback comarator delay.. CRCUT ESGN A. The Charge Pum Voltage oubler Emloying the same rincile resented in Fig. to 4, the voltage doubler imlemented with imroved serial C M b C C ' M M 4 M 3 out ~ C 3 '' Fig. 6. Voltage doubler schematic switch is shown in Fig. 6. n order to achieve a desirable and stable voltage regulation, both the charge um and the oscillator are designed to comensate each other for suly voltage deendence hence the regulator outut voltage is nearly constant across the suly range neglecting rocess and temerature sensitivities. Regarding Fig. 6 C, the voltage doubler caacitor, and C are charged to via the cross-couled transistors M and M. When the inut clock signal b goes high the bottom late of caacitor C and the to late of the C are charged at. Next, when ' goes high, the suly voltage is alied to each second caacitor lates and the charge stored in C is transferred to the load by M 3. The clock signal, obtained from through an inverter based level shifter, is alied on C 3 to obtain a V GS3 higher than V th3 (where is the um voltage and V th3 is the M 3 threshold voltage). Note C 3 is charged by M 4, an extra transistor emloyed to bias M 3 and the caacitor charge is (~3 ). The caacitors C and C 3 can be relatively small as they only drive the gate of M, M 4 and M 3, resectively. However, C must be carefully adjusted to boost the load with the desirable current. Assuming the single-hase doubler without load (M 3 oened) in Fig. 6 is running freely, i. e. with the control system in oen loo, the um voltage is given by: V V V dd V where V S is the drain-source voltage of M by the end of the charge rocess of C, and = (C /C C )V is the voltage on C due to the caacitive voltage division between C and the stray caacitance C when V is alied. V is a delayed signal obtained from V with same clock hase. Then, the um voltage becomes: C V Vdd ÿv S C C () S ()

3 56 SOERA et al.: OW-VOTAGE, VOTAGE-CONTROE CHARGE PUMP REGUATOR Considering V = and V S, and denoting: C η = ÿ < η < C C the um voltage due to a single-hase doubler reduces to: V (3) η (4) Now, after closing M 3, the charge um outut voltage needs to be established regarding the charge transference and the rile voltage. efining as the minimum outut voltage, H as the maximum outut voltage, and f as the VCO oscillation frequency, the outut rile voltage is given by: VoutH Vout = (5) f C C ( ) uring the transference eriod, the charge stored in C and C is droved out sulying the caacitors C S and C. So, the total charge transferred to the outut node is: C C ) V ( C C ) V = ( C C C C ) V (6) ( P S out S f the average value in between and H is, relacing (4) and (5) in (6) roduces: V η V out dd f C C S ( C C S The term [/(C S C )] in (7) accounts for the charge reviously stored in both C S and C, and being sunk by the current load. Note stray caacitances, charge injection, and switching losses might degrade the doubler erformance if not taken into account. Fig. 7 sketches the voltage doubler waveforms in each eriod of oeration with regard to M 3 being oened or closed as a function of the clock hases. Some desirable features obtained in this doubler circuit are the low rile voltage, small storage caacitor and um sizes, minimum clock feedthrough, and fast settling time. The rile voltage minimization is described below. Both the doubler and the uming storage caacitor sizes must be adjusted as a function of the oscillator frequency and system requirements. While the regulator system is working in close-loo the minimum doubler caacitance must satisfy: C C (8) f ( V ηv ) b ' outm dd ÿ ) outh (7) where M is the maximum outut regulated voltage, e.g..3v in the resent case. t is imortant to oint out the doubler can be imlemented with NMOS transistors merely since all gate-tosource voltages are higher than the common-mode voltage (~ /) and V GS3 higher than η V th3. Also, the layout embodies solid guard rings tied to the ground line and to the umed outut minimizing current injection into the adjacent substrate. B. The Minimization Rile Technique To attenuate the outut voltage rile a toology with four doublers working sequentially was adoted as mentioned before. The rile voltage (V r ) in oen loo can be determined from: out Vr (9) mf ( CS C ) where m is the number of doublers. Based in (8-9) the doubler caacitor and the number of doublers were adjusted by simulation to obtain a suitable rile and meet the overall desired target erformance. Fig. 8 illustrates the startu sequence for an architecture with four voltage doublers. The clock signal is delayed evenly in each doubler. C. The Voltage Controlled Oscillator A oular method for realizing digital-outut VCOs in CMOS technology is the constant current charge and discharge tye or C oscillator where current sources are used to charge and discharge the timing caacitors and the outut frequency is inversely roortional to the caacitor value [5]. Fig. 9 illustrates the voltage controlled oscillator. Assuming the SR latch is in its reset state node V C is tied to the suly voltage. n this state constant current ref discharges linearly caacitor C until the voltage V C reaches the bandga voltage V bg. Then the outut of the comarator controlled by V C goes high and set the SR latch. After that the discharge of caacitor C through current reference ref starts while V C is quickly tied to. When V C attains the V bg level the circuit is driven to its initial state. This comletes one eriod of oscillation and the rocess begins again. Note the latch oututs are fed back and their states determine which caacitor is either charged or discharged via the inverter current sources. This method rovides a 5% duty cycle square wave. Assuming C = C = C and ref = ref = ref, the voltage controlled oscillator frequency can be aroximately given by: '' V r t Fig. 7. Voltage doubler waveforms 3 Fig. 8. Charge um startu sequence

4 JOURNA NTEGRATE CRCUTS AN SYSTEMS, VO, NO. 4, ECEMBER Bandga Current Source Voltage Controlled Oscillator V bg R R R 3 bias - M bias M ref V C V C - - bias bias V C sr-latch S Q R Q Q Q R 4 ref C C V C m:n ref f = () C ( V V ) dd Note there is an inversely linear relationshi between the suly voltage and the um-charging rate, the oscillator frequency gets higher as the suly level becomes lower. To attain temerature and ower suly immunity, a temerature comensated voltage and current reference circuits were designed. The bandga cell sulies a reference voltage that is indeendent of temerature by canceling the negative temerature coefficient of a biolar base-emitter voltage (V eb ) with the ositive temerature coefficient of a PTAT circuit (roortional-to-absolute). The bandga core in Fig. 9 rovides a reference voltage given by: R kt = ÿ ln mr V ÿ bg Veb () R q nr 3 where V eb is the base-emitter voltage of transistor Q, (m/n) is the biolar emitter ratio, and (R /R 3 ) is the bandga resistor ratio. All the bandga resistors are imlemented with P diffusion and were adjusted by simulation to meet the required erformance. The current source rovides a constant current indeendent of temerature to discharge the VCO caacitors and bias the comarators. Providing transistors M and M work on weak inversion the current reference bias can be defined by: bias = VR 4 / R4 () where V R4 is the voltage dro through resistor R 4 and is given by: bg ( W / ) ( W / ) kt V R 4 = ÿ ln (3) q Fig. 9. Voltage controlled oscillator architecture Resistor R 4 is made u of P and N-well resistors with comlementary temerature deendence carefully adjusted to comensate the PTAT voltage dro in (3). Considering () simultaneously with the charge um outut deendencies on both the oscillator frequency and the ower suly voltage as described by (7), the um regulator has a reasonably constant outut voltage disregarding fabrication rocess and second order effects. However, secial care must be taking with comarator offset voltage and caacitor matching. The oscillator switching is very clean and quick wasting very low ower consumtion with shoot through current sources. An extra design criterion adoted was determining how small the caacitors could be without introducing errors due to stray caacitances in arallel with C and C. The voltage controlled oscillator frequency has nearly linear voltage suly deendence and generates nominally a 6MHz square waveform when oerating at.6v and MHz working at.v. V. EXPERMENTA RESUTS The charge um regulator circuit was imlemented in a standard.5µm CMOS rocess technology. The regulator occuies an area of.mm whereas the caacitor size is.344mm. Fig. exhibits the charge um regulator erformance across the ower suly range for arts at room temerature. When the suly falls below.3v the charge um holds its outut voltage at about.3v. The charge um regulator outut dros off if the ower suly becomes lower than.6v. Fig. illustrates the voltage rile at the regulator outut. The nominal rile voltage at the charge um outut is 7m when driving a load current of 8mA. Moreover, the circuit achieves above 94% ower efficiency for a ower suly voltage of.8v and 8mA current load. Regulated outut voltage (V) Suly voltage (V) Fig.. Regulator outut vs. suly voltage

5 58 SOERA et al.: OW-VOTAGE, VOTAGE-CONTROE CHARGE PUMP REGUATOR.5 Outut Voltage [V] oad Current [ma].3 Fig.. Outut voltage rile for =.8V and =8mA 8 Fig. 4. Outut voltage vs. load current (=.8V) Regulated outut voltage (V) VCO frequency (MHz) ºC 5ºC 85ºC 35ºC Temerature (C).7.8 Suly voltage (V)..3 Fig.. Regulated outut voltage across temerature range Fig. 5. Oscillator frequency vs. suly voltage Charge Pum Storage Caacitor Ch: Enable signal Ch: Regultator outut Fig. 3. Outut voltage for several load currents. Vdd=.8V Fig. demonstrates the regulator outut voltage has a reasonably small variation across a wide temerature range. The regulator transient resonse after enabling the charge um is illustrated in Figure 3. With an enable signal falling time of about 5ns, the regulator outut voltage stabilizes in less than 6ns. Fig. 4 shows the outut regulated voltage for different values of load current. Fig. 5 shows the VCO frequency as a function of the suly voltage level. Note the oscillator frequency is inversely roortional to the ower suly: lower suly voltages cause higher frequencies allowing obtaining Fig. 6. Microhotograh of charge um regulator and storage caacitor a relatively constant voltage at the regulator outut. The microhotograh of the charge um regulator (four doublers, the VCO and the low voltage detector) including the storage caacitor is shown in Figure 6. V. CONCUSON A voltage-controlled charge um regulator using NMOS switches with only one extra transistor to bias the outut transistor has been develoed. Silicon results indicate the circuit has a good load regulation and quite con-

6 JOURNA NTEGRATE CRCUTS AN SYSTEMS, VO, NO. 4, ECEMBER stant outut voltage over a wide range of suly voltage and temerature. n addition, a highly efficient minimization rile technique was resented achieving 7m of rile voltage. The circuit was fabricated in a.5µm CMOS technology, and occuies an area of.556mm with a drive caability u to 8mA. The regulator is intended to suly an internal flash memory with constant voltage allowing read/ write/erase oerations down to.6v. V. ACKNOWEGMENTS The authors wish to thank. McQuirck (Motorola 8/6 Bit MCU ivision, Austin, USA) for technical discussions and hel during the develoment of the regulator. We also thank A. Gomes,. Nascimento, M. Esindola and H. Albergaria (Motorola - BSTC, Jaguariúna, Brazil) for aer review, measurement and careful layout. V. REFERENCES [] J. F. ickson, "On-chi high-voltage generation in NMOS integrated circuits using an imroved voltage multilier technique", EEE J. Solid-State Circuits, vol. SC-, no 3, June 976, [] Nakagome, Y.; Tanaka, H.; Takeuchi, K.; Kume, E.; Watanabe, Y.;Kaga, T.; Kawamoto, Y.; Murai, F.; zawa, R.; Hisamoto,.; Kisu, T.;Nishida, T.; Takeda, E.; toh, K., "An exerimental.5 V 64Mb RAM", EEE J. Solid-State Circuits, vol. 6, no. 4, Ar. 99, [3] T. B. Cho and P. R. Gray, "A -bit, MS/s, 35 mw ieline A/ converter", EEE Custom ntegrated Circuits Conf., 994, [4] P. Favrat, P. eval, and M. J. eclercq, "A high-efficiency CMOS voltage doubler", EEE Custom ntegrated Circuits Conf., 997,. 59-6, 997 [5] M. Wakayama, A. Abidi, "A 3-MHz low-jitter high-linearity CMOS voltage-controlled oscillator, EEE J. of Solid-State Circuits, vol. 4, no., Aril 989,