A 10-bit, 100 MS/s A/D Converter using Folding, Interpolation, and Analog Encoding

Transcription

1 A 0-bit, 00 MS/s A/D Converter using Folding, Interolation, and Analog Encoding FINAL REPOR EPORT William T. Colleran Integrated Circuits & Systems Laboratory Electrical Engineering Deartment University of California Los Angeles, CA December 993 Funded by TRW Electronics Systems Grou, TRW LSI Products Grou, and the State of California MICRO Program.

2 Table of Contents Chater Introduction Alications for High-Seed Low-Power A/D Converters Ultrasound Imaging Systems High Definition Television Radar Digital Samling Oscilloscoes Design Goals SHPi Process General Considerations Terminology and Notation Quantization Fundamental Limits to Performance References 77 Chater Pielined Architecture Architectural Comarison Flash Converters Feedback or Multi-ass Converters Feedforward Converters Pielined Feedforward Converters vii

3 viii..5 Folding Converters Algorithmic (Cyclic) Converters Architecture Selection Bit High Seed Converter Toology Timing Scheme for Pielined Converter Pielined Feedforward Partitioning Hardware Comlexity (Parts and Power) Performance (Yield and SNR) References 07 Chater 3 Samle-and-Hold Design Samling Bridge Toology and Oeration Error Sources in Diode Samling Bridges Aerture Jitter Small Signal Bandwidth Preamlifier Track Mode Distortion Diode Bridge Track Mode Distortion Finite Aerture Time Hold Pedestal Feedthrough Noise Droo Thermal Distortion Track-and-Hold Design

4 ix 3.3. Preamlifier and Samling Bridge Postamlifier Design Clock Buffer Design Summary Interstage Track and Hold Design References Chater 4 Coarse Quantizer Bit Flash Quantizer Differential Reference Ladder Interolation Layout and DAC Interface References 4 Chater 5 Digital to Analog Converter and Residue Amlifier Segmented Aroach Effects of Mismatches Layout Considerations Residue Amlifier References 39 Chater 6 Folding Fine Quantizer

5 x 6. Concet of Folding Linear Folding Circuits Sinusoidal Folding Sinusoidal Folding Circuits Non-uniform Interolation Folding and Interolating A/D Converter Encoding Cycle Pointer (Coarse Quantizer) Layout References 59 Chater 7 Gain Stabilization Gain Matching Requirements Gain Control References 67 Chater 8 Performance Circuit Layout Test Methodology Test Results References 84

6 xi Chater 9 8 Bit A/D Converter Architecture Performance Chater 0 Conclusions and Suggested Further Research Conclusions Further Research Oortunities References 307 Bibliograhy

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8 List of Figures Figure.. Examles of increasing DSP comlexity in communications systems. (a) A classical system with analog demodulator followed by baseband A/D conversion and DSP. (b) Advanced system with IF A/D conversion using digital demodulation and signal rocessing. (c) Emerging system with RF A/D conversion followed by digital downconversion, demodulation, and baseband signal rocessing Figure.. Basic Reflection imaging system Figure.3. Phased array imaging system Figure.4. Figure.5. Current medical ultrasound imaging system utilizing one A/D converter after the received signals have been delayed and summed Emerging medical ultrasound imaging system with an array of ADCs with digital delays and summation Figure.6. A tyical digital television system Figure.7. Proosed MUSE encoder system.note the comlexity of the digital circuitry following the A/D conversion consistent with the trend deicted in figure Figure.8. Tyical hased array radar system Figure.9. Tyical samling oscilloscoe Figure.0. A/D converter erformance comarison Figure.. Fill codes for SHPi mask layers. Layer names refer to those listed in table Figure.. Cross-section and lan view of minimum-size SHPi device xiii

9 xiv Figure.3. Cross-section and lan view of SHPi device Figure.4. SHPi transistor model used for SPICE simulations Figure.5. Track-and-hold terminology Figure.6. Quantizer transfer functions or quantization characteristics. (a) Uniform quantizer. (b) Non-uniform quantizer Figure.7. Uniolar (a) and biolar (b) quantization characteristics Figure.8. Ideal quantizer transfer functions. (a) Midtread characteristic. (b) Midriser characteristic Figure.9. Quantizer notation, threshold and quantization levels Figure.0. Quantization transfer functions including error sources (a) Offset error. (b) Gain error. (c) Linearity error. (d) Missing codes Figure.. Quantizer models. (a) Nonlinear model. (b) Statistical model Figure.. Quantization noise models. (a) Ideal quantizer. (b) Quantizer with threshold level errors Figure.3. Distribution of quantization error Figure.4. The functions,, and. By lotting the normalized versions,, and versus the shaes of the above functions become indeendent of. Also, equals Figure.5. NPR of ideal midriser quantizer with Gaussian noise inut. Quantizer resolution indicated on curves Figure.6. Otimum loading factor and NPR for Gaussian noise inut Figure.7. The functions,, and. By lotting the normalized versions,, and versus the shaes of the above functions become indeendent of Figure.8. SNR of ideal midriser quantizer with sinusoidal inut. Quantizer resolu-

10 xv tion indicated on curves Figure.9. SNR of ideal midriser quantizer lotted versus sinusoidal inut amlitude. Aroximation is based uon equation Figure.30. Difference between actual SNR and aroximated SNR from figure Figure.3. The inverse cosine function Figure.3. The function for several values of n Figure.33. Harmonic levels for an ideal 8-bit midriser quantizer Figure.34. Harmonic levels for an ideal 0-bit midriser quantizer Figure.35. Peak harmonic number versus analog inut amlitude Figure.36. Peak harmonic ower for ideal midriser quantizer Figure.37. The function evaluated at for eak harmonics. (lower). (uer) Figure.38. Harmonic levels for an 8-bit midriser quantizer with /4 LSB rms threshold errors Figure.39. Thermal limit to achievable resolution Figure.40. Aerture uncertainty causes amlitude errors Figure.4. Maximum aerture jitter consistent with / LSB errors for various values of resolution Figure.4. Maximum attainable resolution limited by aerture jitter Figure.43. Quantization error waveforms. (a) Ideal quantizer. (b) Quantizer with threshold level errors Figure.44. Segment of quantization error waveform with non-zero threshold errors,

11 xvi Figure.45. Achievable resolution as limited by metastability errors Figure.. Flash or arallel A/D converter toology Figure.. Feedback or multi-ass A/D converter toology Figure.3. Successive aroximation A/D converter toology Figure.4. Feedforward A/D converter toology Figure.5. Pielined A/D converter toology Figure.6. Folding A/D converter toology Figure.7. Algorithmic A/D converter toology Figure.8. Bit serial A/D converter toology Figure.9. SNR degradation in folding A/D converters due to mismatches. Quantizer resolution indicated on lot Figure.0. Yield in folding A/D converters for 8 (lower) or 6 (uer) folds er stage. is 64 mv (left) or 8 mv (right). The normalization of the indeendent variable to INL refers to maximum secified INL above which oint a converter fails the erformance test, e.g. if maximum secified INL is / LSB, and is / mv; then the aroriate value on the indeendent axis for determining yield is Figure.. Tyical stage ielined A/D converter Figure.. Alternative imlementation of -stage ielined A/D converter Figure.3. Conventional timing scheme for ielined A/D converter Figure.4. Outut signals from converter elements in ielined A/D emloying conventional timing scheme Figure.5. Modified timing scheme for ielined A/D converter

12 xvii Figure.6. Outut signals from converter elements in ielined A/D emloying modified timing scheme Figure.7. Comarison of A/D converter comlexity versus fine quantizer resolution Figure ieline artitioning Figure ieline artitioning Figure.0. 0 bit A/D converter yield (uer) and mean SNR (lower) versus segmented DAC current source mismatch for both 4-7 and 5-6 artitioning Figure.. 0 bit A/D converter yield (uer) and mean SNR (lower) versus coarse quantizer INL for both 4-7 and 5-6 artitioning Figure.. 0 bit A/D converter yield (uer) and mean SNR (lower) versus fine quantizer INL for both 4-7 and 5-6 artitioning Figure.3. 0 bit A/D converter SNR (uer) and gain error (lower) versus DAC gain error for both 4-7 and 5-6 artitioning Figure.4. 0 bit A/D converter SNR (uer) and gain error (lower) versus fine quantizer gain error for both 4-7 and 5-6 artitioning Figure.5. Histogram of A/D converter SNR for 4-7 (uer) and 5-6 (lower) artitionings Figure.6. Block diagram of selected A/D converter architecture Figure 3.. Track-and-hold building-blocks (a) and oeration (b) Figure 3.. Figure 3.3. Prototye diode bridge track-and-hold circuit with emitter follower reamlifier and ostamlifier Diode-bridge track-and-hold with differential air controlling bridge current

13 xviii Figure 3.4. Diode-bridge switch Figure 3.5. Diode-bridge models in track mode. (a) Large-signal model. (b) Smallsignal model Figure 3.6. Diode bridge oeration in track mode. (a) t. (b). (c) Figure 3.7. T/H toologies. (a) Single-ended. (b) Differential Figure 3.8. Aerture jitter gives rise to amlitude error Figure 3.9. SNR as limited by clock jitter and quantization noise. Quantizer resolution labelled on curves Figure 3.0. Small-signal models of diode-bridge in track mode. (a) Full model. (b) Simlified model when arallel networks are combined Figure 3.. Emitter follower reamlifier with caacitive load used to simulate dynamic distortion Figure 3.. Simulated THD of the emitter follower reamlifier with caacitive load versus load caacitance,, bias current,, amlitude,, and inut frequency,. In each case, the arameter is varied in a,, 5, 0 attern which aroximates exonential sacing (i.e. each value is about twice the revious one) while maintaining integer values Figure 3.3. Large-signal model of diode bridge in track mode with finite bias imedances, Figure 3.4. Diode bridge with current erturbations caused by dynamic current into Figure 3.5. Linear, time-varying model of diode bridge and hold caacitor used for finite aerture analysis Figure 3.6. Resonse of bridge current (a) and small-signal bridge resistance (b) over finite aerture time

14 xix Figure 3.7. Frequency resonse induced by finite aerture time assuming a linear small-signal bridge model. Uer curves reresent frequency resonse with constant bridge resistance,. Lower curves include the effect of bridge turn-off governed by Figure 3.8. Large-signal model for simulating finite aerture effects Figure 3.9. Simulated THD due to finite aerture time as a function of inut amlitude,, inut frequency,, aerture time,, and bridge slew rate,. Parameters are swet in a,, 5, 0 fashion to aroximate an exonential swee with integer values Figure 3.0. Charge injection at bridge turn-off gives rise to hold edestal distortion. (a) Tyical bridge circuit showing auxiliary diodes which control bridge bias voltages in hold mode. (b) Diode small-signal caacitance-voltage characteristic Figure 3.. Comarison between distortion due to hold edestal redicted by analysis and simulation (uer); and between distortion redicted by simle aroximations and simulation (lower) Figure 3.. A bootstraed bridge center-ta reduces hold edestal distortion. (a) Unity-gain buffer drives bridge center-ta from outut node. (b) Diode C- V characteristic still determines residual charge injection Figure 3.3. Diode-bridge track-and-hold with differential air controlling bridge current. Diodes D5 and D6 conduct during hold-mode while diodes D through D4 are cut-off Figure 3.4. Small-signal models of bridge in hold mode. (a) Model including all comonents. (b) Equivalent model simlified through symmetry Figure 3.5. Small-signal frequency resonse of diode bridge in hold mode Figure 3.6. Cross-couled caacitors between comlementary bridges reduce feedthrough and hold edestal error Figure 3.7. Feedthrough versus cross-couling caacitance normalized to otimum

15 xx value Figure 3.8. Cross-couling scheme for reduced feedthrough with series connected diodes as couling elements Figure 3.9. Feedthrough versus area of cross-couled diode structure normalized to the otimum area Figure Cross-couling can artially cancel hold edestal error by cancelling charge exelled by bridge diodes during bridge turn-off. Note that charge injection from a bridge diode connected to the to node of one bridge is cancelled by the cross-couled element connected to the bottom node of the comlementary bridge. Likewise, injection from a diode connected to the bottom of one bridge is cancelled by the cross-couled element connected to the to of the comlementary bridge Figure 3.3. Noise sources affecting track-and-hold oeration. reresents the total jitter noise ower on the drive signals to the diode bridge including the jitter on the incoming clock and that added by the clock buffer circuitry. reresents the mean-square noise voltage at the hold caacitors. This is an aroximation assuming that the dominant comonent is thermal noise and exists during both track mode and hold mode. causes base shot noise which is integrated on the hold caacitor during hold mode giving rise to voltage noise Figure 3.3. Single-ole RC low ass filter for analysis of kt/c noise Figure kt/c noise at the hold caacitors. In the differential imlementation the two indeendent sources contribute to the total noise ower erturbing the held voltage, resulting in doubled noise ower comared to a singleended version. Signal amlitude is also doubled, thus quadruling signal ower and increasing SNR by 3 db over the single-ended case Figure Base shot noise integrates on the hold caacitors during the hold interval adding a noise comonent to the held voltage Figure Postamlifier inut bias current causes droo on hold caacitor

16 xxi Figure A differential T/H imlementation largely cancels droo effects Figure Thermal contour of minimum-size SHPi device ( µm X8 µm emitter area) dissiating mw on a 50 µm thick substrate Figure Thermal contour of large device (75 µm X75 µm emitter area) dissiating 00 mw Figure Emitter follower buffer Figure A single-ended T/H circuit based on a diode-bridge with emitter follower reamlifier, differential air current switch with resistive loads, and emitter follower ostamlifier Figure 3.4. A differential track-and-hold imlementation with linearity comensation Figure 3.4. Differential reamlifier and bridge with comensation Figure Layout of differential reamlifier and diode bridge with feedforward comensation Figure Postamlifier imlementations. (a) An oerational amlifier connected as a voltage follower. (b) A differential air configured as a voltage follower. (c) A differential air-based follower with enhanced erformance. (d) An oen-loo unity-gain ostamlifier with linearity comensation Figure Differential ostamlifier imlementation Figure Layout of differential ostamlifier with feedback bootstraing Figure Clock buffer schematic diagram Figure Layout of first track-and-hold clock buffer circuit Figure Comlete track-and-hold circuit (with ostamlifier shaded). The clock buffer has not been drawn for simlicity

17 xxii Figure Layout of first track-and-hold circuit Figure 3.5. Simulated T/H outut sectrum. Fs00 Mss, Fin43.75 MHz Figure 3.5. Second stage track-and-hold block diagram with feedback to bridge center-ta nodes to reduce gain-loss due to hold edestal error Figure Second track-and-hold with bootstraed center-ta Figure Layout of second T/H Figure Interstage ostamlifier schematic which rovides high inut imedance and voltage gain of. Outut emitter followers are not shown for simlicity Figure Second T/H ostamlifier Figure Second T/H with relica Figure 4.. Flash or arallel A/D converter toology Figure 4.. Differential reference ladder with comarators Figure 4.3. Figure 4.4. Figure 4.5. Figure 4.6. Figure 4.7. Differential reference ladder showing comarator inut bias currents Three dimensional deiction of differential reference ladder with comarator connections Interolation between reamlifiers reduces loading on differential reference ladder and reduces ower by halving the number of comarator re-amlifiers Differential reference ladder drawn to emhasize circular symmetry, and including reference to interolated thresholds in grey Coarse quantizer reamlifier array driven by differential reference ladder

18 xxiii Figure 4.8. Coarse quantizer comarator with internal DAC current switch Figure 4.9. Coarse quantizer latch array with current segment inuts and differential DAC outut Figure 5.. Fully-segmented current-outut reconstruction DAC Figure 5.. Figure 5.3. Figure 5.4. Figure bit yield for a fully-segmented DAC with 4 bit resolution versus current segment mismatch assuming maximum INL is / LSB bit A/D converter yield (uer) and mean SNR (lower) versus segmented DAC current source mismatch for both 4-7 and 5-6 artitioning Segmented DAC current source array with scrambled wiring matrix at to Segmented DAC current source array with common centroid layout Figure 5.6. Segmented DAC current source array with trimmable layout Figure 5.7. Residue amlifier imlementations. (a) Tyical aroach using transconductance cell and subtracting currents at outut. (b) Imroved aroach subtracting currents at transconductor emitter Figure 5.8. Residue amlifier and its relicas Figure 6.. Architecture of feedforward quantizer Figure 6.. Figure 6.3. Folding A/D converter architecture. Analog folding with F folds reduces fine quantizer resolution to Reduction in dynamic range seen be comarator array for (a) sawtooth and (b) triangle folding characteristics Figure 6.4. Translinear-based current-mode folding circuit Figure 6.5. Current-mode folding circuit using cascodes

19 xxiv Figure 6.6. Figure 6.7. Figure 6.8. A folding function which is not iece-wise linear. The transfer function shown is sinusoidal for convenience but could be any non-saturating, eriodic function An array of hase-shifted, non-linear folding blocks with comarators detecting zero-crossings can circumvent the need for an inverse-sine quantizer Linear suerosition imlements non-uniform interolation to generate multile sinusoids equally-saced in hase from two quadrature sinusoids Figure 6.9. Translinear sinusoidal folding circuit with voltage drive Figure 6.0. Translinear sinusoidal folding circuit with current drive Figure 6.. Folding circuit based uon hyerbolic tangent transfer function of voltage driven differential airs Figure 6.. Folding circuit based on wired-or interconnection Figure 6.3. Fully-differential sinusoidal folding circuit with differential reference ladder, overflow comensation, and common-mode de-bias circuitry Figure 6.4. Differential non-uniform interolation ladder generates sinusoids equally saced in hase from quadrature inuts. Distortion is minimized due to symmetry of circuit enabling use of simle, low-ower emitter follower buffers Figure 6.5. (a) Differential non-uniform interolation ladder. (b) Phasor reresentation of quadrature and interolated signals. (c) Corresonding voltage waveforms Figure 6.6. Threshold error at interolated thresholds Figure 6.7. Folding, interolating, and analog encoding fine quantizer using quadrature folded waveforms

20 xxv Figure 6.8. Imroved encoding scheme significantly reduces hardware comlexity. All circuits are differential but are shown single-ended for simlicity Figure 6.9. Cycle ointer incororating analog encoding. Actual circuit is differential but is shown single-ended for simlicity Figure 6.0. Layout of fine quantizer analog circuitry including differential reference ladder, folding amlifiers, interolation ladder, and analog multiliers from the encoding block Figure 7.. Figure 7.. Figure 7.3. Figure 7.4. Figure 8.. Figure 8.. Figure 8.3. Figure 8.4. Figure 8.5. Effects of comonent gain errors on A/D transfer function. (a) Effect of fine quantizer gain error. (b) Effect of DAC gain error bit A/D converter SNR (uer) and gain error (lower) versus DAC gain error for both 4-7 and 5-6 artitioning bit A/D converter SNR (uer) and gain error (lower) versus fine quantizer gain error for both 4-7 and 5-6 artitioning Gain-matching relica circuits and feedback loos which adjust comonent gains bit A/D converter with constituent comonents highlighted. Die size is aroximately 4 mm X 4 mm (60 mil X 60 mil). Analog inut is at to, left of chi. Digital oututs are at bottom Die hotograh of 0-bit A/D converter with nominal DAC layout. Unused area surrounding DAC degeneration resistors is reserved for use in other ADC versions Die hotograh of 0-bit A/D converter with common centroid reconstruction DAC layout Die hotograh of 0-bit A/D converter with trimmable reconstruction DAC layout A/D converter test setu. All synthesizers are hase-locked to one master synthesizer. Pulse generator sulies ECL clock signal to DUT uon

21 xxvi trigger from low hase-noise synthesized source. Four ulse generators are used to suly clocks to DUT, but only one is shown for simlicity. Off-chi reconstruction DAC is helful for real-time debugging of system. Digitized data is catured in fast, dee memory and analyzed on workstation off-line Figure 8.6. Figure 8.7. Figure 8.8. Figure 8.9. A/D converter test setu. Synthesizers, ulse generators, sectrum analyzer, and filter bank are housed in rack on left. High-seed memory and workstation are on right. Power sulies, oscilloscoes, and test fixtures are on bench in rear Digital outut sectrum from A/D converter when samling a 5.87 MHz sinusoidal inut at 75 Mss Digital outut sectrum from A/D converter when samling a 5.87 MHz sinusoidal inut at 75 Mss Digital outut sectrum from A/D converter when samling a 5.87 MHz sinusoidal inut at 75 Mss Figure 8.0. Digital outut sectrum from A/D converter when samling a 49.6 MHz sinusoidal inut at 75 Mss Figure 8.. Differential linearity as measured by a histogram test with fin 6MHz and fs 75Mss Figure 8.. Integral linearity as measured by a histogram test with fin 5.87MHz and fs 75Mss Figure 8.3. Differential linearity as measured by a histogram test with fin 49.6 MHz and fs 75 Mss Figure 8.4. Integral linearity as measured by a histogram test with fin 5.87 MHz and fs 75 Mss Figure 8.5. Beat frequency test. fs 75 Mss, fin MHz. ADC outut is decimated by then alied to reconstruction DAC and dislayed on oscilloscoe

22 xxvii Figure 9.. Figure bit A/D converter architecture. T/H derives from inut T/H in 0-bit ADC. Quantizer is based uon 7-bit fine quantizer, also from 0-bit converter bit A/D converter with overlays to indicate location of constituent comonents Figure 9.3. Die hotograh of 8-bit A/D converter Figure 9.4. Figure 9.5. Figure 9.6. Figure 9.7. Figure 9.8. Figure 9.9. Measured SNR and harmonic distortion versus inut frequency at 5 Mss Measured SNR and harmonic distortion versus inut frequency at 50 Mss Measured SNR and harmonic distortion versus inut frequency at 00 Mss Measured SNR and harmonic distortion versus inut frequency at 5 Mss Measured SNR and harmonic distortion versus inut frequency at 50 Mss Measured SNR and harmonic distortion versus inut frequency at 75 Mss Figure 9.0. Measured SNR and harmonic distortion versus inut frequency at 00 Mss Figure 9.. Measured SNR and harmonic distortion versus inut frequency at 00 Mss with T -40 C Figure 9.. Measured SNR and harmonic distortion versus inut frequency at 5 Mss Figure 9.3. Measured SNR versus inut frequency at several samle rates

23 xxviii Figure 9.4. Measured integral linearity error versus ower suly variation at several temeratures with fs 00 Mss. Uer curves lot eak INL. Lower curves lot RMS INL

24 List of Tables Table.. Comarison of erformance requirements for HDTV and medical ultrasound imaging alications along with design goals for this work Table.. Requirements for medical ultrasound imaging alications Table.3. Requirements for HDTV alications Table.4. Performance goals for this develoment Table.5. SHPi NPN characteristics Table.6. SHPi mask layers Table.7. SHPi NPN transistor SPICE model arameters Table.8. Otimum quantizer loading and NPR for Gaussian noise inut Table.. Comarison among several A/D converter architectures Table 3.. Bias voltages across bridge elements in track mode and hold mode xxix

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26 ACKNOWLEDGEMENTS I am grateful to the many eole who suorted and encouraged me during the work leading to this thesis: rofessors, colleagues, friends, and family. My advisor at UCLA, Dr. Asad A. Abidi, heled select a challenging and worthwhile research toic and guided me throughout this endeavor. I am grateful to him and the other members of my committee, Henry Samueli, Gabor C. Temes, Siegfried G. Knorr, Milos D. Ercegovac, and William E. Slater. My colleagues at UCLA have been a constant source of suort, contributing in innumerable ways to the work described here. I feel rivileged to have worked with these stimulating researchers, esecially John Angell, James Chang, Ramon Gomez, Eric Holmberg, Patrick Pai, Gary Sullivan, and Tyson Tuttle. In addition to their other contributions, Pat Pai and James Chang assisted greatly in the rearation of this manuscrit. TuongLong Huy Phan roved invaluable, tirelessly laying out the integrated circuits, and Maryam Rofougaran skillfully drew many of the figures aearing in this manuscrit. Several eole outside of UCLA were also suortive of my efforts. Binoy Rosario, Brian Boso, Wink Gross, Ken Weigel and Jim Marsh made fabrication of the circuits ossible at Tektronix Integrated Circuit Oeration. Fred Weiss rovided access to TriQuint Semiconductor s Gallium Arsenide MESFET rocess for a recursor to this roject which led to our beneficial relationshi with Tektronix. K.C. Wang, Peter Asbeck, Randy Nubling, and Derrick Cheung funded a arallel develoment of a Gallium Arsenide HBT A/D converter at the Rockwell International Science Center and shared results of their work with me. Tino Gomez of TRW s Analog and Digital Products deartment assembled all of the fixtures required during the evaluation of the integrated circuits. His exert abilities eased the difficulty of testing greatly. Throughout my graduate studies at UCLA I received financial suort from TRW, Inc. and through the University of California MICRO rogram. My management at TRW, esecially Bill Ashley, Fred Carer, Ken degraaf, and Keith Kelley, has been consistently suortive during this arduous rocess. Most imortantly, my family, Mom and Dad, Bud, Beth, and Brian gave me constant moral suort and encouragement - more than they realize. Without their faith and insiration this work very likely would not have been comleted. I cannot adequately exress the love and gratitude I feel for them. xxxi

27 VITA 96 Born, Bangor, Maine 983 B. S., Electrical Engineering (Magna Cum Laude) University of Notre Dame Notre Dame, Indiana Member of Technical Staff Electronic Systems Grou TRW, Inc. Redondo Beach, California 985 M. S., Electrical Engineering University of Southern California Los Angeles, California MICRO Fellow Deartment of Electrical Engineering University of California Los Angeles, California TRW Fellow Deartment of Electrical Engineering University of California Los Angeles, California Deartment Staff Electronic Systems Grou TRW, Inc. Redondo Beach, California xxxii

28 PUBLICATIONS W. T. Colleran and A. A. Abidi, A 0-Bit 75MHz Two-Stage Pielined Biolar A/D Converter, to aear in IEEE Journal of Solid-State Circuits, vol. 8, no., Dec W. T. Colleran, T. H. Phan, and A. A. Abidi, A 0b 00Ms/s Pielined A/D Converter, 993 IEEE International Solid-State Circuits Conference Digest of Technical Paers, vol. 36, San Francisco, CA.,.68-69, Feb W. T. Colleran and A. A. Abidi, A 6dB Wideband Matched GaAs MESFET Amlifier, IEEE Transactions on Microwave Theory and Techniques, vol. 36, no. 0, , Oct W. T. Colleran and A. A. Abidi, A 6dB Wideband Matched GaAs MESFET Amlifier, IEEE International Solid-State Circuits Conference Digest of Technical Paers, vol. 3, San Francisco, CA, , Feb W. T. Colleran and A. A. Abidi, Wideband Monolithic GaAs Amlifier using Cascodes, Electronics Letters, vol. 3, no. 8, , Aug. 7, 987. xxxiii

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30 ABSTRACT OF THE DISSERTATION A 0-bit 00 Megasamle-er-Second Analog-to-Digital Converter Utilizing Folding, Interolation, and Analog Encoding Techniques by William Thomas Colleran Doctor of Philosohy in Electrical Engineering University of California, Los Angeles, 993 Professor Asad A. Abidi, Chair Monolithic imlementations of data converters at the 0 bit, 00 megasamle-er-second (Ms/s) level are considered a high riority for many alications today including ultrasound imaging, high definition television, radar signal rocessing, and instrumentation. Several drawbacks including excessive ower consumtion and die size revent current high-seed conversion methods from being extended to the 0-bit level. The urose of this research roject was to develo more efficient architectures for high seed, medium resolution converters, and to evolve the circuit designs necessary for these architectures. Analog-to-digital (A/D) converters that are known to work at the highest seed tyically involve a flash architecture, receded by a diode-bridge samle-and-hold (S/H) circuit. However, single-chi imlementations of flash converters with resolution greater than 8 bits are difficult to attain because these toologies involve large device count and large ower dissiation. Further, xxxv

31 xxxvi multi chi realizations yield degraded erformance and increased ower dissiation comared to monolithic aroaches due to the overhead incurred when driving signals between chis. Innovative architectures which include subranging, ielining, analog encoding, folding, and interolation have been investigated for a monolithic A/D converter which includes an on-chi S/H function to enhance overall converter erformance. These techniques resulted in a toology which is highly integrable yet which aroaches the erformance of a fully arallel or flash A/D converter. The integrated circuit dissiated 800 mw while digitizing 50 MHz inut signals at 75 Ms/s with 56 db signal-to-noise-lus-distortion ratio.

32 Chater Introduction Analog-to-digital (A/D) conversion and digital-to-analog (D/A) conversion lie at the heart of most modern signal rocessing systems where digital circuitry erforms the bulk of the comlex signal maniulation. As digital signal rocessing (DSP) integrated circuits become increasingly sohisticated and attain higher oerating seeds more rocessing functions are erformed in the digital domain. Driven by the enhanced caability of DSP circuits, A/D converters (ADCs) must oerate at ever-increasing frequencies while maintaining accuracy reviously obtainable at only moderate seeds. This trend has several motivations and oses imortant consequences for analog circuit design. The motivations for rocessing most signals digitally are manifold: digital circuits are much less exensive to design, test, and manufacture than their analog counterarts; many signal rocessing oerations are more easily erformed digitally; digital imlementations offer flexibility through rogrammability; and digital circuitry exhibits suerior dynamic range, thereby better reserving signal fidelity. As a consequence of the aforementioned advantages accrued by DSP, fewer and fewer oerations benefit from analog solutions. Figure. illustrates the evolution towards systems relying uon more sohisticated DSP hardware with a concomitant reduction in analog circuit content. This move ortends two imortant ramifications for the role of analog circuitry in future systems. First, only Radio Frequency (RF) rocessing and data conversion (including anti-aliasing filters) will remain as imortant niches where analog imlementations exhibit advantages over digital aroaches. Data converters will continue to lay a significant role

33 Chater Introduction RF Signal Analog Demodulator Baseband Signal A/D Converter DSP (a) RF Signal RF Mixer IF Signal A/D Converter Digital Demodulator & Processing (b) RF Signal A/D Converter Digital Mixer, Demodulator, & Processing (c) Figure.. Examles of increasing DSP comlexity in communications systems. (a) A classical system with analog demodulator followed by baseband A/D conversion and DSP. (b) Advanced system with IF A/D conversion using digital demodulation and signal rocessing. (c) Emerging system with RF A/D conversion followed by digital downconversion, demodulation, and baseband signal rocessing. in advanced electronic systems oerating in the RF and Intermediate Frequency (IF) regimes. Further, since A/D conversion generally requires more ower and circuit comlexity than D/A conversion to achieve a given seed and resolution, ADCs frequently limit erformance in signal rocessing systems. This fact underscores the second consequence of enhanced DSP erformance on the role of analog circuit design. That is, since A/D conversion limits overall system erformance, develoment of imroved A/D conversion algorithms and circuitry reresents an extremely imortant area of research for the foreseeable future. This dissertation describes the results of research into the develoment of new techniques for achieving high-seed, low-ower A/D conversion where high-seed refers to converters caable of oeration in excess of 50 megasamles er second (Ms/s) and low-ower imlies dissiation below one Watt. Imortant arameters of ADCs in addition to seed and ower dissiation such as resolution, linearity, dynamic distortion, and yield are addressed. Since, generally one of these

34 . Alications for High-Seed Low-Power A/D Converters 3 asects of ADC erformance can be imroved at the exense of others, design techniques utilized when aroaching high-seed A/D conversion have historically required large ower dissiation. Conversely, many alications which require low ower dissiation such as ortable digital voltmeters (DVMs) led to designs which are fundamentally limited in seed. The urose of this research was to develo new A/D conversion techniques which are inherently fast yet which consume low ower. Table.. comares the erformance goals for this roject along with the Parameter Units HDTV Requirement Ultrasound Requirement Design Goal Resolution bits Samle Rate Mss Inut Bandwidth MHz Power mw INL a bits DNL bits / / SNR db SFDR db S/(N+D) db Table.. Comarison of erformance requirements for HDTV and medical ultrasound imaging alications along with design goals for this work. a. INL and DNL are defined in section.3.. requirements for two imortant alications of high-seed A/D converters which served as motivations for this work: High-Definition Television (HDTV) and medical ultrasound imaging systems. These and other alications for high-seed, low-ower ADCs are next described in detail.. Alications for High-Seed Low-Power A/D Converters As mentioned reviously, the ever-increasing seed and sohistication of monolithic DSP hardware is enabling unrecedented imrovements in system erformance. Frequently, however;

35 4 Chater Introduction such enhancements are limited by the attainable A/D converter caabilities. In such instances, increased ADC erformance is articularly advantageous (and valuable) since system viability is directly imacted. Several alications where high-seed, low-ower A/D converters lay a ivotal role in determining overall system erformance are detailed below. The converter requirements for these alications heled determine ractical design goals for this research roject... Ultrasound Imaging Systems Medical ultrasound imaging is by far the most imortant commercial alication of highseed, low-ower ADCs of the tye described here. In this alication, A/D converters digitize electrical signals from an array of iezo-electric transducers which resond to acoustic echoes from a atient s body. The digitized data from the converter array can then be combined to form an image of the tissue within the body. The diagnostic utility of such real-time imaging is obvious, leading to an imressive commercial market. Currently over 0,000 medical ultrasound machines are sold worldwide annually. Systems now under develoment use arrays of 8 A/D converters generating a worldwide annual market of over million chis. Suitable ADCs must meet stringent erformance criteria such as listed in table. and at resent no such comonent exists. A basic reflection imaging system (Fig..) [], [] utilizes a iezo-electric transducer Transducer T R Signal Processor Dislay Patient Pulse Generator Figure.. Basic Reflection imaging system. which emits acoustic energy when excited electrically or conversely electrical energy when excited acoustically. With the switch in the transmit osition a ulse generator excites the transducer resulting in roagated wavefronts emanating from the transducer. Immediately following ulse

36 . Alications for High-Seed Low-Power A/D Converters 5 transmission the switch is changed to the receive osition using the same transducer. When the wavefront encounters a discontinuity, as shown, a scattered wave is roduced indicated by the reflected vectors. This scattered wave is received by the transducer and the resultant electrical signal is rocessed and dislayed giving information about the size and location of the discontinuity. The rocessing usually comrises bandass filtering, gain control, and enveloe detection. Although concetually simle, such a system can only form one-dimensional images containing information describing the distance a discontinuity lies from the transducer. Two-dimensional images can be formed by hysically scanning the transducer across the region of interest, but a suerior aroach relies on an array of transducers which can be electrically controlled to scan a two-dimensional field. In array imaging systems which use electronic deflection and focusing, or hased array systems as they are often called, each transducer receives reflected signals from every oint in the field of view (Fig..3). The oututs of all transducers are aroriately delayed and summed to Controlled Controlled Delay Controlled Delay Controlled Delay Delay Transducer Array Control Unit Summer Signal Processor Dislay Figure.3. Phased array imaging system. reresent the energy reflected from a secific oint within the view field. In this manner signals from the desired oint undergo constructive interference, while those signals from other oints sum in an uncorrelated manner. By electronically controlling the delay elements in the array, the beam is steered through the region of interest forming a real-time two-dimensional image. Current medical ultrasound systems emloy analog delay-lines and summing electronics with A/D conversion occurring after the received signals have been summed (Fig..4). Such systems lace only modest restrictions on A/D erformance usually requiring 8-bit resolution at video samle rates while

37 6 Chater Introduction Delay Delay Delay Delay Σ ADC Signal Processor Transducer Array Control Unit Dislay Figure.4. Current medical ultrasound imaging system utilizing one A/D converter after the received signals have been delayed and summed. tolerating ower dissiation well above one Watt. However, the analog delay-lines and summing electronics are cumbersome, difficult to control, and degrade signal fidelity. Therefore, ultrasound systems currently under develoment incororate one ADC er transducer channel enabling use of digital delays and summation (Fig..5) [], [], [3]. Image resolution in hased array systems Digital ADC ADC Delay Digital ADC Delay Digital ADC Delay Digital Delay Transducer Array Σ Digital Summer Signal Processor Control Unit Dislay Figure.5. Emerging medical ultrasound imaging system with an array of ADCs with digital delays and summation. increases with the number of array elements and the frequency of emitted ulses. To enhance image quality, emerging ultrasound units use larger arrays (8 to 56 elements) and higher RF ulse frequencies (u to 5MHz) than their redecessors. This tye of system gives suerior image quality, but because of the large number of ADCs required, the ower dissiation and rice of each converter must be minimized. Additionally, samle rates and inut bandwidths must increase to accommodate the increased transducer frequencies and amlitude resolution must imrove to 0 bits. This combination of erformance secifications (summarized in table.) reresents a very

38 . Alications for High-Seed Low-Power A/D Converters 7 Parameter Ultrasound Requirement Units Resolution 0 bits Samle Rate 40 Mss Inut Bandwidth 5 MHz Power 500 mw INL bits DNL / bits SNR 56 db SFDR 58 db Power Sulies +/ 5 V Die Cost <0 $ Selling Price <40 $ Table.. Requirements for medical ultrasound imaging alications. stringent and as yet elusive goal, but the magnitude of the ultrasound market rovides comelling motivation to develo such A/D converter technology. Note that the modest die cost of $0 er screened comonent laces a restriction on the die size and yield of the converter given a certain wafer cost... High Definition Television Debate rages today over what form future television systems will assume. Unquestionably the next generation of video equiment will deliver unrecedented icture quality with satial resolution increasing to millions of ixels and amlitude resolution imroving to better than one art-er-thousand. Because of this dramatic imrovement, the inchoate system has been dubbed High Definition Television or HDTV. Almost certainly HDTV will rely uon a digital transmission standard taking advantage of the owerful image comression algorithms develoed to reduce the required amount of transmitted data. Such a system (Fig..6) requires A/D conversion of the incoming rasterized signal from a video camera at rates far in excess of current video signals. After modulation and transmission, the received signal is demodulated, digitized, and rocessed for dislay. The exact form of the receiver system deends on available technology and will follow the

39 8 Chater Introduction CAMERA A / D MODULATION RASTERIZED SIGNALS TRANSMISSION CHANNEL D/A DIGITAL PROCESSING A / D DEMODULATION DISPLAY Figure.6. A tyical digital television system. trend deicted in figure.. Therefore, the A/D converter in the receiver will migrate towards the antenna eventually oerating at RF samle rates. At resent, broadcast studio equiment laces more demanding constraints on ADCs than home television units. An oerational broadcast encoding system has been in use in Jaan for several years. This system, the Multile Sub-Nyquist Samling Encoding (MUSE) system, (Fig..7) [4] requires one A/D converter oerating above 40 HDTV in RGB LPF LPF LPF A/D A/D A/D γ M T X Time comression LPF LPF TCI Encoder S M Interfield Pre-filter Interfield Pre-filter Field Offset Subsamling (4.3 MHz) MHz LPF ~ MHz MHz 8 MHz 48.6 Ms/s Samling Conversion Samling Conversion S M M I X 6. Ms/s Frame Offset Subsamling ζ Emhasis Control Synchronize, and Add Audio (4 Channels), Indeendent Data Inut Audio Encoder Motion Area Detection,350 Kb/s Time Comression Motion Vector Detection.5 MBd LPF Audio/VIT Signal Adder 6. Ms/s Transmission Equalization LPF 3.4 Ms/s D/A 3.4 MHz LPF 3 MHz MUSE OUT FM Modulation TX Figure.7. Proosed MUSE encoder system.note the comlexity of the digital circuitry following the A/D conversion consistent with the trend deicted in figure.. Ms/s for each of the 3 signals comrising an HDTV image in RGB format. Digitization at even higher rates is required for an HDTV comosite signal. Increased dynamic range of the HDTV

40 . Alications for High-Seed Low-Power A/D Converters 9 video signal also mandates digitization with 0-bit resolution. Table.3 summarizes the A/D Parameter HDTV Requirement Units Resolution 0 bits Samle Rate 75 Mss Inut Bandwidth 30 MHz Power 000 mw INL bits DNL bits SNR 5 db SFDR 56 db Power Sulies +/ 5 V Die Cost <5 $ Selling Price <00 $ Table.3. Requirements for HDTV alications. converter requirements for HDTV. Note that the samle rate and inut bandwidth are higher than those required for ultrasound systems (Table.), but that higher ower consumtion and die cost are tolerable...3 Radar Radar and electronic warfare (EW) systems reresent another imortant alication of high-seed, low-ower A/D converters. Many modern systems emloy hased-array techniques such as those used in ultrasound machines (Fig..5) with the iezo-electric transducers relaced by RF antennas. At resent, digitization usually occurs after downconversion (Fig..8) so this alication incororates baseband A/D conversion [3]. The samle-rate and resolution of the ADC deend uon the desired satial resolution and discrimination of the radar image. Samle-rates above 50 Mss with greater than 8 bit resolution are often desirable. Jam resistant radars require higher resolution A/D converters to enable detection of small signals in the resence of highowered interference.

41 0 Chater Introduction "I" (In-Phase) Channel Detector ADC RF Weighting, Delay, and Combining Network Local Oscillator 90 degree Phase Shifter Digital Processor Detector ADC Antenna Array "Q" (Quadrature) Channel Figure.8. Tyical hased array radar system. EW systems often lace more stringent requirements on ADCs than radars by emloying IF and RF A/D conversion. In such systems an incoming radar signal is digitized (referably at RF frequencies) then stored in a high-seed memory called a digital RF memory (DRFM). This digital data can then be converted back to analog form and transmitted to the originator confusing its signal rocessing algorithms. Alternatively, the stored radar signature can be used later for threat analysis. Similar techniques are used in radar range finders and terrain maing systems. In each of these alications higher samle-rates and digitizable signal bandwidths imrove erformance; therefore, radar systems always serve as an alication for faster A/D converters...4 Digital Samling Oscilloscoes Much instrumentation in general and digital samling oscilloscoes (DSOs) in articular rely uon fast, accurate A/D converters to erform their functions. A DSO comrises an ADC (receded by signal conditioning circuitry), a buffer memory, and a dislay (Fig..9) [5], [6]. Some Analog Inut Signal Conditioning ADC Buffer Memory Low Rate Digital Play back Gain Adjust Clock & Control Write Read Figure.9. Tyical samling oscilloscoe.

42 . Design Goals DSOs require only 8-bit A/D conversion because the dislay is limited to that resolution; however as more emhasis is laced uon digital storage and analysis of catured waveforms, limitations of dislay resolution no longer determine ADC accuracy. Therefore, newer DSOs are migrating to 0 and bit A/D converters and are functioning as digital waveform recorders, not merely oscilloscoes. Some samling oscilloscoes utilize high-seed samling gates with very small aerture times to effect extremely high inut bandwidths, often in the tens of GHz. The samle-rates of these circuits, however, are usually quite slow, around a few megasamles/second. This technique, sometimes called equivalent-time samling, introduces aliasing whose effects can be tolerated if a narrowband, eriodic signal is being viewed. In many instances, however, aeriodic or broadband signals must be digitized mandating Nyquist rate samling which imlies a samlerate greater than twice the bandwidth of the incoming signal. To roerly digitize such waveforms, very high samle-rate A/D converters are desirable. Because some DSOs are ortable batteryowered units, low-ower ADCs are mandatory. The combination of the above converter requirements; 0 to bit resolution, high-seed, and low-ower form a formidable set of secifications.. Design Goals The design goals for this roject were established based uon the requirements of the alications described above and uon the caabilities of other A/D converters extant. A summary of reorted erformance (Fig..0) shows no 0-bit resolution converters caable of 50 Mss oeration while consuming less than Watt. To address this need, develoment of a 0-bit, 00 Mss A/D converter consuming 750 mw was undertaken with the goal of achieving in excess of 9.5 effective bits of resolution for analog inut signals at 50 MHz. To ensure that commercially viable techniques were utilized throughout, untrimmed oeration was required from standard +5 V and 5. V ower sulies using a conventional oxide-isolated silicon biolar rocess. These erformance goals are summarized in table.4 along with more exlicit secifications for measures of dynamic linearity such as signal-to-noise ratio (SNR) and surious-free dynamic range (SFDR). Notice that the SFDR requirement is quite stringent at 65 db. This is consistent though with the ideal SFDR for a 0-bit ADC which is aroximately 90 db. The biolar rocess used for this roject rovides lateral PNP transistors and trimmable thin-film Nichrome (NiCr) resistors; however, to kee the design as generally alicable as ossible, PNP transistors were not used nor was trimming of resistors allowed.

43 Chater Introduction 650mW [8] 400mW [6] 3.5W, AD 9005 Biolar CMOS BiCMOS This work Resolution (Bits) mW [9].5W [3] 50mW [7] 900mW [0] 750mW, Design Goal 80mW [] 300mW [].0W [8].7W [7] 75mW [7] 300mW [4] 800mW [] 7.5W, AD 908.0W [3] 6 mw [5].6W Siemens SDA Samling Frequency (Mss) Figure.0. A/D converter erformance comarison. Parameter Performance Goal Units Resolution 0 bits Samle Rate 00 Mss Inut Bandwidth 50 MHz Power 750 mw INL bits DNL / bits SNR 59 db SFDR 65 db S/(N+D) 58 db Table.4. Performance goals for this develoment.

44 . Design Goals 3.. SHPi Process The semiconductor rocess used for this roject is called SHPi rovided by Tektronix, Inc. of Beaverton, Oregon. SHPi is an oxide-isolated biolar rocess with NPN transistors which exhibit a maximum cutoff frequency, f t, of aroximately 8.5 GHz. The rocess rovides NPN, PNP, and JFET transistors as well as Schottky diodes, trimmable thin-film resistors, imlanted resistors, and two-level gold interconnect metal. Only NPN transistors, Schottky diodes, and untrimmed resistors were used during this develoment. Minimum size devices exhibit aroximately 4GHz f t at the low bias conditions used. A summary of SHPi NPN device arameters is included in table.5. Parameter Value Units Minimum Device Size Minimum Emitter Size 7 X 5 µm.6 X 8 µm I c for eak f t.0 mα f t 8.5 GHz β 00 r b 75 Ω r e 0 Ω r c 00 Ω V A 5 V t f s C je 33 ff C jc 34 ff C cs 8 ff Table.5. SHPi NPN characteristics.. The information contained in this section was drawn largely from the SHPi Full Custom Integrated Circuit Design Guide ublished by Tektronix Integrated Circuits Oeration. This document is available as art number from Biolar Products Grou, Integrated Circuits Oeration, Tektronix, Inc. P.O. Box 500 Beaverton, Oregon

45 4 Chater Introduction The SHPi rocess was develoed for high-erformance analog alications and delivers excellent comonent matching. For examle, adjacent minimum-size transistors exhibit V BE mismatches with 00µV standard deviation. Likewise, β mismatches show standard deviations of %. Thin-film resistor matching deends uon geometry and device searation, but with roer design can be reduced to less than 0.5% standard deviation. The comlexity of the SHPi rocess limits integration to only modest levels (8 0 thousand comonents for reasonable yield). This limit arises from the large number of mask stes required (4 as shown in table.6) when NiCr resistors Mask Number Layer Name Mnemonic Buried Layer bl Isolation is 3 Channel Sto ch 4 Substrate Contact sc 5 Dee Collector dc 6 + Contact 7 Active Base ab 8 Emitter e 9 Contact ct 0 Nichrome ni st Metal m st Via v 3 nd Metal m 4 Passivation a Table.6. SHPi mask layers. and two layer interconnect are used. An additional mask is necessary to manufacture JFETs on the same substrate, but this otion was not invoked. Both layers of interconnect metal are gold with 4µm itch and 60 mω/sq sheet resistance. This imlementation rovides for dense layouts with excellent current-carrying caability and minimal arasitic resistance. To facilitate descrition of integrated circuit layouts the SHPi mask layers will be consistently drawn as deicted in figure..

46 . Design Goals 5 bl sc ab ni m is dc e m a ch ct v Figure.. Fill codes for SHPi mask layers. Layer names refer to those listed in table.6. A lan view (using the layer fill-atterns shown in figure.) and a cross-section of a minimumsize SHPi NPN transistor is shown in figure.. Larger devices are created by adding multile emitter and collector stries (Fig..3). Accurate comuter simulation is critical to the successful develoment of higherformance integrated circuits. Accurate simulations in turn deend uon accurate modeling of device behavior. The transistor model used for simulations during this develoment was rovided by Tektronix and is a macrocell (Fig..4) based on the standard SPICE BJT model. The arameters used with this subcircuit are listed in table.7.

47 B E B 6 Chater Introduction N Size: 7 x 5 microns CN 5 µ m 7 µ m c b e b metal Oxide n+dc Oxide + ch n+ buried layer + ch - Substrate Thin Oxide n emitter + + n EPI n+ bl Figure.. Cross-section and lan view of minimum-size SHPi device..3 General Considerations.3. Terminology and Notation Much of the nomenclature commonly used to describe data converters and their related circuits is idiosyncratic to the field. Therefore, a brief discussion of the more imortant terminology will now be undertaken. A samle-and-hold (S/H) or track-and-hold (T/H) circuit is frequently required to cature raidly varying signals for subsequent rocessing by slower circuitry. Although a S/H refers to a device which sends an infinitesimal time acquiring signals and a T/H refers to a device which sends a finite time in this mode, common ractice will be followed and the two terms will be used interchangeably throughout this discussion as will the terms samle and track. The function of a track-and-hold circuit is to buffer its inut signal accurately during track mode roviding at its outut a signal which is linearly roortional to the inut, and to maintain a constant outut level

48 C B E B E B C.3 General Considerations 7 4 µ m N4 Size: 4 x 8 microns N4C 8 µ m Metal c b e b e b c Metal Oxide n+dc n+dc Oxide + ch n+ buried layer + ch - Substrate Thin Oxide n emitter + + n EPI n+ bl Figure.3. Cross-section and lan view of SHPi device. c dcb rcx b rbx q dsub e sub Figure.4. SHPi transistor model used for SPICE simulations. during hold mode equal to the T/H outut value at the instant it was strobed from track to hold by an external clock signal (Fig..5). Several arameters describe the seed and accuracy with which this oeration is erformed. The track mode is the state when the T/H outut follows the T/H inut. The hold mode refers to the eriod when the T/H outut is maintained at a constant value. The track-

49 8 Chater Introduction Parameter Value Units Parameter Value Units ise.9e 6 A tf s isc 7.9e 6 A tr ns bf 00 cje 33 ff br 4 cjc 5.7 ff vaf 5 V vje.65 V var 4.5 V vjc.65 V ikf 5.96 ma mje 0.4 ikr ma mjc 0.4 ne.5 nc.5 dcb rbx 35 Ω cjo 8 ff rb 37 Ω vj.65 V rbm. Ω mj 0.4 rcx 95 Ω dsub rc 9 Ω cjo 8 ff re 9 Ω vj.65 V irb 70 µa mj 0.4 Table.7. SHPi NPN transistor SPICE model arameters. to-hold transition is the instant when the circuit switches from the track mode to the hold mode and the hold-to-track transition refers to the switch from hold mode back to track mode. The time between successive track-to-hold transitions is the samle eriod whose recirocal is the samle rate. While in track or samle mode, the T/H functions as a simle buffer amlifier. Oeration in this mode is described by the same secifications which characterize any analog amlifier such as gain, offset, bandwidth, nonlinearity, distortion, slew rate, and settling time. These arameters are not eculiar to T/H circuits and need not be elaborated uon further. While in the hold mode two effects are of rimary imortance. The first is droo which

50 .3 General Considerations 9 Amlitude Acquisition time Track time Settling time A/D Conversion time Track/Hold Outut Track/Hold Inut Hold Samle Hold Time Figure.5. Track-and-hold terminology. describes the decay of the outut signal as energy is lost from the storage element (usually a caacitor) within the T/H circuit. Droo is frequently caused by leakage or bias currents discharging a caacitor and manifests itself as an aroximately constant increase or decrease of outut voltage with time. The second imortant asect of hold mode erformance is feedthrough which describes the unwanted resence at the T/H outut of a signal comonent roortional to the inut signal. The feedthrough signal is usually described as the ratio of the unwanted outut signal to the inut signal amlitude. The acquisition time is the duration during which the T/H must remain in the track mode to enable the circuit to accurately relicate the inut signal, thereby ensuring that the subsequent hold mode outut will lie within a secified error band of the inut level that existed at the track-to-hold transition (after gain and offset effects have been removed). The remainder of time during the track mode exclusive of acquisition time is called the track time during which the T/H outut is a relica of its inut. The settling time describes the interval between the track-to-hold transition and the time when the T/H outut has settled to within a certain error band of its final value. The remainder of the time during the hold mode reresents the maximum time available for A/D conversion if the T/H is used for that urose. Conversion time of an A/D converter is the interval between the convert command and the instant when the digital code is available at the ADC outut. Therefore, the minimum samle eriod of a ractical A/D converter system is the sum of acquisition time,

51 0 Chater Introduction settling time, and conversion time. The track-to-hold transition determines many asects of T/H erformance. The delay time is the time elased from the execution of the external hold command until the internal track-to-hold transition actually begins. In ractical circuits this switching occurs over a non-zero interval called the aerture time measured between initiation and comletion of the track-to-hold transition. Practical circuits do not exhibit recisely the same samle eriod for each samle. This random variation from samle to samle is caused by hase noise on the incoming clock signal and further exacerbated by electronic noise within the T/H itself. The standard deviation of the samle eriod is termed the aerture jitter and limits amlitude resolution in A/D conversion. Finally, at the trackto-hold transition, circuit effects frequently give rise to a erturbation at the T/H outut. This effect which manifests itself as a discontinuity in the T/H outut waveform called hold jum or hold edestal can deend on the inut signal giving rise to distortion. A quantizer is a device which mas a continuous range of inut levels onto a finite set of discrete digital code words. An analog-to-digital converter (A/D converter) comrises a quantizer along with other signal conditioning circuitry such as amlifiers, filters, T/H circuits etc. In site of this difference, the terms quantizer and A/D converter are often used synonymously. A quantizer can be uniquely described by its transfer function or quantization characteristic which indicates the device s discrete oututs as a function of the continuous inut signal. The quantization characteristic therefore contains two sets of information: the first includes the digital codes associated with each outut state, and the second includes the threshold levels which are the set of inut amlitudes at which the quantizer transitions from one outut code to the next (Fig..6). The digital coding can take on one of several forms including natural binary, sign lus magnitude, offset binary, ones comlement, twos comlement, binary coded decimal (BCD), and Gray code each of which has advantages in articular alications. An ADC s actual threshold levels are denoted by T k where the index k ranges from 0 to M giving a total of M + values. Corresondingly, ideal thresholds levels are denoted T * k. The ideal thresholds can be located arbitrarily along the abscissa; however, evenly saced thresholds are most common. (Such devices are called uniform quantizers.) In general, otimum erformance results when the threshold locations match the robability density function of the incoming signal. However, in the absence of a riori knowledge of the inut signal statistics, uniform quantization outerforms other arrangements. Therefore, uniform quantizers are most commonly used and will be dealt with exclusively here. Quantizers whose ideal thresholds are

52 .3 General Considerations Quantization Levels Outut 0 Outut Quantization Levels Inut Outut Codewords Threshold Levels Inut Outut Codewords Threshold Levels (a) (b) Figure.6. Quantizer transfer functions or quantization characteristics. (a) Uniform quantizer. (b) Non-uniform quantizer. located symmetrically about the origin are called biolar quantizers while those whose thresholds are restricted to ositive (or negative) values are termed uniolar (Fig..7). Note that these 7 Outut 7/ Outut 6 5/ 5 4 FS FSR / / +FS 3 -/ 3 Inut -3/ -FS -5/ Inut -7/ FSR (a) (b) Figure.7. Uniolar (a) and biolar (b) quantization characteristics. characteristics differ only in the location of their resective origins. The Full-Scale Range, FSR, of a uniform quantizer reresents that ortion of the transfer function domain sanned by M equal-

53 Chater Introduction length intervals between adjacent ideal thresholds. The length of these intervals is called the quantization ste or simly Q. The relationshi between the Full-Scale Range and the quantization ste can be stated succinctly: Q FSR M (.) A term related to Full-Scale Range is Full-Scale, FS, which is the magnitude of the Full-Scale Ranges s maximum excursion from the transfer function origin. Because biolar and uniolar quantization characteristics differ in their definition of the origin, the meaning of Full-Scale varies when alied to differing tyes of characteristics. In a uniolar quantizer the Full-Scale Range sans from 0 to FSR, so FS FSR while in a biolar quantizer the Full-Scale Range is centered at the origin sanning from FSR to FSR, so FS FSR. Figure.7 illustrates these differences. Quantization levels, ( Q * k, k 0,, M ), are assigned values midway between adjacent ideal thresholds, i.e. Q * k ( T * k + T * k+ ). These oututs must be so assigned because the corresonding digital code words have no secific analog value. Therefore, the gain of the A/D converter is imlicitly defined. Figure.8 illustrates the two most common quantization Outut 7/ Outut 3 5/ 3/ -5/ -3/ -/ / / 3/ 5/ Inut -/ 3 Inut - -3/ - -5/ -3-7/ (a) (b) Figure.8. Ideal quantizer transfer functions. (a) Midtread characteristic. (b) Midriser characteristic.

54 .3 General Considerations 3 characteristics, the midtread characteristic and the midriser characteristic. For an N-bit biolar (uniolar) quantizer, a midtread characteristic has M + N thresholds and has one quantization level with value zero ( FSR ). A midriser characteristic has M + N + thresholds, one of which has value zero ( FSR ). By convention, T 0 and T M for each characteristic so only M hysical thresholds actually exist. Midriser quantizers have M N quantization levels which ma neatly onto the N binary outut codes exressible with an N-bit digital word. For this reason midriser quantizers are utilized more frequently than their midtread counterarts. The ideal thresholds and quantization levels for a uniform quantizer whether biolar or uniolar, midtread or midriser can be defined by the following relationshis: T k * for k 0 kq Off T for k M for k M (.) Q * k kq Off Q for 0 k M. (.3) QMOff,, T, and Off Q are related as follows: Midriser: M N Midtread: M N Q FSR M (.4) Uniolar: Biolar: Off T 0 Off Q 0 Off M T Q ( M ) Off Q Q Figure.9 deicts an ideal (biolar, midriser) quantization characteristic showing the relationshi

55 4 Chater Introduction between these values. T 0 T T M T M + T M T M T M Q M Q M Q Q 0 Figure.9. Quantizer notation, threshold and quantization levels. Real quantizer transfer functions fall short of the ideal because imerfections in fabrication cause actual thresholds to deviate from their desired lacement. Such non-idealities can be exressed in several ways (Fig.0). An error which causes all thresholds to shift from their ideal ositions by an equal amount is called an offset and is usually denoted. Non-ideality which results in an erroneous quantizer ste size, Q, is called gain error or scale-factor error. Q can be defined as a function of FSR (equation.) or alternatively Q can be assigned the value which minimizes threshold errors as calculated by linear regression. In the latter case equation. still holds, but FSR is a function of Q instead of vice-versa. Linearity error refers to the deviation of the actual threshold levels from their ideal values after offset and gain errors have been removed. Excessive linearity error results in missing codes, a condition wherein a valid outut code, say Q j, never occurs because its defining interval [ T j, T j + ] has become vanishingly small, T j + T j. Linearity error is quantified by the threshold level errors, ε k T k T * k (.5)

56 .3 General Considerations 5 7/ Outut 7/ Outut Ideal 5/ Ideal 5/ Actual 3/ Actual 3/ / / -/ 3 Inut -/ 3 Inut Offset Error -3/ -5/ -3/ -5/ -7/ -7/ (a) (b) 7/ Outut 7/ Outut Ideal 5/ Ideal 5/ Actual 3/ Actual 3/ / / Missing Code -/ 3 Inut -/ 3 Inut -3/ Threshold Errors -3/ -5/ -5/ -7/ -7/ (c) (d) Figure.0. Quantization transfer functions including error sources (a) Offset error. (b) Gain error. (c) Linearity error. (d) Missing codes. where k is defined for thresholds 0 through M but has meaning only for the real thresholds through M. This array of error terms, also called Integral Nonlinearity or simly INL, is frequently described by its eak value or its root-mean-square (rms) value: σ e M M ε k k (.6)

57 6 Chater Introduction Related to INL is the Differential Nonlinearity or DNL: d k T k T k Q. (.7) Since DNL is defined by a first-order difference equation, it is valid only for the range k M and only has hysical meaning over k M. The M element array of DNL values is also frequently described by its statistical roerties such as eak and rms. The terms integral and differential arise when describing the above two error measures because DNL can be defined as the first-order difference of the INL sequence. d k T k T k Q T k T k ( T * k T * k ) ( T k T * k ) ( T k T * k ) ε k ε k (.8) Several terms are commonly used to describe the relative ower of the analog inut to an A/D converter. The loading factor, LF, exresses the rms amlitude of the inut waveform relative to the quantizer FSR: LF rmsamlitudeoftotalinut FSR. (.9) The recirocal of loading factor is referred to as crest factor, CF, which is in turn related to the signal factor, SF. Signal factor differs from crest factor by including the rms value of only the signal inut while crest factor includes the rms of the signal lus noise inut. SF FSR rmsamlitudeofsignalinut. (.0).3. Quantization The quantization rocess can be described by a nonlinear inut outut transfer function as deicted in figure. and described in section.3.. The quantized outut signal, Q( x), is the

58 .3 General Considerations 7 Inut x Nonlinearity Outut Q( x) Inut x (a) Outut Q( x) x+ U( x) Quantization Noise U( x) (b) Figure.. Quantizer models. (a) Nonlinear model. (b) Statistical model. sum of the original inut signal, x, and a quantization error, U( x) where U( x) Q( x) x. (.) Here U( x) is the error resulting when the inut signal, x, is quantized with finite resolution. This quantization error, as shown in figure., is a deterministic function of the inut signal, x. However, subject to certain simlifying constraints [7], [8]; U( x) can be aroximated as a random noise comonent. The constraints necessary to justify this statistical model are: U( x) is a stationary rocess U( x) is uncorrelated with x The elements of U( x) are uncorrelated with each other The robability density function of U( x) is uniform over ( Q, Q ). The descrition of quantization in this section follows that given in by Martin and Secor in High seed analog to digital converters in communication systems: Terminology, architecture, theory, and erformance, D. R. Martin and D. J. Secor, tech. re., TRW Electronic Systems Grou, Redondo Beach, CA, Nov. 98.

59 8 Chater Introduction -FSR/ -FSR/ Q Q U( x) Q (a) U( x) Q (b) FSR/ x FSR/ x Figure.. Quantization noise models. (a) Ideal quantizer. (b) Quantizer with threshold level errors. Under these constraints U( x) is often modelled as a uniformly distributed random variable thereby simlifying the analysis of quantizer erformance. Quantizer oeration is frequently characterized by signal-to-noise ratio (SNR) which exresses (usually in decibels) the ratio of the outut signal ower to the outut noise ower. Since the quantization noise is assumed to be uniformly distributed on ( Q, Q ) (Fig..3) the Q Q ( x) Q Q x Figure.3. Distribution of quantization error.

60 .3 General Considerations 9 outut noise ower, or variance, can be easily calculated. σ Q x Q ( x) dx Q Q x Q dx Q Q 3 x3 Q 3Q Q Q ( ) 8 8 Q 3 3 (.) The ower of the outut signal (assuming a quantizer with unity gain) can be calculated as a function of the loading factor, LF. σ S LF ( FSR ) LF ( N Q ) LF Q N 4 (.3) where a midriser characteristic has been assumed. The quantizer SNR is therefore given by: σ S LF Q N 4 SNR Q σ Q Q 3 N LF (.4) where the subscrit Q modifying SNR refers to quantization noise as distinct from thermal noise or other deleterious error sources which comromise overall signal to noise ratio. In decibels, this exression simlifies to SNR Q 6.0N log ( LF )db. (.5) When evaluated for a sinusoidal inut with amlitude equal to Full-Scale (i.e. LF ) the

61 30 Chater Introduction SNR exression evaluates to SNR Q 6.0N +.76dB (.6) which is a frequently used equation for redicting otimum A/D erformance. For a 0-bit converter maximum SNR is 6.97 db. Another formulation based uon equation.4 and using the inut amlitude to determine the signal ower gives the following alternative exression for quantizer SNR under the condition of a sinusoidal inut: σ S A SNR Q σ Q Q 6 ( A Q) (.7) which when exressed in decibels simlifies to SNR Q 0log ( A Q) dB. (.8) This formula, equivalent to equation.5, emhasizes that under the resent assumtions, SNR deends only uon the inut amlitude relative to the quantizer ste, Q. A quantizer at eak loading (i.e. with the inut amlitude, A ( N ) Q) gives maximum signal-to-noise ratio σ S ( N )Q SNR Max 6 Q σ Q A N Q 3 N (.9) which equates to equation.6. Because they exress the relationshi between quantizer resolution and maximum achievable SNR, equations.6 and.9 can be used to assess the erformance of any quantizer relative to the ideal. By relacing the maximum achievable SNR by the actual SNR and solving for the equivalent resolution, N, a figure of merit called the number-of-effective-bits, N eff, results. N eff log ( 3 SNR ) Actual log ( 3 SNR ) Actual (.0)

62 .3 General Considerations 3 or if SNR is known in decibels, SNR ActualdB.76 N eff. (.) 6.0 The number-of-effective-bits (sometimes referred to as effective-number-of-bits, ENOB) is a commonly used metric for summarizing the erformance of non-ideal quantizers. Equation.5 redicts that the SNR in db will increase linearly with increasing loading factor (also in db). This relationshi holds until maximum SNR is achieved at LF for sinusoidal inuts. Further increases in loading factor yield decreasing SNR because the quantizer becomes overloaded (i.e. the quantizer inut exceeds Full-Scale) thereby roducing a severely distorted outut. In ractice, A/D converters encounter inuts which are more comlicated than simle sinusoids. Under conditions with such comlicated signal environments, the A/D converter inut can be simulated by a Gaussian noise source. The ratio of the inut noise ower to the quantization noise ower can then be used as a measure of quantizer fidelity. This erformance metric is call noise-ower-ratio, NPR, and is calculated in a manner similar to SNR. Equations. and.3 are again used to redict the quantization noise ower and signal noise ower resectively with the modification that the signal ower is due to a Gaussian noise inut as characterized by its ower relative to the quantizer loading factor, LF. Therefore, equation.5 redicts NPR as well as SNR if the roer value of LF is used. To minimize overload with a Gaussian inut, a substantially reduced LF as comared to the sinusoidal inut case must be used. For examle, reducing the Gaussian inut standard-deviation to one fourth of the Full-Scale amlitude (LF/4) reduces the robability of overload to %, simlified exression for NPR: erf( 4 ). This selection results in the following NPR Q 6.0N 7.7dB (.) The above simlified analyses are based uon the assumtions that quantization noise is uniformly distributed and uncorrelated with the inut signal. These assumtions are only aroximated in ractice, and to the extent that such aroximations are invalid the receding derivations will roduce erroneous results. In articular, the receding equations for SNR and NPR neglect overloading effects and therefore redict unbounded erformance for increasing loading

63 3 Chater Introduction factor. A more accurate analysis of quantizer distortion based on work by Max [9] and modified by Martin and Secor [0] which avoids the aforementioned simlifying assumtions follows. The mean-square quantization error for a quantizer whose inut is x with robability density function P x ( x) and whose outut is U( x) can be exressed as σ Q [ U( x) x] P x ( x) dx E { [ U( x) x] } (.3) where E { } reresents the exectation oerator. Note that the quantization error deends on the robability density of the inut and is not assumed to be uniformly distributed. If we define the quantizer outut as a noise comonent lus a signal comonent with a ossibly non-unity gain term, i.e., U( x) u gs + n Q (.4) then by suitable selection of the signal gain, g, we can ensure that the quantization noise, n Q, is uncorrelated with the outut signal, gs. Zero correlation between outut signal and outut noise means 0 E { gs n Q } E { gs ( u gs) } E { gsu} E { gsgs} (.5) which imlies ge { su} g E { s } (.6) Therefore, g E { su} E { s } (.7)

64 .3 General Considerations 33 This value of g ensures that gs is a minimum mean-square estimate of the inut, u. Note that the quantization error, n Q, is not assumed to be uncorrelated with the inut as in the revious simlified analysis. The SNR of the quantizer is given by SNR P S P T P S P N (.8) where P S is the outut signal ower, P S E { ( gs) } E { g s } g E { s } E { su} E { s } [ E { su} ] E s { } E s { } (.9) P T is the total outut ower, P T E { u } (.30) and P N is the outut noise ower resulting from inut noise. P N can be calculated in exactly the same manner as P S with the inut, s, taken to be the noise comonent of the total inut. This substitution results in an exression for P N corresonding to equation.9: [ E { nu} ] P N E { n } (.3) The SNR of a quantizer can be calculated given the statistical roerties of its inut by determining P S, P T, and P N which in turn requires evaluation of E { s },E { u },E { n },E { su},ande { nu}. This rocedure will be erformed for a sinusoidal inut and for a Gaussian inut. A quantization characteristic, f(x), can be reresented by

65 34 Chater Introduction M f( x) Q i IxT (, i, T i+ ) i 0 (.3) where I( x, a, b) is the indicator function defined by I( x, a, b) if a x < b { 0otherwise (.33) and M, Q i, and T i are as defined reviously in section.3.. For concreteness a biolar, midtread quantizer characteristic will be assumed resulting in M N quantization levels and M N threshold levels, Q i * M ( i + )Q 0 i M (.34) T i * M ( i )Q i 0 i M i M (.35) For a Gaussian inut with robability density function P n ( x) πσ e x σ (.36)

66 .3 General Considerations 35 (which is lotted in normalized form in figure.4) the total outut ower from the quantizer is.75 PPn(x) n ( x) * Aσ FFn(x) n ( GGn(x)/A n ( σ fx f(x) ().5 π P n ( x) σ G n ( x) σ x/sigma x σ Figure.4. The functions P n ( x), F n ( x), and G n ( x). By lotting the normalized versions P n ( x) σ, F n ( x), and G n ( x) σ versus x σ the shaes of the above functions become indeendent of σ. Also, P n ( x) σ equals G n ( x) σ.

67 36 Chater Introduction P T [ f( x) ] P n ( x) dx M i 0 Q i [ Fn ( T i ) F n ( T i + )] M M Q 0Fn ( T 0 ) + Q ifn ( T i ) Q j Q 0 + M i Q i i Q i ( )F n ( T i ) j F n ( T j ) Q M F n ( T M ) (.37) where F n ( x) (also lotted in figure.4) is the comlementary integral of the Gaussian robability density function, related to the familiar comlementary error function. F n ( x) P n ( u) du x (.38) Here the deendence uon σ has been left imlicit for clarity. In the reduction of equation.37 to its most simlified form the identities F n ( ) and F n ( ) 0 were used to relace F n ( T 0 ) and F n ( T M ) resectively. Note that if ideal thresholds are used T i is relaced by T* i, Q i is relaced by Q* i, and ( Q* i ) ( Q * i ) simlifies to T i *Q. The correlation between the inut Gaussian noise, u, and the outut noise, n, is E { nu} xf ( x)p n ( x) dx M Q i i 0 T i + xp n ( x) dx M i T i ( Q i Q )G i ( T ) n i (.39) where G n ( x), the comlementary integral of the weighted Gaussian robability density function,

68 .3 General Considerations 37 is given by: G n ( x) up n ( u) du x x σ π e σ x σ σ π e z dz (.40) and is lotted in figure.4. The inut noise ower is E { n } σ which can be combined with E { nu} to give the outut noise ower, [ E { nu} ] P n E { n } [ E { nu} ]. (.4) σ The resultant NPR at the quantizer outut is NPR Q P n P T P n (.4) where P s from equation.8 is ignored since a Gaussian noise source is being used. Note that this calculation requires aroximately M evaluations of F n ( x), the comlementary integral of P n ( x), and M evaluations of G n ( x), the comlementary integral of xp n ( x) for each value of the inut arameter σ, hence LF. A lot of the NPR based uon this method (Fig..5) indicates an aroximately linear deendence of NPR on LF for small values of LF in agreement with the simlified result in equation.5. Also evident in this region is the 6 db er bit deendence of NPR uon resolution. However, the new lot more accurately redicts NPR at high LF by accounting for the effects of overloading. These overloading effects are ignored by the revious aroach leading to erroneous results. Efficient system design mandates judicious selection of loading factor to otimize quantizer NPR, and the above results serve as a guide in this regard. Otimum loading factor, crest factor (the recirocal of loading factor), and NPR are tabulated in table.8 This information, also resented grahically in figure.6, can be used when selecting system gain arameters to achieve desired erformance in a comlex signal environment where A/D overloading is unavoidable. Similar analysis to that erformed for Gaussian noise inuts can be alied for the case of

69 38 Chater Introduction 70 NPR (db) N N Loading Factor (db) Figure.5. NPR of ideal midriser quantizer with Gaussian noise inut. Quantizer resolution indicated on curves. Resolution (Bits) Otimum Loading Factor (db) Otimum Crest Factor Otimum NPR (db) Table.8. Otimum quantizer loading and NPR for Gaussian noise inut.

70 .3 General Considerations 39 Resolution (Bits) Otimum Loading Factor (db) Otimum Crest Factor Otimum NPR (db) Table.8. Otimum quantizer loading and NPR for Gaussian noise inut Otimum Loading Factor (db) Maximum NPR (db) Resolution (Bits) 0 Figure.6. Otimum loading factor and NPR for Gaussian noise inut. sinusoidal inuts to ascertain quantizer SNR under such conditions. For a sinusoidal inut with

71 40 Chater Introduction amlitude A the robability density function is P s ( x) for x < A π A x 0otherwise (.43) which is lotted in figure.7. Identical analysis which led to the use of F n ( x), the.5.5 PPs(x) s ( * AA FFs(x) s ( GGs(x)/A s ( A ( ) ff(x) x.75.5 π xx/a A Figure.7. The functions P s ( x), F s ( x), and G s ( x). By lotting the normalized versions P s ( x) A, F s ( x), and G s ( x) A versus x A the shaes of the above functions become indeendent of A. comlementary integral of the Gaussian robability density function, in equation.37 necessitates

72 .3 General Considerations 4 utilization of F s ( x), the comlementary integral of the sinusoidal robability density (Fig..7): F s ( x) P s ( u) du x A x du π A u x asin ( ) x < A π A x < A 0 x> A (.44) Likewise, calculation of the correlation between the inut sinusoid and the outut signal requires evaluation of the comlementary integral of the weighted sinusoidal robability density function, G s ( x), (Fig..7) which has the form: G s ( x) up s ( u) du x π A x x A 0 x > A A x u du π A u. (.45) These two functions, F s ( x) and G s ( x), can be used with the following equations (analogous to equations.37 through.39 derived for the Gaussian inut case) to determine the total outut ower, P T, and E { su}. P T [ f( x) ] P s ( x) dx M i 0 Q i [ Fs ( T i ) F s ( T i + )] (.46) Q 0 + M i Q i Q i ( )F s ( T i )

73 4 Chater Introduction Since F s ( x) is for x < A and 0 for x> A this exression for P T can be further simlified to P T Q J + K i J Q i Q i ( )F s ( T i ) (.47) where J is the smallest integer such that A < T J and K is the largest integer such that T K < A. E { su} is calculated as follows: E { su} xf ( x)p s ( x) dx M Q i i 0 T i+ xp s ( x) dx M i T i ( Q i Q i )G s ( T i ). (.48) This exression can also be simlified if the inut amlitude is less than V FS to K E { su} ( Q i Q )G ( T ) i Q G s i s ( T i ) i J K i J (.49) where J and K are defined as above. Since the inut signal ower is known, E { s } A, the outut signal ower can be easily calculated [ E { su} ] P s E { s } [ E { su} ]. (.50) A

74 .3 General Considerations 43 This exression can be exanded using equation.49 giving K Q G s ( T i ) i J Q K P s A A G s ( T i ) K Q A π A T i i J K Q π i J T i ( ) A i J (.5) The signal to quantization noise ratio is then given by SNR Q P s P T P s (.5) where P n from equation.8 is ignored since a noiseless source is assumed. As in the Gaussian noise inut case, determination of the SNR requires M evaluations of F s ( x) and M evaluations of G s ( x) for each value of the sinusoidal inut amlitude, A. By erforming these calculations, the lot of SNR versus loading factor, LF, found in figure.8 results. Note the aroximate linear deendence of SNR on loading factor (when both are exressed in db) and the 6 db er bit deendence of SNR on resolution. Both of these trends are redicted by the simle aroximation of SNR found in equation.5. However, figure.8 indicates two additional characteristics not redicted by that equation. First, SNR degrades for loading factors which lead to cliing of the inut sinusoid (LF greater than 3 db). Second, SNR deviates slightly from linear deendence uon LF with each trace exhibiting a series of bums along the SNR curve. These bums arise because of the non-uniform robability density of the inut sinusoid which is near its eak a high ercentage of the time. As the loading factor increases, the sinusoid eak travels from one threshold to the next resulting in small variations in SNR. The local SNR minima occur when the inut sinusoid s eak equals a quantizer threshold while the local SNR maxima occur when the inut eak is midway between thresholds. The data dislayed in figure.8 is more exhaustive than might aear at first glance because for unclied sinusoidal inuts, SNR deends solely on the inut amlitude and not on the quantizer resolution. Therefore, a quantizer with a given loading factor and resolution

75 44 Chater Introduction 80 N 60 0 SNR (db) N Loading Factor (db) Figure.8. SNR of ideal midriser quantizer with sinusoidal inut. Quantizer resolution indicated on curves. behaves identically to another quantizer with different resolution but loading factor adjusted aroriately to maintain constant inut amlitude (measured in LSBs or Q stes). Since loading factor is inversely roortional to the quantizer Full-Scale Range, LF rmsofinut A A ( ) FSR M Q M Q A, (.53) N ( ) Q maintaining constant amlitude, A, requires a constant LF N roduct. Therefore, if an increase in resolution by one bit is accomanied by a reduction in loading factor of 6.0 db, identical SNR will be obtained. For examle, referring to figure.8, the SNR indicated on the N3 curve at LF 4 db (aroximately 9.7 db) is reeated exactly on the N4 curve at LF 0.0 db. This technique can be used to ascertain the SNR for any resolution quantizer (u to N) with any

76 .3 General Considerations 45 loading factor (assuming no cliing) from the figure. A -bit quantizer with 6 db loading factor can be seen from the N3 curve at LF 6.8 ( ( 3)) to exhibit an SNR of 7 db. Alternatively, the exclusive deendence of SNR on amlitude can be emhasized by lotting SNR versus amlitude, A, indeendent of quantizer resolution (Fig..9). In this format, the SNR is seen Actual SNR Aroximation SNR (db) Amlitude (LSBs) Figure.9. SNR of ideal midriser quantizer lotted versus sinusoidal inut amlitude. Aroximation is based uon equation.7. to deend solely on inut amlitude with local minima occurring when the amlitude equals a threshold value and maxima occurring between thresholds. The aroximation for SNR included in this grah along with the actual SNR data follows equation.7 and is accurate to within / db for amlitudes above 6 LSBs (Fig..30). Similar analysis to that erformed above for the Gaussian and sinusoidal inut cases can determine quantizer SNR (or NPR) for any inut signal whose statistics are known. Additionally, the above technique can be easily modified (by substituting T * i for T i and Q * i for Q i ) to redict

77 46 Chater Introduction SNR (db) Amlitude (LSBs) Figure.30. figure.9. Difference between actual SNR and aroximated SNR from erformance of non-ideal quantizers. This rocedure, although more accurate than other aroaches, is mathematically tedious and numerically intensive. Therefore, the simle and intuitive aroximation of equation.5 remains a owerful and frequently-used redictor of quantizer signal-to-noise ratio. Until now quantization noise ower has been calculated without regard to sectral content while determining signal-to-noise ratio. However, in many alications the quantization noise sectrum of an A/D converter is of articular interest. The sectrum of an instantaneous nonlinear quantization characteristic can be determined by calculating the Fourier series exansion of a quantizer outut in resonse to an inut sinusoid. Since the quantizer is assumed to be timeinvariant, its outut corresonding to an inut sinusoid with eriod T will also be eriodic with eriod T, thus ermitting a Fourier series exansion. If an inut signal x() t Acos ( πt T) is alied to an ideal quantizer (the rationale for selecting the amlitude A will become evident shortly), the resultant outut waveform will be

78 .3 General Considerations 47 Q() t f( x() t ) f( Acos ( πt T) ) (.54) where the function f( ) reresents the quantization characteristic reviously described in equation.3 (and reeated here for convenience). M f( x) Q i IxT (, i, T i+ ) i 0 (.55) and I( x, a, b) is the indicator function defined by I( x, a, b) if a x < b { 0otherwise (.56) Using equations.54 through.56 the quantizer outut can be exressed as M Q() t Q i I( t, t i, t i + ) i 0 (.57) where the values t i reresent the time at which the inut sinusoid crosses the threshold T i. t i T π cos T i ( ) A (.58) The motivation for selecting the sinusoidal amlitude as A is now aarent. Since the inverse cosine function monotonically decreases with its argument, selecting a negative sinusoidal amlitude ensures that the values of t i will increase with the index, i, from the smallest value to the largest as the thresholds, T i, index from the most negative value to the most ositive. This simle definition is roblematic however, because the inverse cosine is undefined for arguments whose magnitude is greater than, a condition which arises in equation.58 for any thresholds, T i, whose magnitude is greater than A. Since this situation imlies that some thresholds are never crossed and their corresonding quantization levels never aear at the outut, Q() t, a simle solution lies in restricting the range of summation in equation.57 to those values of Q i which actually occur for a given inut level, A. The range over which the time oints t i are defined is likewise suitably limited by using the variables J and K where J is the smallest integer such that A< T J and K is

79 48 Chater Introduction the largest integer such that T K < A. The quantizer outut becomes K Q() t Q i I( t, t i, t i+ ) for 0<t<T i J (.59) where the time instances t i are t i T i T π cos ( ) J i K A (.60) The endoints of the time interval are arbitrarily chosen to be t J 0 and t K+ T. Also, the symmetry of the inut cosine can be used to define the quantizer outut over the interval T t T. Q() t Q( T t) for T t T (.6) The eriodic quantizer outut can be exressed as a Fourier series Q() t a 0 + a n n cos nπt nπt ( ) + b T n sin ( ) T (.6) where the coefficients a n and b n of the exansion are: T a n T Q() t nπt cos ( ) T 0 (.63) T b n T Q() t nπt sin ( ) T 0 (.64)

80 .3 General Considerations 49 Substituting the exression for Q() t (equation.59) into the definition for a n yields T K 4 a n T Q i It (, t i, t i+ ) cos 4 T πn 0 i J K Q i i J t i + t i K Q i i J K πn ( Q i Q i ) Q πn i J K i J sin nπt cos ( ) dt T nπt i + sin ( ) T nπt i ( ) T nπt i sin ( ) T nπt ( ) dt T nπt i sin ( ) T (.65) which can be further simlified by noting that each value of t i is multilied by the term π T. By modifying the definition of t i to exclude the unnecessary term T π, a n simlifies to a n K Q nt πn sin ( i ) i J (.66) with t i defined as T i t i cos ( ) for J i K A (.67) Because Q() t is an even function, it is orthogonal to sin ( nπt T) ; therefore, all of the coefficients are zero. The exansion for Q() t is therefore b n Q() t a 0 + a n n cos nπt ( ) T (.68)

81 50 Chater Introduction The ower in each harmonic, P ( n), is simly related to its Fourier coefficient: P ( n) a n (.69) When comared to the ower in the fundamental comonent of the outut signal the harmonic distortion results. HD n P ( n) a n P ( ) a a n a (.70) which when exressed in dbc becomes a n HD n 0log 0log a a n a (.7) The coefficient of the fundamental comonent, a, can be simlified as follows a K T i Q cos π sin ( ( )) A i J K Q π i J T i ( ) A (.7). Here the notation P ( n) is used for the ower in the n-th harmonic to avoid confusion with the noise ower, P n.

82 .3 General Considerations 5 Using equation.69 with equation.7 to calculate the fundamental signal ower gives P s P a Q ( ) π K i J Q K π T i ( ) A i J T i ( ) A (.73) Notice that this exression for signal ower is identical to equation.5 which redicts quantizer outut signal ower based uon the statistics of the inut signal Equation.73 indicates that P s is the weighted sum of ositive ordinates along the unit circle as the abscissa is steed uniformly within the range (,). It is instructive to examine the form of the Fourier coefficients, a n, to ascertain the nature of the distortion roducts emanating from the quantizer. The exressions for an and ti can be combined to give the consolidated equation a n K T i Q ncos πn sin ( ( )) A i J (.74) The argument of this summation, sin ( ncos ( T A )), closely resembles the n-th Chebyshev i Polynomial, T n ( x), defined as: T n ( x) cos ( ncos ( x) ) (.75) which can also be exressed by the recurrence relation + xt n ( x) T n ( x) T n (.76)

83 5 Chater Introduction leading to the following olynomial forms for the first 4 functions: T 0 x T T x T 3 4x 3 3x T 4 8x 4 8x + (.77) sin ( ncos ( x) ) can be exressed in terms of T n ( x) by noting that d T n ( x) dx T n ( x) sin ( ncos ( x) ) n x (.78) so that S n ( x) sin ( ncos ( x) ) T n ( x) x n (.79) The first few functions of sin ( ncos ( x) ), abbreviated S n ( x) for simlicity, are S 0 0 S x S x x (.80) S 3 ( 4x ) x S 4 ( 8x 3 4x) x The behavior of S n ( x) can most easily be envisioned when ket in the form sin ( ncos ( x) ). The argument of the sine function, cos ( T A ) (lotted in figure.3 for reference), is a i monotonically increasing function of its argument sanning from 0 to π as the threshold index, i, swees from J to K. The sine of this argument (when the arameter n is equal to ) exhibits one maximum when T i A is zero and is equal to zero itself at both endoints ( T i A ± ). In

84 .3 General Considerations 53 π 3π/4 ( ) cos acos(-x) x π/ π/ x Figure.3. The inverse cosine function. fact, this function is the uer unit semi-circle discussed above in the calculation of P s. As the arameter n is increased, the range covered by the argument of the sine function increases from ( 0, π) to ( 0, nπ). Therefore, the number of extrema in the function sin ( ncos ( T A )) i increases to n. This function is lotted for several values of n in figure.3 where it can be seen that sin ( ncos ( T A )) is an even function for all n odd and an odd function for all n even. When i n is even, the odd symmetry exhibited by the sine function ensures that the summation used to calculate a n in equation.74 equals exactly 0. This brings out the imortant fact that a erfect quantizer roduces no even harmonics whatsoever. The even symmetry of sin ( ncos ( T A )) when n is odd enables the summation in equation.74 to be calculated i with half the original number of function evaluations. The quasi-eriodic nature of the sin ( ncos ( T A )) functions lotted in figure.3 is reminiscent of the assband rile of i Chebyshev filters whose characteristics are defined by the related Chebyshev olynomials.. The absence of even harmonics in a quantizer outut sectrum should not be surrising since the quantization characteristic itself is a urely odd function of its inut variable and therefore has a olynomial exansion with only odd terms.

85 54 Chater Introduction n n ( ncos ( x )) sin(n*acos(-x)) sin.5 0 n 3 n n x Figure.3. The function sin ( ncos ( T A )) i for several values of n. sin ( ncos ( T A )) i Equation.74 can be used with equation.7 to calculate the harmonics comrising the sectrum of an ideal 8-bit quantizer (Fig..33). The maximum harmonic distortion for lower-order harmonics is near 7 dbc, or 9N dbc. Additionally, a slightly higher ower harmonic occurs of order aroximately 800. This behavior can be comared to that of an ideal 0-bit quantizer (Fig..34) which exhibits maximum ower lower-order harmonics of aroximately -90 dbc, again equal to -9N dbc. The eak harmonic, which is slightly higher in ower than -9N dbc, occuies a harmonic osition just above The relative ower and osition of the eak harmonic in quantizer outut sectra generally follow the trends alluded to above for the secific 8-bit and 0-bit cases. In articular, the osition of the eak harmonic is closely aroximated by π N as shown in figure.35 which lots the eak harmonic number versus inut amlitude measured in LSBs. In the aroximation π N, N refers to the maximum number of effective bits for a given inut amlitude. So, for examle, an inut amlitude of 6 LSBs equates to log ( 6) 5 maximum effective bits, or N 5 while an amlitude of 5 LSBs corresonds to N The maximum harmonic ower generated by an ideal quantizer is aroximately -9N dbc where again

86 .3 General Considerations SDR (db) Harmonic Number Figure.33. Harmonic levels for an ideal 8-bit midriser quantizer. N is the effective resolution assuming full loading with a sinusoidal inut. Therefore, N 7.5 imlies that thresholds are traversed by an inut sinusoid with amlitude This quantizer, with 8 thresholds, will exhibit identical erformance to any quantizer with higher resolution but the same inut amlitude because thresholds which are not traversed by the inut waveform do not enter into the SNR or distortion calculations which limit their summations to the range of activated thresholds. A lot of the eak harmonic distortion versus inut amlitude as exressed by maximum effective resolution (Fig..36) indicates very close conformance to the aroximation -9N dbc. Also lotted in the same figure is the relative ower in the third harmonic, HD 3, which conforms to the -9N dbc aroximation as well. The location of the eak distortion roduct at harmonic number π N arises because of the quasi-eriodic nature of the function sin ( ncos ( T A )) as next exlained. The ower in i any distortion roduct (according to equation.74 which is reeated below for convenience) deends uon the sum of samles of sin ( ncos ( T A )) which varies as a function of the i harmonic number, n.

87 56 Chater Introduction SDR (db) Harmonic Number Figure.34. Harmonic levels for an ideal 0-bit midriser quantizer. a n K T i Q ncos πn sin ( ( )) A i J (.8) To maximize the sum comrising a n, all of the samles, J i K, should be at or near a eak of sin ( ncos ( T A )). Two examles which illustrate this rincile are deicted in figure.37 i where sin ( ncos ( T A )) and its samles are lotted for the cases N 4 whose eak i harmonic is number 47 and N 5 whose eak occurs at n 99. Notice that in each case nearly all of the samles occur at or near a function extrema. The condition required for such samle lacement, where the samles are located at the uniformly saced locations T i A, is that the samle after the abscissa midoint equal the samle at the abscissa midoint. That is, ncos T M + sin ( ( )) ncos T M sin ( ( )) A A (.8)

88 .3 General Considerations Peak Harmonic Number Aroximation, Aroximate Peak π N 600 Peak Harmonic Number Inut Amlitude (LSBs) Figure.35. Peak harmonic number versus analog inut amlitude. This exression can be simlified by using the ideal values of T M + and T M. 0 sin ( ncos ( )) sin ( ncos ( )) A A sin ( n π ) (.83) Taking the inverse sine of both sides of equation.83 introduces an ambiguity characterized by the integer m which secifies by how many eriods the arguments of the two sinusoids differ. The resultant condition for eak distortion becomes ncos ( ) n π A + mπ (.84)

89 58 Chater Introduction 0-0 Peak Harmonic Power (dbc) Peak Harmonic Power 3rd Harmonic Power 9N Aroximation Quantizer Resolution (Bits) Figure.36. Peak harmonic ower for ideal midriser quantizer. which simlifies to A m n π π cos ( + ). (.85) sin ( m n π) Therefore, n π m sin m π ( A) A m πa (.86) where the aroximation used relies uon sinx x for x small, a condition which holds for most values of A. If full loading is assumed, A can be exressed in terms of the quantizer resolution by using the relationshi N A + which rearranges to give A ( N ) N. Using

90 .3 General Considerations 59.5 sin(99acos(x)) sin(47acos(x)) x Figure.37. The function sin ( ncos ( x) ) evaluated at x T i A for eak harmonics. (lower) N 4n, 47. (uer) N 5n, 99. this exression for A in equation.86 gives the final condition for maximum distortion: n m π N m π N (.87) where m is any nonzero integer. Since the Fourier coefficients a n deend on the recirocal of n as

91 60 Chater Introduction well as the sum of the samles of the function sin ( ncos ( T A )), the minimum value of n which satisfies equation.87 will give the largest distortion ower. Therefore, m yields the highest harmonic ower resulting in n maxhd π N (.88) as redicted emirically from the lots of quantizer distortion sectra. Notice that local distortion maxima will occur at multiles of n maxhd as redicted by equation.87. Such maxima are easily noticeable in figure.34 where the eak harmonic number is just over 3000 ( π 0 ) and local maxima occur just above 6000 and 9000 corresonding to m from equation.87 taking on values of,, and 3, resectively. The magnitudes of the local maxima are aroximately -6 db and -0dB relative to the absolute maximum corresonding to 0log(/) and 0log(/3) as exected. Martin and Secor [0] have shown that the relative ower of the 3rd harmonic outut from a fully loaded N-bit A/D, -9N dbc, can be redicted from the Fourier series exansion of the quantization error emanating from the converter in resonse to a sinusoidal inut. The analysis relies uon an identity which exresses the Fourier coefficients in terms of Bessel functions with known aroximations. Note that the 3rd harmonic is found emirically to lie within a few decibels of the eak harmonic for most cases (see figure.36) so that the -9N dbc aroximation for HD 3 also serves as a good aroximation for eak harmonic ower. For a fully loaded quantizer the result is P 3 HD 3 P ( ) 3 N 3N (.89) which when exressed in decibels simlifies to P 3 HD 3 0log 0log ( 3N ) 30Nlog ( ) 9NdBc P (.90) When the quantizer is less than fully loaded, equation.89 can be generalized by exressing the number of quantization codes outut from the converter as a function of the inut amlitude, A, rather than as a function of the quantizer resolution, N. That is, N in equation.89 is relaced by

92 .3 General Considerations 6 A Q giving HD 3 0 log dbc ( A Q) 3 [ 30log ( A Q) + 30log ( ) ]dbc [ 30log ( A Q) + 9]dBc (.9) Alternatively, the inut amlitude can be exressed with the loading factor, LF (equation.9), as A Q N LF (.9) This exression can be substituted into the first line of equation.9 giving HD 3 0 log dbc ( A Q) 3 0log ( N LF ) 3 dbc [ 9N + 30log ( ) + 30logLF ]dbc [ 9N logLF ]dbc (.93) Notice that if the loading factor is exressed in decibels (i.e. LF indb 0logLF ) then.93 further simlifies to HD 3 [ 9N LF indb ]dbc (.94) Equation.94 gives the very simle and imortant result that the 3rd harmonic (emirically seen to be near the highest-ower harmonic) can be aroximated by -9NdBc at full loading ( LF 3dB ). Also, the distortion degrades by.5 db for each db decrease in the loading factor. This relationshi leads to the counter-intuitive but correct conclusion that distortion increases for decreasing inut signal ower. The surrising correlation between distortion and signal ower can be justified qualitatively by noting that the quantization error remains bounded by one quantization ste, Q, regardless of inut amlitude. Therefore, the fixed distortion ower is a larger fraction of smaller inut signals than of

93 6 Chater Introduction larger inut signals; and harmonic distortion degrades for lower level inuts corresondingly. The above results for quantizer distortion sectra assume ideal quantization characteristics described by uniform threshold lacement. Real quantizers will exhibit imerfections in threshold locations which are generally characterized statistically or by a olynomial exansion which includes higher-order terms than the linear exansion describing the ideal thresholds. The effect of such non-idealities on quantizer outut sectra can be ascertained by studying their corresonding imact on the summations which determine the Fourier coefficients, a n, as detailed in equation.74 and deicted in figure.3. First, since random erturbations of the ideal thresholds destroy the symmetry of the samles of sin ( ncos ( T A )), the even-order coefficients no longer sum to i exactly zero. Therefore, even harmonics are generated by non-ideal quantizers. Second, the relative significance of higher-order harmonics is generally reduced because these terms become large only when a secific relationshi holds between threshold lacement and eaks of the function sin ( ncos ( T A )). Such alignment is highly unlikely in the resence of random threshold i erturbations. These two assertions are borne out by the examle below (Fig..38) which deicts the outut sectrum for an 8-bit quantizer having Gaussian distributed threshold errors with standard deviation equal to one quarter of an LSB. Clearly the even-order harmonics are significant and the higher-order terms no longer limit the surious-free dynamic range (SFDR). The dominant harmonic, however, remains near the redicted value of -9N dbc. As described in section 0., the effect of deterministic threshold erturbations on the sectra of quantized signals remains an imortant area where better understanding is needed. Certain A/D converter architectures give rise to redictable threshold errors which ultimately limit linearity; however, determining distortion sectra based uon these errors is still imractical. For examle, biolar flash converters tyically exhibit threshold errors caused by bias currents flowing through a resistive reference-generation ladder. This effect, sometimes called reference bowing, is redictable, but its effect on the converter outut sectrum is difficult to ascertain. Also, multistage A/D converters with imerfect matching between stages exhibit threshold lacement with eriodic deviations from the ideal. Again, the threshold locations are redictable and even admit a simle olynomial exansion; however, the concomitant effect on the converter s sectrum. As in the case of an ideal quantizer, this result should not be surrising since threshold errors destroy the odd symmetry of the quantization characteristic uon which a olynomial exansion comosed of urely odd harmonics is based.

94 .3 General Considerations SDR (db) Harmonic Number Figure.38. Harmonic levels for an 8-bit midriser quantizer with /4 LSB rms threshold errors. is difficult to determine in analytic form. Develoment of techniques for redicting such effects would rove invaluable for high-erformance data converter design..3.3 Fundamental Limits to Performance Many factors imact overall system oeration and can limit erformance below the ideal redicted in the revious section. Several such factors which resent limits on A/D converter erformance will now be discussed. In a 50 Ω system, thermal noise induced by the source resistance limits A/D converter resolution to a sub-ideal value which can be calculated if the system bandwidth, f, and signal amlitude, V fsr, are known []. The noise ower available from the source resistance is P n kt f (.95)

95 64 Chater Introduction where k is Boltzmann s constant, T is the temerature in degrees Kelvin, and f as reviously defined is the bandwidth of the system. The maximum signal ower is V fsr P s ( ) R (.96) where R is the source resistance and full-scale quantizer loading is assumed. The maximum achievable SNR of an A/D converter oerating under such circumstances is: V fsr ( ) R SNR Thermal kt f V fsr. (.97) 8kTR f By using this exression for SNR in equation.0 the maximum attainable quantizer resolution as limited by thermal noise is seen to be V fsr N eff log. (.98) 3 8kTR f For a given quantizer inut range, V fsr, achievable resolution, N eff, is inversely roortional to bandwidth and absolute temerature as shown in figure.39. As can be seen from this grah, 0 bit resolution is within the thermal limit for bandwidths well above the 50MHz design goal. Aerture jitter, which is the noise induced uncertainty in the otherwise eriodic samling interval, also laces a fundamental limit on achievable resolution [], [], [3], [4] for the following reason. If a signal is changing in time with a maximum slew rate equal to S, and its value is to be determined with accuracy dv, then the samling instant, T must be defined with accuracy dt (Fig..40 ) such that dt dv S (.99) where the timing uncertainty, dt, is referred to as the aerture jitter, τ jitter.if the A/D converter requires N bit resolution, then to ensure amlitude error less than ±/ LSB, dv must be limited

96 .3 General Considerations 65 0 V fsr.0v T -55C T 5C T 5C 8 V fsr 0.5V Resolution (bits) 6 V fsr.5v 4 R source 50Ω Bandwidth (MHz) Figure.39. Thermal limit to achievable resolution. such that dv V fs N V fs N. (.00) The maximum sloe of a sinusoidal inut signal of amlitude V fs and frequency f in is S πf in V fs resulting in τ jitter dt dv S V fs N πf in V fs ( N + ). (.0) πfin This constraint shows the maximum aerture jitter consistent with N bit resolution and is lotted

97 66 Chater Introduction V fs V() t V fs sin ( πf in t) Sloe dv() t dt 0 V fsr V fs dv dv T dt dt Q V fs N V fs Figure.40. Aerture uncertainty causes amlitude errors. versus bandwidth, f in, for various values of resolution, N, in figure N Aerture Jitter (s) 0 N Analog Inut Bandwidth (MHz) Figure.4. Maximum aerture jitter consistent with / LSB errors for various values of resolution.

98 .3 General Considerations 67 Alternatively, equation.0 may be solved for N in terms of τ jitter giving N eff log ( ). (.0) πτ jitter f in This relationshi, lotted in figure.4 for various values of τ jitter, shows that to achieve 0 Maximum Attainable Effective Bits τ jitter s 0s 00s τ jitter ns tas ta0s ta00s tans Analog Inut Bandwidth Figure.4. Maximum attainable resolution limited by aerture jitter. effective bits of resolution, τ jitter must be ket well below 0s; and to maintain adequate margin for this arameter a value close to s is desirable. This constraint on accetable jitter mandates use of a track-and-hold circuit receding the 0-bit quantizer and further imlies that on-chi clock buffer circuitry must be designed secifically to revent degradation of the hase noise from that resented to the A/D converter from outside clock and signal sources. Unavoidable threshold level errors caused by device mismatches also reduce maximum achievable SNR. The effect of such imerfections on the quantization error waveform is shown in

99 68 Chater Introduction figure. which is reeated here for convenience (Fig..43). As seen in this figure, threshold -FSR/ -FSR/ Q Q U( x) Q (a) U( x) Q (b) FSR/ x FSR/ x Figure.43. Quantization error waveforms. (a) Ideal quantizer. (b) Quantizer with threshold level errors. errors increase the maximum amlitude and the variance of the quantization error waveform thereby increasing the ower in the noise comonent of the SNR equation. To determine the quantization noise ower in the resence of threshold errors, the quantizer error is now studied in more detail. The quantization error, Q( x) U( x), reresents the difference between the quantizer outut,, and the quantizer inut, x, as defined in equation. and reeated here: U( x) Q( x) x (.03) The waveform Q( x), and hence U( x), is determined solely by the M thresholds T i, i,, M which differ from the ideal thresholds, T* i, according to ε k T k T * k (.04)

100 .3 General Considerations 69 where is the quantizer offset. The quantization error, Q( x),equals zero when the inut is equal to the outut. Since the quantizer outut takes on the M discrete values Q* j, j 0,, M, the quantization error vanishes for the M values of inut equal to Q* j. These relationshis are deicted succinctly for one quantizer ste in figure.44. The noise ower emanating from the U( x) Q + ε j Q Q j * x Q * j ε j x Q + ε j Q * j x T j T j * Q j * Q Figure.44. Segment of quantization error waveform with non-zero threshold errors,. ε j quantizer can be calculated by dividing the inut range into a discrete set of subranges and determining the variance of each corresonding outut waveform. If the subranges comrise the set A j, j,, L then, σ n E { U( x) } L E { U( x) x A j }P x ( xx A j ) j (.05)

101 70 Chater Introduction If the subranges, A j, are taken to be the regions between adjacent nulls in the quantization error, U( x), and further, the inut is assumed uniformly distributed on each such interval, then the noise due to the j-th interval, σ nj, can be calculated according to the following equation derived from figure.44. σ nj E { U( x) x A } E { U( x) Q * j < x Q* j } Q T j Q * j j ( x) dx + ( Q j x) dx Q * j Q j * T j (.06) which can be simlified by using the substitution y x Q * j in both integrals and recalling that Q* j Q * j Q to obtain σ nj Q Q + Q 0 ε j Q ( y) dy + ( Q y) dy Q Q + y dy ( Q Qy) dy Q + 0 Q + ε j Q Q 3 y3 0 ( Q y Qy Q + ) Q + εj Q 3 Q3 Q 3 Q ε j Q Q + ( 4 + Qε j + ε j ) Q + ε j ε j (.07) The total quantizer outut noise ower, σ n, is calculated by using this result for σ nj in equation.05. σ n L σ nj j P x ( xx A j ) (.08)

102 .3 General Considerations 7 which can be further simlified if a uniformly distributed inut is again assumed. σ n L L j Q σ nj + σ e (.09) where σ e is the rms threshold error as defined in equation.6. The first term on the right side of equation.09 is the quantization noise of an ideal quantizer as derived in equation.. The second term is the added noise ower brought on by imerfect lacement of thresholds. This new exression for outut noise ower can be used in lace of the simler exression Q in equations such as.4 and.7 to redict SNR for non-ideal quantizers. The receding derivation assumes that the inut signal exhibits a uniform robability density function. For many inuts this assumtion is unjustified and more exhaustive analysis must be erformed to obtain accurate redictions of quantizer erformance under non-ideal conditions. In such cases, the techniques of section.3. can be alied with the actual threshold levels, T i, used in lace of the ideal values, T * i, to accurately redict SNR erformance. Comarator regeneration time also laces a fundamental limit on achievable resolution [], [5], [6] for the following reason. If a comarator is given a finite time to regeneratively roduce a logic-level outut, then for some range of differential inut values near zero, the comarator outut will not be large enough to be unambiguously interreted by succeeding encoding logic. This logic can therefore roduce erroneous outut codes which increase the noise ower in the quantizer outut waveform thereby diminishing SNR. Such coding errors have been called conversion errors, rabbit errors, sarkle codes, and metastability errors. The nature of the digital outut roduced under conditions of metastability errors deends greatly on the outut coding format used. With most forms of binary coding, metastability errors manifest themselves as outut code errors which can be modelled as a random N-bit word. The ower contributed to the quantizer outut noise in this case is: E { n ConversionError } ( N Q) (.0) Note that this result follows directly from figure.3 and equation. which redict the quantizer outut noise to be Q for oututs uniformly distributed on ( Q, Q ). In the resent

103 7 Chater Introduction case, the outut (under the conditions of a metastability error and binary coding) is resumed to be uniformly distributed on ( N Q, N Q ). Equation.0 follows directly. The outut noise due to metastability errors becomes σ n E { n MetastabilityError }P ME ( N Q) P ME Q N P ME (.) where P ME is the robability of a metastability error. If Gray coding is used rather than binary, metastability errors manifest themselves as a single bit error in an otherwise accurate outut codeword. This beneficial effect arises because in Gray coded A/D converters each comarator influences one and only one outut bit. Therefore, a metastable comarator causes the corresonding bit to become indeterminate, but all other bits behave correctly (ignoring the unlikely event of two metastable comarators during one conversion). In fact, this characteristic is the chief rationale for imlementing Gray encoding in A/D converters. When a metastability error gives rise to an erroneous outut bit, the amount of noise added to the outut corresonds to an amlitude error equal to one quantizer ste, Q; however, with robability / the bit in question will assume the correct value. Therefore, the exected meansquare noise given a metastability error is: E { n MetastabilityError } ( Q + 0 ) (.) so the noise ower due to metastability errors in Gray coded converters becomes Q σ n P ME Q 6P ME (.3) which is less than the noise ower in a binary converter (equation.) by the factor N 6. This factor reresents an extreme noise reduction for even modest resolution A/D converters. The maximum SNR with metastability errors can be calculated by using the receding exressions for noise ower with equation.7 which gives SNR as a function of inut amlitude and quantizer ste-size.

104 .3 General Considerations 73 A ( N ) Q SNR Q Q Q N Q 8 Q (.4) where full loading ( A ( N ) Q) has been assumed for maximum SNR. By relacing the denominator of equation.4 which is the noise due to quantization with the noise exressions develoed for metastability errors (equations. and.3) the maximum achievable SNR given metastability errors results. For binary encoding: N Q 8 SNR ME ( Q ) N P ME 3 P ME (.5) and for Gray encoding: N Q 8 SNR ME Q ( ) 6P ME N 4P ME (.6) where the subscrit ME modifying SNR distinguishes the noise as that caused by metastability errors. Equation.0 can be used to convert the above SNR exressions into effective bits. For binary encoding: N effme log ( ) P ME log ( P ME ) (.7) and for Gray encoding N effme log N 6P ME log N 6 log ( P ME ) N log ( P ME ) log ( 6) (.8) The robability of a metastability error deends uon the statistics of the inut signal, but if a

105 74 Chater Introduction uniformly distributed inut is assumed, P ME is given by [woodward] P ME V L AQ (.9) where V L is the minimum amlitude voltage which will unambiguously be interreted as an aroriate logic level (so V L reresents the range of ambiguous voltages), A is effective gain of a comarator at the end of the latch mode, and Q is the quantizer ste size. P ME is seen to be the ratio of the ambiguous voltage range (referred to the comarator inut) divided by total inut range seen by the same comarator. The effective comarator gain, A, which is deendent uon the dynamic comarator resonse and the time allowed to regeneratively establish an outut state can be described as A A 0 e t τ (.0) where A 0 is the DC gain of the comarator and τ is the time-constant (assumed first order) which governs the comarator resonse during latch mode. The robability of metastability then becomes P ME V L A 0 Q e t τ (.) where t, the amount of time the comarator is allowed to regenerate, is governed by the A/D converter samle rate, f s. The term V L A 0 Q is on the order of 0 for reasonable values of V L, A 0, and Q. Additionally, τ is ideally equal to the recirocal of ω t, the radian unity gain cut-off frequency of the transistors comrising the latch; however in ractical circuits τ is usually several times this value: 5 τ πf t (.) Equation. can be used with equation.7 to redict maximum effective resolution as limited

106 .3 General Considerations 75 by metastability errors with binary encoding. N effme log ( P ME ) log V L A 0 Q e t τ log V L A 0 Q + t τ log e (.3) If the time allowed for regeneration, t, is equal to half the samle eriod, T s, and the inut bandwidth of the A/D converter is limited by Nyquist s condition ( f in f s ( T s ) ) then t in equation.3 can be relaced by ( 4f in ) resulting in N eff log e 8f in τ log V L A 0 Q 8lnf in τ log V L A 0 Q (.4) where ln ( x) is the natural logarithm function. N eff as calculated by equation.4 is dislayed grahically in figure.45 which indicates that for an effective resolution of 0-bits and an inut bandwidth of 50MHz, the comarator time-constant, τ, must be less than 300 s. The achievable resolution for Gray encoding can be calculated in a similar fashion to equation.4 giving N eff log N log e 6 8f in τ log V L + A 0 Q N + 8lnf in τ log V L log A 0 Q ( 6) (.5) where N is the number of bits in the Gray-encoded outut word. Notice that the achievable resolution as limited by metastability errors in this case is greater than that achievable in the binary case so long as N > log ( 6).9; that is, for all resolutions of ractical interest. For a Gray encoded A/D converter to achieve 0 bits of resolution with a 50MHz inut bandwidth τ can be slightly longer than ns, a factor of three higher than the binary encoded configuration. Alternatively, with the same comarator time constant the Gray converter exhibits three times the

107 76 Chater Introduction 0 Achievable Resolution (Bits) s 00s τ 00s V L A o Q 0 τ 000s Inut Bandwidth (MHz) Figure.45. Achievable resolution as limited by metastability errors. bandwidth as the binary converter. In some alications, notably video signal rocessing, SNR is not the most imortant measure of erformance degradation due to metastability errors. Rather, eak error is the metric used for such characterization because large code errors when reconstructed via D/A conversion aear on a video monitor as noticeable ixel amlitude discontinuities. These momentary discontinuities, a white ixel on a dark background or vice-versa, seem to the human visual system like sarkles hence the name sarkle codes. Gray encoding hels greatly in this regard by limiting the maximum metastability-induced error to one LSB.

108 .3 General Considerations 77 References [] A. Macovski, Medical Imaging Systems. Prentice Hall, 983. [] G. S. Kino, Acoustic Waves: Devices, Imaging, and Analog Signal Processing. Prentice Hall, 987. [3] D. H. Sheingold, ed., Analog Digital Conversion Handbook. Prentice Hall, third ed., 986. The Engineering Staff of Analog Devices. [4] Y. Ninomiya, HDTV broadcasting systems, IEEE Communications Magazine, vol. 9,. 5, Aug. 99. [5] K. Rush and P. Byrne, A 4GHz 8b data acquisition system, in International Solid State Circuits Conference, , IEEE, Feb. 99. [6] S. Swierkowski, D. Mateda, G. Cooer, and C. McConaghy, A sub-00 icosecond GaAs samle-and-hold circuit for a Multi-Gigasamle/Second integrated circuit, in International Electron Device Meeting,. 7 75, IEEE, 985. [7] W. R. Bennett, Sectrum of quantized signals, Bell System Technical Journal, vol. 7, , July 948. [8] A. Gersho, Princiles of quantization, IEEE Transactions on Circuits and Systems, vol. CAS-5, , July 978. [9] S. Max, Quantizing for minimum distortion, IRE Transactions on Information Theory, vol. IT-6,. 7, Jan [0] D. R. Martin and D. J. Secor, High seed analog to digital converters in communication systems: Terminology, architecture, theory, and erformance, tech. re., TRW Electronic Systems Grou, Redondo Beach, CA, Nov. 98. [] L. E. Larson, High-seed analog-to-digital conversion with GaAs technology: Prosects, trends and obstacles, in International Symosium on Circuits and Systems, , IEEE, 988. [] R. J. van de Plassche and P. Baltus, An 8-bit 00-MHz full Nyquist analog-to-digital converter, IEEE Journal of Solid State Circuits, vol. SC-3, , Dec [3] T. Wakimoto, Y. Akazawa, and S. Konaka, Si biolar -GHz 6 bit flash A/D conversion LSI, IEEE Journal of Solid State Circuits, vol. SC-3, , Dec [4] M. Shinagawa, Y. Akazawa, and T. Wakimoto, Jitter analysis of high-seed samling systems, IEEE Journal of Solid State Circuits, vol. SC-5,. 0 4, Feb [5] C. E. Woodward, K. H. Konkle, and M. L. Naiman, A monolithic voltage-comarator array for A/D converters, IEEE Journal of Solid State Circuits, vol. SC-0, , Dec [6] B. Zojer, R. Petschacher, and W. A. Luschnig, A 6-Bit/00-MHz full Nyquist A/D converter, IEEE Journal of Solid State Circuits, vol. SC-0, , June 985. [7] M. K. Mayes and S. W. Chin, A multiste A/D converter family with efficient architecture, IEEE Journal of Solid State Circuits, vol. SC-4, , Dec. 989.

109 78 Chater Introduction [8] M. P. Kolluri, A -bit 500-ns subranging ADC, IEEE Journal of Solid State Circuits, vol. SC-4, , Dec [9] Y. Sugimoto and S. Mizoguchi, An exerimental BiCMOS video 0-bit ADC, IEEE Journal of Solid State Circuits, vol. SC-4, , Aug [0] T. Shimizu, M. Hotta, K. Maio, and S. Ueda, A 0-bit 0-MHz two-ste arallel A/D converter with internal S/H, IEEE Journal of Solid State Circuits, vol. SC-4,. 3 0, Feb [] S. H. Lewis and P. R. Gray, A ielined 5-Msamle/s 9-bit analog-to-digital converter, IEEE Journal of Solid State Circuits, vol. SC-, , Dec [] S. H. Lewis, H. S. Fetterman, G. F. Gross, Jr., R. Ramachandran, and T. R. Viswanathan, A 0 b 0 Msamle/s analog-to-digital converter, IEEE Journal of Solid State Circuits, vol. SC-7, , Mar. 99. [3] R. Petschacher, B. Zojer, B. Astegher, H. Jessner, and A. Lechner, A 0-b 75-MSPS subranging A/D converter with integrated samle and hold, IEEE Journal of Solid State Circuits, vol. SC-5, , Dec [4] R. E. J. van de Grift, I. W. J. M. Rutten, and M. van der Veen, An 8 bit video ADC incororating folding and interolation techniques, IEEE Journal of Solid State Circuits, vol. SC-, , Dec [5] M. Hotta, T. Shimizu, K. Maio, K. Nakazato, and S. Ueda, A -mw 6-b video-frequency A/D converter, IEEE Journal of Solid State Circuits, vol. SC-, , Dec [6] B.-S. Song, M. F. Tomsett, and K. R. Lakshmikumar, A -bit Msamle/s caacitor error-averaged ielined A/D converter, IEEE Journal of Solid State Circuits, vol. SC-3, , Dec [7] Y. Akazawa, A. Iwata, T. Wakimoto, T. Kamato, H. Nakamura, and H. Ikawa, A 400MSPS 8b flash AD conversion LSI, in International Solid State Circuits Conference, , IEEE, Feb [8] C. W. Mangelsdorf, A 400-MHz inut flash converter with error correction, IEEE Journal of Solid State Circuits, vol. SC-5,. 84 9, Feb. 990.

110 Chater Pielined Architecture. Architectural Comarison Several architectures were investigated to ascertain their suitability for imlementing a 0- bit, 00 Mss, low-ower data converter. The following sub-sections resent the results of this study, highlighting those features which ertain to selection of an aroriate architecture for this roject. This discussion is not intended as an exhaustive descrition of A/D converter techniques. For such a treatment, the reader is referred to the text by Sheingold, [3], and the review aer by Gordon, []... Flash Converters Traditionally, high seed A/D converters have relied uon the arallel or flash architecture (Fig..) wherein the analog inut signal is simultaneously comared to every threshold voltage of the ADC by a bank of comarator circuits [5], [4]. The threshold levels are usually generated by resistively dividing one or more references into a series of equally-saced voltages which are alied to one inut of each comarator. The collection of digital oututs from this comarator bank is called a thermometer code because every comarator outut below some oint along the array is a logic (corresonding to the mercury-filled ortion of a thermometer) while all comarator oututs above this osition are logic 0 (corresonding to the emty ortion of a thermometer).

111 80 Chater Pielined Architecture +Vref Vin Encoding N-bit Digital Outut Logic -Vref N - Comarators Thermometer Code Figure.. Flash or arallel A/D converter toology. The thermometer code is easily encoded into a binary outut word with an array of simle logic gates and a read-only-memory (ROM). Although concetually simle, and caable of very highseed oeration, the flash architecture suffers from several significant deficiencies described next. In arallel ADCs, one comarator is required for each threshold of the converter. Thus, the total number of comarators required is N, where N is the resolution of the ADC. Because this quantity grows exonentially with resolution, the required number of comarators is quite large, even for medium resolution comonents such as that considered here. All of the drawbacks of flash A/D converters stem from this exonential deendence of comarator count on resolution. Thus, increased ADC resolution leads to dramatic growth in the required number of comarators which in turn causes the following detrimental effects:

112 . Architectural Comarison 8 Large die size which imlies high cost Large device count leading to low yield Comlicated clock and signal distribution with significant caacitive loading (both device and arasitic) Large inut caacitance requiring high ower dissiation in the T/H driving the A/D converter and degrading dynamic linearity High ower suly noise due to large digital switching current Significant errors in threshold voltages caused by comarator inut bias current flowing through the resistive reference ladder Although the flash toology is very effective for lower resolution converters [5], [5], [7], [6], [9], [0], [3], [], [3], and has been used widely to imlement 8-bit ADCs [7], [5], [6], [7], [8], [9], [4], [0], [], [], [3], [4], the above combination of factors make imlementation of flash converters above 8-bits very difficult, esecially if low ower dissiation is required. Therefore, the fully arallel architecture was rejected for this roject... Feedback or Multi-ass Converters The feedback, or multi-ass, A/D converter architecture reduces comlexity comared to the flash arrangement by utilizing comarators multile times during each quantization [5], [6], [7], [8], [9], [30]. In this architecture (Fig..), the full N-bit digitization rocess is divided into a series of lower resolution, m-bit quantizations. Each of these stes begins by amlifying the incoming signal aroriately, followed by a coarse m-bit quantization. The digital result from this oeration is alied to a secial accumulator called a Successive Aroximation Register (SAR), the outut of which drives an N-bit D/A converter. The analog outut from the DAC subtracts from the inut signal to form a residue signal which is ready for the next ass through the feedback loo. The N-bit resolution obtainable with this arrangement is governed by N m where m is the resolution of the coarse quantizer used, and is the number of asses around the loo required to roduce each N-bit outut code. The gain of the amlifier receding the m-bit quantizer must be increased at each successive ass around the feedback loo to ensure that the coarse quantizer is driven with the roer amlitude. The gain required to meet this condition is

113 8 Chater Pielined Architecture Inut Signal Residue Signal m(-) A V m-bit Quantizer m - Switchable Gain Stage Reconstructed Relica N-bit DAC N Successive Aroximation Register (SAR) N-bit Digital Outut Figure.. Feedback or multi-ass A/D converter toology. A V m ( ) (.) where m is the resolution of the coarse quantizer and is the number of the ass through the loo. For examle, on the 3rd ass through a loo with a 4-bit quantizer, the amlifier gain should be A V 4( 3 ) 56. Similarly, the digital words emanating from the coarse quantizer are multilied by the same factor inside the SAR (this weighting alied to incoming words distinguishes the SAR from a simle accumulator). When the coarse quantizer resolution, m, is unity, the quantizer itself reduces to a comarator and the amlifier can therefore, be eliminated. This simlified feedback converter (Fig..3) is called a successive aroximation A/D converter and reresents the lower bound on feedback ADC comlexity for a given resolution [3]. Conversely, when the coarse quantizer resolution, m, equals the full ADC resolution, N, the SAR and reconstruction DAC become unnecessary, and the feedback architecture reduces to a flash imlementation. Therefore, the feedback A/D converter architecture is a canonical structure, equivalent to a flash converter when m N and ; and equivalent to a successive aroximation converter when m and N. Clearly, intermediate values between these extremes reresent different trade-offs between comlexity and seed of oeration.

114 . Architectural Comarison 83 Vin N-bit DAC N-bit Digital Outut Successive Aroximation Register (SAR) Figure.3. Successive aroximation A/D converter toology. The feedback A/D converter architecture can offer significant hardware savings comared to a flash imlementation because the coarse quantizer resolution, m, can be much smaller than the converter resolution, N. However, the feedback imlementation suffers from several drawbacks reducing its suitability for the resent alication including the following: Requires N m asses to generate full N-bit outut word, thus limiting maximum throughut rate Requires N-bit accurate DAC Requires switchable gain amlifier which can be very difficult to realize in ractice Largely because of the limitation on maximum throughut rate, the feedback architecture was rejected for this roject...3 Feedforward Converters [3] [33] [34] [35] [36] [37] [38] [39] [40] [4] [0] [43] [44] [45] [46] [47] [8] [3] [9] [5] [5] [53] [54] [55] [] By emloying a cascade of coarse quantizer stages, the feedforward ADC toology (Fig..4) mitigates the throughut limitations which constrain feedback converters. Each stage

115 84 Chater Pielined Architecture Vin Stage Stage i Stage m i -bit m i -bit ADC DAC + _ A m i V m i bits of N-bit digital outut Figure.4. Feedforward A/D converter toology. comrising the feedforward A/D erforms the same oerations found in the feedback architecture, namely: coarse quantization, conversion back to analog format via D/A conversion, subtraction from the inut signal to form a residue, and amlification. Rather than alying these oerations times in succession as in the feedback toology, stages are cascaded to roduce the same effect. The digital data from each of the quantization stages must be suitably weighted before the words are summed to form the N-bit digital outut. (This mechanism is akin to the weighting alied by the SAR in the feedback arrangement.) Several advantages accrue from this cascade arrangement. The architecture is inherently faster than the feedback toology, no switchable gain amlifier is required, and digital error correction is ossible to make accuracy virtually indeendent of threshold errors within the constituent coarse quantizers. However, two chief disadvantages comromise the suitability of this scheme for high-seed oeration. First, since the feedforward converter utilizes stages similar in comlexity to the entire feedback ADC, its comlexity is also aroximately times the comlexity of the feedback case. Second, since each signal must rile through a cascade of substages, the net throughut is only marginally greater than in the feedback architecture. The ielined

116 . Architectural Comarison 85 A/D toology, described next, circumvents this settling roblem...4 Pielined Feedforward Converters The ielined feedforward A/D converter architecture (Fig..5) alleviates the throughut Vin Stage Stage i Stage T/H + _ A m i V m i -bit m i -bit ADC DAC m i bits of N-bit digital outut Figure.5. Pielined A/D converter toology. limitations associated with the un-ielined feedforward case by lacing a T/H at the inut of each of the stages comrising the converter. In this way, while stage is rocessing an inut samle, stage rocesses the receding samle, stage 3 rocesses the samle before that, and so on; such that all stages rocess one samle er clock cycle. Although this oeration roduces a delay or latency of sub-conversions before roducing a valid outut code, the throughut of the system is equal to that of each rocessing cell and can be significantly higher than the corresonding throughut of any of the converters discussed reviously. The ielined feedforward architecture combines the advantages of high throughut demonstrated by flash converters along with low comlexity, ower dissiation and inut caacitance characteristic of feedforward converters. The sole disadvantage associated with the ielined aroach is the requirement for T/H circuits which can be very difficult to imlement monolithically. Since analog switches (fundamental to T/H

117 86 Chater Pielined Architecture oeration) are difficult to imlement using biolar comonents (as discussed in chater 3) most ielined A/D converters have utilized CMOS semiconductor rocesses [57], [58], [], [60], [6], [6], [63], [64], [65]. However, the benefits of the ielined architecture, high-throughut combined with low comlexity, rovide comelling motivation to utilize this toology. If monolithic T/H circuits with suitable erformance can be develoed, the ielined A/D toology rovides the technique for extending high-throughut, high-resolution conversion beyond those limits currently attainable...5 Folding Converters A folding A/D converter (Fig..6) oerates in a similar manner to a feedforward ADC by Vout Analog Folding Block Fine Quantizer Vin cycle cycle cycle 3 cycle F- cycle F Vin (N-log F)-bit Flash ADC N ( / F Comarators) Encoding N-bit Digital Outut Residue Signal Logic (log F)-bit ADC Coarse Quantizer Figure.6. Folding A/D converter toology. coarsely quantizing the incoming signal and generating a residue signal for further quantization by a lower resolution succeeding stage. However, in a folding converter, the residue signal is formed by a secial analog circuit (the Analog Folding Block highlighted in figure.6) which oerates simultaneously with the coarse quantizer [66], [45], [67], [68], [69], [4], [7], [7], [73], [], [75], [5]. This arrangement obviates the need for a T/H between the coarse and fine quantizer by forming the residue signal without going through an A/D-D/A combination with its concomitant clock delay. The folding converter deicted in figure.6 corresonds to a -stage feedforward imlementation with a log F-bit coarse quantizer and an ( N log F) -bit fine quantizer, where

118 . Architectural Comarison 87 F is the number of eriods or folds in the transfer function of the analog folding block. This analog cell, details of which are described in chater 6, erforms the function of the DAC and the subtraction element from the feedforward architecture described reviously, but does so in an unclocked manner enabling simultaneous oeration of the coarse and fine quantizers. Since the folding A/D architecture offers low comlexity along with otentially high-seed oeration, this toology remains as a viable candidate for the 0-bit, 00 Mss converter designed here...6 Algorithmic (Cyclic) Converters [3] [38] [77] [78] [79] [80] [76] [6] [6] [8] [53] [8] A canonical ADC structure similar in form to the successive aroximation toology is the algorithmic A/D converter (Fig..7) which is sometimes referred to as a cyclic converter [76], [38]. Vin S/H Comarator + - Serial Outut Bit-stream Vref/ Amlifier X + - Vref/ Figure.7. Algorithmic A/D converter toology. In this arrangement, conversion begins by comaring the inut signal to a mid-scale value. If the inut exceeds this mid-scale reference, the reference is subtracted from the inut, and the result is amlified by in rearation for further rocessing. This rocedure is erformed once for each bit of resolution required in the A/D conversion with the comarator outut on the -th ass reresenting the -th MSB of the resulting codeword. An inut multilexor and T/H are necessary to coordinate signal flow and timing within the converter. Although extremely simle and otentially very accurate, the cyclic toology is not suitable for high-seed oeration because of the

119 88 Chater Pielined Architecture multile comarisons necessary during each conversion. As in the transformation from the feedback to the feedforward architecture, several algorithmic structures can be laced in cascade to form a converter with higher comlexity but accomanied by an attendant increase in maximum throughut rate. Such a toology has been termed a bit-serial A/D converter (Fig..8) but is actually a secial case of the ielined Vin Stage Stage m Stage S/H + - X Vref/ -Bit Outut Vref/ Figure.8. Bit serial A/D converter toology. feedforward architecture constructed from -bit stages. This conversion technique is very attractive because it is simle and can be easily extended to higher resolutions by adding more identical stages. However, since each stage requires a T/H circuit, the bit-serial aroach has been largely limited to CMOS imlementations [58], []...7 Architecture Selection Table. includes a summary comarison among the architectures described above. Based on the relative advantages of these cometing aroaches, the toology for a 0-bit, 00 Mss lowower A/D was selected. A flash architecture was rejected because its ower dissiation for a 0- bit imlementation would exceed the 750 mw goal unless extremely low bias levels are used. Such

120 . Architectural Comarison 89 Quantizer Architecture Flash or Parallel Feedback or Multi-ass Feedforward Pielined Feedforward Folding Algorithmic or Cyclic Advantages Very fast Basically linear & monotonic No D/A required Low transistor count Single inut T/H required Error correction ossible Moderate transistor count Error correction ossible Low inut caacitance Very high seed Error correction ossible Low inut caacitance High seed Low transistor count Folding circuit relaces coarse quantizer and D/A Low inut caacitance Very low transistor count Low ower Disadvantages Very high transistor count Very high ower dissiation Resolution limited by inut range and transistor mismatch High inut caacitance Feedback reduces maximum samle rate Subtraction element required Switchable gain amlifier required D/A required Moderate samle rate Multile T/H circuits required Resolution limited Folding circuit cannot realize ideal transfer function T/H required for high inut frequencies Concetually comlex Difficult to layout Low seed Table.. Comarison among several A/D converter architectures. low bias levels comromise comarator settling time, thus reducing maximum achievable samlerate. In contrast, the feedback architecture, although caable of low ower oeration, was deemed too slow to meet the 00 MHz samle-rate requirement. Likewise, because of its sequential nature of oeration, the algorithmic toology was rejected for inadequate seed. Although caable of somewhat faster oeration than the feedback or algorithmic architectures, the feedforward aroach was deemed too slow for the demanding 00 Mss oerating seed required. The remaining candidate converter tyes include the ielined feedforward structure and the folding imlementation. Both of these conversion methods show romise, however, as will be

121 90 Chater Pielined Architecture demonstrated in the next section, the folding A/D converter in incaable of attaining 0-bit resolution without trimming. Therefore, a hybrid aroach using a ielined feedforward architecture with a constituent fine quantizer base on a folding toology was selected. The details of this architecture and rationale for its selection are discussed next.. 0 Bit High Seed Converter Toology A folding A/D converter romises low-ower dissiation and is caable of high oerating seed; however, mismatches in transistor V BE within the analog folding block can lead to unaccetable threshold errors caused by erturbations in the resultant residue waveform from the ideal. These level errors manifest themselves as degradations in achievable SNR (see section.3.3 and equation.09) or alternatively as decreases in circuit yield given a maximum INL secification. If the cycle transitions of a folding characteristic such as that deicted in figure.6 are erturbed by transistor V BE mismatches, the resultant ADC thresholds will be similarly modified. Equation.09 redicts that when calculating the effect of such errors on A/D signal-tonoise ratio, the variance of the threshold errors adds to the quantization noise ower. Comaring the exected SNR of a folding A/D converter including the effects of V BE mismatches with the maximum achievable SNR gives the exected SNR degradation from ideal (Fig..9). SNR degradation is lotted in figure.9 for combinations of two arameters, F and V Ta. F is the number of folds in the analog residue waveform generated by the analog folding block, and V Ta is the voltage sacing between adjacent cycle transitions in the folding characteristic. For all combinations of these two arameters and assuming σ VBE, the standard deviation of V BE mismatch, is aroximately mv ; SNR degradation is db or less for ADC resolutions less than or equal to 8 bits. However, SNR degradation becomes much more significant in the higher resolution converters, N 9 and N 0. In the 9-bit case, SNR degradation is robably accetable for some combinations of F and V Ta ; however in the 0-bit case, SNR degradation is unaccetably large for all combinations of these arameters. Alternatively, the detrimental effect of transistor V BE mismatch on folding A/D erformance can be measured by circuit yield. Figure.0 deicts ADC yield normalized to maximum allowable INL for the circuit arameters F and VTa, and for several values of converter resolution, N. For tyical values of (about / mv) and maximum INL (about / LSB), circuit yield is below 50% in all cases excet F 6, σ VBE

122 . 0 Bit High Seed Converter Toology 9 0 SNR Degradation (db) N9 N0 SNR Degradation (db) F8, V Ta 64mV F8, V Ta 8mV F6, V Ta 64mV F6, V Ta 8mV N7 N σ Vbe (mv) σ Vbe (mv) Figure.9. SNR degradation in folding A/D converters due to mismatches. Quantizer resolution indicated on lot. V be V be V Ta 8mV. Note by contrast, that for N 7 and N 8, yield is virtually 00% for all combinations of F and V Ta. Intuitively, this condition arises because the converter full-scale range is determined by V FSR F V Ta (.) (see figure.6). Therefore, the threshold sacing, Q, is given by Q V FSR F V Ta N N (.3) σ VBE This voltage must be large comared with to revent significant threshold errors imlying that V FSR should be increased to mitigate the effects of transistor mismatch. However, F cannot be

123 9 Chater Pielined Architecture Yield (%) Yield (%) N0 N9 N9 N8 N8 N7 F8 VTa64mV N7 F6 VTa64mV N σ Vbe /INL (mv/lsb) F6 VTa8mV N0 N0 N9 N9 N8 F8 VTa8mV N8 N σ Vbe /INL (mv/lsb) Figure.0. Yield in folding A/D converters for 8 (lower) or 6 (uer) folds er stage. V Ta is 64 mv (left) or 8 mv (right). The normalization of the indeendent variable to INL refers to maximum secified INL above which oint a converter fails the erformance test, e.g. if maximum secified INL is / LSB, and is / mv; then the aroriate value on the indeendent σ VBE axis for determining yield is. made arbitrarily large without unduly loading the T/H circuit which must drive the A/D converter. Likewise, V Ta is constrained to a small range of values because it must be a small multile of V T, the thermal voltage, for roer oeration of the folding circuits envisioned. (These two oints will be made more clear when folding circuits are describe in detail in chater 6). Therefore, V FSR is limited to a maximum value of aroximately V FSR F V Ta 6 8mV.048V (.4) The quantizer ste-size, Q, then becomes mv: not large enough relative to to make σ VBE

124 . 0 Bit High Seed Converter Toology 93 transistor mismatch effects negligible. The receding discussion along with the data in figures.9 and.0 indicate that without trimming, a 0-bit folding A/D converter will exhibit very low yield couled with degraded SNR because V BE mismatches significantly erturb threshold ositions from their ideal locations. Therefore, the second accetable toology, the ielined feedforward aroach, was selected as the architecture for this roject. However, since the folding A/D imlementation offers significant erformance advantages over other aroaches for medium-resolution alications, a folding converter was selected to realize the fine quantizer. The resulting ADC architecture (Fig..) Vin S/H First Stage S/H + - Second Stage X (n-) n-bit Folding & Interolating Fine Quantizer n-bit Flash Coarse Quantizer n-bit DAC Delay Register Error Correction, Encoding, and Outut Registers Combining Logic N-bit Digital Outut Required linearity: N bit n bit n bit Figure.. Tyical stage ielined A/D converter. comrises a -stage ielined feedforward converter with an inut T/H circuit and an interstage T/H circuit. The coarse quantizer drives a reconstruction DAC whose outut is subtracted from the held inut to form a residue signal. This residue is amlified aroriately and then digitized by a folding fine quantizer. The linearity required from the comonents of this circuit are indicated in figure.. Both T/H circuits must exhibit linearity consistent with 0-bit oeration. Similarly, the DAC and subtracter must be linear to this level. However, owing to the benefits of digital error correction, the coarse quantizer needs linearity only consistent with its resolution, n, not the full 0-bit resolution of the converter [58], []. The amlifier and fine quantizer must exhibit linearity consistent with n bits, as exected. As will be discussed in chater 3, imlementing T/H circuits in biolar technology roves

125 94 Chater Pielined Architecture to be very difficult and requires significant ower dissiation, articularly when wide dynamic range is necessary. Therefore, a modification to the tyical ielined architecture which reduces the required linearity of the second (or interstage) T/H was devised. This modification entails moving the interstage T/H to a location after the subtraction element (Fig..) where its linearity need only Vin S/H First Stage + - Second Stage S/H X (n-) n-bit Folding & Interolating Fine Quantizer n-bit Flash Coarse Quantizer n-bit DAC Delay Register Combining Logic Error Correction, Encoding, and Outut Registers N-bit Digital Outut Required linearity: N bit n bit n bit Figure.. Alternative imlementation of -stage ielined A/D converter. match that of the n-bit quantizer which it drives. The corresonding timing changes necessary to imlement this modification are next described... Timing Scheme for Pielined Converter In a conventional ielined feedforward ADC (Fig..3), the coarse quantizer and the interstage T/H share inuts. These two elements also oerate in-hase, meaning that during one clock hase both elements track their mutual inut, and during the other clock hase the T/H freezes its outut while the coarse quantizer switches its outut to a new digital code. The timing signals necessary to roduce this behavior are included in figure.3, and the resultant outut signals from each of the converter blocks are shown in figure.4. From these diagrams the throughut delay is seen to be.5 clock eriods. In the modified ielined architecture, the interstage T/H is relocated after the subtracter circuit; therefore, the system timing is altered corresondingly (Fig..5). In this arrangement, the

126 . 0 Bit High Seed Converter Toology 95 Φ Φ Φ Φ Vin T/H ADC T/H DAC ADC DELAY (Master) Error Correct & Latch Out Digital Outut Φ Φ T/H Φ Φ Φ Φ Φ Φ T H T H T H ADC R T R T R T T/H DELAY Master ADC H T H T H T T R T R T T R T R T R R Outut R T R T R T 5ns 5ns T Track H Hold RRegenerate Figure.3. Conventional timing scheme for ielined A/D converter. coarse quantizer and interstage T/H do not share a common inut, nor do they oerate in-hase. Rather, the inut T/H and the coarse quantizer oerate in-hase so that both elements oerate in track mode simultaneously. Therefore, the coarse quantizer s digital outut word tracks the dynamic inut signal (Fig..6), and the DAC analog outut forms a real-time (albeit coarse) relica of the inut. The dynamically changing DAC outut subtracts from the active outut of the first T/H to form the residue signal which drives the interstage T/H. The throughut delay in this arrangement is.5 clock eriods as in the conventional case. Since the inut T/H and the coarse quantizer oerate in track mode simultaneously, the coarse quantizer must digitize a dynamic signal rather than a static one. The coarse quantizer is therefore suscetible to the finite aerture time effects described in section.3.3. Two factors mitigate these effects which would normally degrade coarse quantizer linearity severely. First, the resolution of the coarse quantizer is quite low (only 4 bits as will be seen shortly) so that large aerture-time induced errors are tolerable. And second, the clock to the coarse quantizer is retarded by ns to allow the T/H outut to settle before quantization begins.

127 96 Chater Pielined Architecture T/H Outut n- n n+ n+ ADC Outut T/H Outut DAC Outut n- n n+ n- n n+ n- n n+ ADC Outut Delay Outut Latch Outut n- n- n n+ n- n- n n+ n- n- n Figure.4. Outut signals from converter elements in ielined A/D emloying conventional timing scheme. This rather unconventional clocking arrangement is motivated by the desire to relace the interstage T/H requiring 0-bit linearity with a simler and lower ower T/H requiring only m-bit linearity. The new scheme does not degrade converter linearity because the coarse quantizer is very low resolution, only 4 bits, and because the coarse quantizer clock signal is delayed slightly to allow adequate settling before quantization. The low resolution coarse quantizer is made ossible because the fine quantizer which uses the folding architecture is articularly efficient, realizing 7 bits of resolution with roughly the same number of transistors and ower dissiation as the 4-bit coarse quantizer..3 Pielined Feedforward Partitioning In a ielined feedforward A/D imlementation without error correction, the converter resolution equals the sum of the resolutions of the individual stages. If error correction is used, the converter resolution diminishes by the amount of redundancy (in bits) used for the correction. In the resent design, one bit of error correction or overrange is used so the sum of the resolutions of the individual stages must equal. The next sub-sections describes the rationale behind the

128 .3 Pielined Feedforward Partitioning 97 Vin Φ T/H ADC DAC Φ Φ T/H ADC DELAY Master STAGE Slave Φ Error Correct & Latch Out Digital Outut Φ Φ Φ T/H ADC T/H DELAY Master ADC Outut Φ Φ Φ Φ Φ Φ T H R H T T R T R T H T H T H T T R T R T T R T R T R T R T R T T H R ns 5ns 5ns T Track H Hold RRegenerate Figure.5. Modified timing scheme for ielined A/D converter. artitioning of this total resolution between the coarse and fine quantizers. Most feedforward converters use substantially identical architectures for each constituent quantizer. Therefore, dividing the comlexity evenly between stages reduces the total comlexity of the A/D converter. Since in this roject a very efficient folding converter is used as the fine quantizer, evenly artitioning the resolution among stages does not minimize device count. Rather, a distribution with a very low resolution coarse quantizer followed by a higher resolution folding fine quantizer yields lower comlexity. Circuit yield and exected erformance also lay a role in selecting the artitioning of resolution among stages. Some selections are more sensitive to errors induced by device mismatches and are therefore less robust than other artitionings. Otimized converter artitioning minimizes device count (hence ower dissiation and die size) without degrading yield or exected erformance given device mismatches.

129 98 Chater Pielined Architecture T/H Outut n- n n+ n+ ADC Inut DAC Outut T/H Outut ADC Outut Delay Outut Latch Outut n- n n+ n+ n- n n+ n+ n- n n+ n- n- n n+ n- n- n n+ n- n- n Figure.6. Outut signals from converter elements in ielined A/D emloying modified timing scheme..3. Hardware Comlexity (Parts and Power) The number of transistors in a flash quantizer is roortional to the number of comarators required, N, where the roortionality constant equals the number of transistors necessary for each comarator (including associated circuitry such as a reamlifiers and logic gates for encoding). Likewise, the number of transistors required for a folding quantizer equals the sum of the transistors comrising the analog folding block, the coarse quantizer, and the fine quantizer (see Fig..6). The analog folding block and the coarse quantizer comlexity deend only uon F, the number of eriods in the folding characteristic, and not uon N, the quantizer resolution, whereas the fine quantizer comlexity is roortional to N F. Therefore, the total comlexity of an N-bit folding quantizer equals a constant roortional to F lus a term roortional to N F. The above results are summarized in figure.7 which lots total comlexity (as measured by transistor count) of a 0-bit -stage feedforward A/D converter consisting of a flash coarse quantizer and a folding fine quantizer and assuming one bit of overrange for error correction. This

130 .3 Pielined Feedforward Partitioning Transistor Count Bit A/D First Quantizer Second Quantizer (8 Folds) Assumes -Bit Overrange First Quantizer Resolution Figure.7. resolution. Comarison of A/D converter comlexity versus fine quantizer lot shows that ADC comlexity is minimized if the first quantizer is selected to have 4-bit resolution. This is a broad minimum, however, so 3-bit and 5-bit coarse quantizers also roduce low total converter comlexity. As will be shown in the next sub-section, the 3-bit coarse quantizer artitioning is overly sensitive to comonent mismatching roducing inadequate yield and excessive threshold errors. Therefore, only the artitionings based on 4-bit and 5-bit coarse quantizers are considered further. The A/D converter utilizing a 5-bit coarse quantizer (called the 5-6 artitioning) is deicted in figure.8 which indicates the linearity requirements of each comonent. The contending architecture based on a 4-bit coarse quantizer (the 4-7 artitioning) is deicted in figure.9. Since the 4-7 aroach exhibits lower comlexity than the 5-6 artitioning, the former should be utilized unless sensitivity to comonent mismatches roves otherwise..3.3 Performance (Yield and SNR) The 4-7 and 5-6 artitionings exhibit different sensitivities to comonent mismatches.

131 00 Chater Pielined Architecture Vin S/H First Stage + - S/H Second Stage X6 6-bit Folding & Interolating Fine Quantizer 5-bit Flash Coarse Quantizer 5-bit DAC Delay Register Combining Logic Error Correction, Encoding, and Outut Registers 0-bit Digital Outut Required linearity: 0 bit 6 bit 5 bit Figure ieline artitioning. Vin S/H First Stage + - S/H Second Stage X8 7-bit Folding & Interolating Fine Quantizer 4-bit Flash Coarse Quantizer 4-bit DAC Delay Register Combining Logic Error Correction, Encoding, and Outut Registers 0-bit Digital Outut Required linearity: 0 bit 7 bit 4 bit Figure ieline artitioning. These sensitivities can be ascertained by simulation, and an otimum artitioning can be selected based uon the results. Comonent mismatches which affect ADC erformance include DAC current source error, coarse quantizer INL, fine quantizer INL, fine quantizer gain error, and DAC gain error. The effects of each of these error sources is investigating by simulating the ADC transfer function in the resence of the secified error. The threshold erturbations due to the error source can then be quantified by secifying the resultant A/D converter SNR.

132 .3 Pielined Feedforward Partitioning 0 DAC current source matching is largely determined by resistor matching which is usually exressed by the standard deviation of resistor mismatch normalized to the mean resistance value. That is, for resistors with mean value µ R, and standard deviation σ R, the resistor mismatch is σ R µ R exressed in ercent. In a well-controlled monolithic rocess σ R µ R is usually a small fraction of %. The effect of DAC current source matching was determined via Monte Carlo analysis where, for a large number of test cases, a random distribution is selected for the DAC current source values. The resultant ADC transfer function is calculated, and SNR based uon threshold errors is determined. The distribution of SNR values associated with the ensemble is then secified by its ensemble average or yield, the ercentage of test cases where SNR is above some secified value (in this case 59 db). The deendence of A/D converter SNR on DAC current source mismatch (Fig..0) is stronger for the 4-7 artitioning than for the 5-6 artitioning. However, the anticiated resistor mismatch in Tektronix SHPi rocess is aroximately 0.%. At this value of σ R µ R, the difference in exected SNR between the two cases is negligible. Coarse quantizer INL is largely due to transistor mismatches and is secified by its rms value in LSBs. The effect of this error source on converter SNR was investigated with the same method used for DAC current source mismatch henomenon. Owing to the digital error correction used in the roosed toologies, coarse quantizer INL less than / LSB in magnitude does not affect A/D converter SNR (Fig..). Since / LSB rms INL is easily obtainable for both the 4- bit quantizer and the 5-bit quantizer cases, coarse quantizer INL will not substantially imact overall A/D converter erformance. Fine quantizer INL was investigated in identical manner to coarse quantizer INL resulting in the lots included in figure. which indicate that SNR sensitivity to fine quantizer INL is identical for the 4-7 and 5-6 artitionings. However, since a secified INL in a 6-bit fine quantizer is more readily obtained than in a 7-bit quantizer, this data indicates that the 5-6 artitioning is more robust in this regard. For the feedforward toology to oerate correctly, the inut-referred full-scale-outut from the DAC must equal the full-scale inut to the coarse quantizer. Likewise, the full-scale outut from the amlifier block must equal the full-scale inut to the fine quantizer. Mismatches in these settings introduce systematic errors into the ADC transfer function.

133 0 Chater Pielined Architecture ADC Yield at 59 db (%) n4 n7 n5 n n5 n6 Mean SNR (db) n4 n DAC Current Source Matching (%) Figure.0. 0 bit A/D converter yield (uer) and mean SNR (lower) versus segmented DAC current source mismatch for both 4-7 and 5-6 artitioning. If the DAC full-scale-outut is set incorrectly; that is, if its gain is erroneous, threshold errors result which degrade SNR. Such threshold errors are a deterministic function of the DAC gain error and can be calculated via simulation. A/D converter SNR, calculated in this manner, is lotted for a range of gain errors in figure.3. This figure indicates that SNR degradation for the 4-7 artitioning is a stronger function of DAC gain error than for the 5-6 artitioning. However, for DAC gain errors of aroximately %, the degradation is less than db and the discreancy between the 4-7 artitioning and the 5-6 is even less.

134 .3 Pielined Feedforward Partitioning ADC Yield at 59 db (%) n4 n7 n5 n Mean SNR (db) n4 n7 n5 n Coarse Quantizer INL (Bits) Figure.. 0 bit A/D converter yield (uer) and mean SNR (lower) versus coarse quantizer INL for both 4-7 and 5-6 artitioning. Fine quantizer gain errors are treated in a manner analogous to DAC gain errors. Simulations of this deterministic henomenon indicate that the sensitivity of the 4-7 toology to this effect is greater than the 5-6 case (Fig..4). Again, however, the difference in sensitivities is small for the range of mismatches anticiated which is aroximately %. To assess the cumulative effect of comonent mismatches on SNR, Monte Carlo simulations varying all of the above error sources were erformed. The resulting histograms of SNR

135 04 Chater Pielined Architecture ADC Yield at 59 db (%) n4 n7 n5 n Mean SNR (db) n5 n6 57 n4 n Fine Quantizer INL (Bits) Figure.. 0 bit A/D converter yield (uer) and mean SNR (lower) versus fine quantizer INL for both 4-7 and 5-6 artitioning. give insight into the exected oeration of the 4-7 and 5-6 artitioned A/D converters. These histograms (Fig..5) indicate that for the comonent mismatches anticiated, the exected SNR for the 5-6 artitioning will be clearly suerior to that for the 4-7 artitioning. However, the 4-7 artitioned samles indicate adequate erformance with nearly all samles exhibiting SNR equal to 59 db or greater.

136 .3 Pielined Feedforward Partitioning n5 n6 SNR (db) n4 n7 0 n4 n7 ADC Gain Error (%) n5 n DAC Gain Error (%) Figure.3. 0 bit A/D converter SNR (uer) and gain error (lower) versus DAC gain error for both 4-7 and 5-6 artitioning. Because the 4-7 artitioning offers a significant comlexity advantage over the 5-6 artitioning and delivers adequate insensitivity to exected comonent mismatches, this toology was selected over the more robust 5-6 aroach. The final 0-bit A/D converter architecture (Fig..6) consists of a ielined feedforward toology with a 4-bit coarse quantizer and a 7-bit folding fine quantizer. The interstage T/H is located after the subtracter element so that it needs to exhibit linearity consistent with 7-bit quantization. The inut T/H and the coarse quantizer oerate in track

137 06 Chater Pielined Architecture n5 n6 SNR (db) n4 n ADC Gain Error (%) n4 n7 n5 n Fine Quantizer Gain Error (%) Figure.4. 0 bit A/D converter SNR (uer) and gain error (lower) versus fine quantizer gain error for both 4-7 and 5-6 artitioning. mode simultaneously to enable this lacement of the interstage T/H. Consequently, the coarse quantizer samle clock is retarded by ns relative to the other A/D clocks to allow for adequate settling from the inut T/H before coarse quantization. The one bit of overrange is used for error correction so that coarse quantizer threshold errors less than LSB will not affect the A/D converter linearity.

138 .3 Pielined Feedforward Partitioning 07 Number of Occurrences n4, n7 Gain Error 0.5% Offsets mv INL /3 LSB INL /4 LSB DAC Error 0.% Number of Occurrences n5, n6 Gain Error 0.5% Offsets mv INL /6 LSB INL /8 LSB DAC Error 0.% SNR (db) Figure.5. Histogram of A/D converter SNR for 4-7 (uer) and 5-6 (lower) artitionings. References [] D. H. Sheingold, ed., Analog Digital Conversion Handbook. Prentice Hall, third ed., 986. The Engineering Staff of Analog Devices.

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143 Chater Pielined Architecture error-averaged ielined A/D converter, IEEE Journal of Solid State Circuits, vol. SC-3, , Dec [63] S. Sutarja and P. R. Gray, A 50ks/s 3b ielined A/D converter, in International Solid State Circuits Conference,. 8 9, IEEE, Feb [64] S. Sutarja and P. R. Gray, A ielined 3-bit, 50-ks/s, 5-V analog-to-digital converter, IEEE Journal of Solid State Circuits, vol. SC-3, , Dec [65] M. Ishikawa and T. Tsukahara, An 8-bit 50-MHz CMOS subranging A/D converter with ielined wide-band S/H, IEEE Journal of Solid State Circuits, vol. SC-4, , Dec [66] A. Arbel and R. Kurz, Fast ADC, IEEE Transactions on Nuclear Science, vol. NS-, , Feb [67] J. V. Woods and R. N. Zobel, Fast synthesized cyclic-arallel analogue-digital convertor, IEE Proceedings, vol. 7,. 45 5, Ar [68] W. Wolz, Videoumsetzer mit mehrfachfaltung, Elektronik, , July 983. [69] R. E. J. van de Grift and R. J. van de Plassche, A monolithic 8-bit video A/D converter, IEEE Journal of Solid State Circuits, vol. SC-9, , June 984. [70] R. E. J. van de Grift, I. W. J. M. Rutten, and M. van der Veen, An 8 bit video ADC incororating folding and interolation techniques, IEEE Journal of Solid State Circuits, vol. SC-, , Dec [7] R. E. J. van de Grift and M. van der Veen, An 8b 50MHz video ADC with folding and interolation techniques, in International Solid State Circuits Conference, , IEEE, Feb [7] D. Daniel, U. Langmann, and B. G. Bosch, A silicon biolar 4-bit -Gsamle/s full Nyquist A/D converter, IEEE Journal of Solid State Circuits, vol. SC-3, , June 988. [73] R. J. van de Plassche and P. Baltus, An 8b 00-MHz folding ADC, in International Solid State Circuits Conference,. 3, IEEE, Feb [74] R. J. van de Plassche and P. Baltus, An 8-bit 00-MHz full Nyquist analog-to-digital converter, IEEE Journal of Solid State Circuits, vol. SC-3, , Dec [75] J. van Valburg and R. van de Plassche, An 8b 650MHz folding ADC, in International Solid State Circuits Conference,. 30 3, IEEE, Feb. 99. [76] B. D. Smith, Jr., An unusual electronic analog-digital conversion method, IRE Transactions on Instrumentation, vol. PGI-5, , 956. [77] P. W. Li, M. Chin, P. R. Gray, and R. Castello, A ratio-indeendent algorithmic A/D conversion technique, in International Solid State Circuits Conference,. 6 63, IEEE, Feb [78] P. W. Li, M. J. Chin, P. R. Gray, and R. Castello, A ratio-indeendent algorithmic analogto-digital conversion technique, IEEE Journal of Solid State Circuits, vol. SC-9, , Dec [79] H. Onodera, T. Tateishi, and K. Tamaru, A cyclic A/D converter that does not require ratio-matched comonents, IEEE Journal of Solid State Circuits, vol. SC-3,. 5 58,

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145 4 Chater Pielined Architecture

146 Chater 3 Samle-and-Hold Design The function and secification of Samle-and-Hold (S/H) circuits was discussed in section.3.. The hardware imlementations of such devices which are also referred to as Track-and-Hold (T/H) circuits or Samle-and-Hold Amlifiers (SHAs) will now be described. A T/H circuit comrises five elements; an inut reamlifier, a samling switch, a storage element which is assumed to be a caacitor, an outut amlifier or ostamlifier, and a clock buffer (Fig. 3.a). The reamlifier resents a high or well-controlled imedance to the signal source while maintaining a low outut imedance for raidly charging and discharging the storage or hold caacitor. Additionally, the reamlifier can rovide gain to maximize the dynamic range of the stored signal. The samling switch, when closed, enables the reamlifier to drive the stored signal on the hold caacitor; and, when oen, disconnects the hold caacitor from the reamlifier reserving a constant stored signal equal to the value at the instant the switch was oened. The ostamlifier resents a high imedance to the hold caacitor to minimize leakage of the stored charge and drives succeeding circuitry with a (ossibly amlified) relica of the held signal. Frequently, the ostamlifier exhibits low outut imedance thus ensuring adequate frequency resonse and distortion characteristics when driving caacitive loads. The clock buffer facilitates switch oeration by roviding suitable logic signals in resonse to the incoming clock. Such buffering. T/H circuits which emloy inductors as storage elements are ossible in theory but for a variety of reasons have roven imractical. Suerconducting coils have been investigated for this urose.

147 6 Chater 3 Samle-and-Hold Design Amlitude Vout Acquisition time Track time Settling time A/D Conversion time Inut Buffer Samling Switch Outut Buffer Vin Vin Track/Hold Command Clock Buffer Hold Caacitor Vout Hold Samle Hold Track/Hold Command time Hold Track Hold Track time (a) (b) Figure 3.. Track-and-hold building-blocks (a) and oeration (b). requires adequate gain and frequency resonse without unduly exacerbating clock timing jitter. This oeration is deicted grahically in figure 3.b. Each of the elements described above can be easily imlemented in a standard biolar integrated circuit technology (such as Tektronix SHPi) with the excetion of the samling switch. High-erformance switches are articularly difficult to realize in biolar rocesses, and the availability of native integrated circuit switches in MOS technologies rovides comelling motivation to use such rocesses when analog switching is necessary. The inferior caabilities of MOS devices in high-seed, high-accuracy alications; however, limits the utility of this otion. Comlementary rocesses combining both biolar and MOS devices (BiCMOS) rovide an adequate solution, but these rocesses are currently rare and exensive. Therefore, utilization of a high-erformance biolar switch is imerative. Such a circuit will be discussed in detail next. 3. Samling Bridge Toology and Oeration The basis of almost all analog switches imlemented in biolar IC technologies is the diode samling bridge (Fig. 3.) which rovides a low imedance between inut and outut when conducting, high isolation when not conducting, and very fast switching between the conducting and non-conducting states. This architecture has been widely used in samling alications for many years owing to its simlicity and seed of oeration [6], [7], [8]. The diode-bridge switch is

148 3. Samling Bridge Toology and Oeration 7 V in D D D3 D4 C H V out Preamlifier Diode Bridge Postamlifier Figure 3.. Prototye diode bridge track-and-hold circuit with emitter follower reamlifier and ostamlifier. virtually a necessity in biolar semiconductor technologies lacking field-effect transistors (FETs) and has been oular in silicon technologies [9], [8], [0], [], [] and more recently in Gallium- Arsenide (GaAs) Heterojunction Biolar Transistor (HBT) technologies [3], [4]. The diodebridge has frequently been used even in some technologies with native FET devices [5], [6], [7], [8] because of its suerior switching roerties, but the emerging reeminence of CMOS technology has driven many workers to ursue high erformance track-and-hold circuits based uon CMOS switches [9], [0], [], [], [3], [4], [5]. Others have develoed switches in biolar technologies without diode-bridges [6], [7], [3] or have utilized FET switches in more exotic technologies such as GaAs [9], [30]. The diode-bridge switch offers seed and recision advantages over most other aroaches but suffers from some disadvantages which must be contended with to develo high-erformance T/H circuits. These drawbacks will be discussed in the next several sections. The reamlifier and ostamlifier in figure 3. are simle emitter follower buffers, but any tye of amlifier fulfilling the characteristics described in the receding introduction will suffice. Selection of amlifier toologies for these functions deends uon ractical considerations such as linearity, ower dissiation, frequency resonse, comlexity, etc. Since this section details oeration of the diode bridge itself, the re- and ostamlifiers comrising the track-and-hold in figure 3.3 are deicted as ideal elements for simlicity while the bridge drive circuitry consists of a

149 8 Chater 3 Samle-and-Hold Design I Bridge I Bridge D D Vin X D6 V CT X Vout D3 D5 D4 C H I I Hold Q Q Track I Bridge Figure 3.3. bridge current. Diode-bridge track-and-hold with differential air controlling differential transistor air and ideal current sources. The circuit oerates in the following manner. When in track mode, transistor Q conducts all of the diff-air current causing I 0 and I I Bridge. Consequently, each of the diodes D through D4 conducts I Bridge causing their small-signal imedances to be very low, I Bridge V T. The reamlifier can therefore charge or discharge the hold caacitor, C H, through the small imedance ( r d + r d ) ( r d3 + r d4 ) enabling V out to track V in. Conversely, in hold mode transistor Q conducts the diff-air current resulting in I I Bridge and I 0. In this case diodes D through D4 conduct no current thereby interosing a large (ideally infinite) small-signal imedance between the reamlifier and the hold caacitor. Diodes D5 and D6 conduct I Bridge inning the to and bottom of the bridge at V CT V D and V CT + V D resectively where V CT is some convenient bias voltage and V D is the forward diode voltage dro. In this state the outut is effectively isolated from the inut. Although fairly simle and caable of faithfully relicating analog switch oeration, this toology suffers from several drawbacks which limit erformance and which will be discussed in detail next. The nature of diode bridge oeration during track mode is quite comlicated and will be elaborated uon with reference to figure 3.4 which shows a diode bridge with ideal current drive. When the current sources in figure 3.4 are at value zero, all 4 diodes conduct no current and the

150 3. Samling Bridge Toology and Oeration 9 I Bias 0 D D Vin Vout D3 D4 I Bias 0 Figure 3.4. Diode-bridge switch. outut terminal is isolated from the inut terminal as described reviously. When the current sources are at value I Bias, circuit oeration deends uon the exonential relationshi between diode voltage and current: I D I SA e V D V T I S Ae V D V T (3.) where I S is the diode saturation current, A is the diode area and V T is the thermal voltage, kt q, which equals aroximately 6mV at room temerature. Performing KVL around the loo of diodes gives V D + V D3 V D + V D4 (3.) which through the use of equation 3. becomes V T ln I D A I S V T ln I D3 + V A 3 I T ln I D S + A I S V T ln I D4 A 4 I S (3.3) If all of the I S terms are assumed to be identical (the area arameters A through A4 can be suitably modified to account for any mismatches in saturation current) equation 3.3 can be

151 0 Chater 3 Samle-and-Hold Design simlified to I D I D3 A A 3 I D I D4 A A 4 λ (3.4) where λ is defined as the ratio of areas as shown. If all diode areas are equal mandating λ equation 3.4 becomes I D I D3 I D I D4 (3.5) Performing KVL around the uer (lower) half of the diode ring gives a constraint on V D and V D ( V D3 and V D4 ): V in V out V D V D V in V out V D3 V D4 ( ) (3.6) Using the diode I-V characteristic (Eq. 3.) in the first equation above yields V in V out V T ln I D A I S V T ln I D A I S V T ln I D I D A A V T ln I D I D (3.7) where the last simlification assumes A A. Solving for I D gives ( ) V T I D I D e V in V out (3.8). This surrisingly simle result is reresentative of all circuits in which a set of elements with exonential I-V characteristics form a closed voltage loo. The above relationshi arises because the elements transconductances are linear functions of their branch currents. Such toologies have therefore been dubbed translinear circuits [] and have seen widesread use in analog multiliers, dividers, and other function generators [], [3], [4], [5].

152 3. Samling Bridge Toology and Oeration An additional constraint is found by erforming KCL at the to of the diode bridge roducing I D + I D I Bias (3.9) Equations 3.8 and 3.9 can be solved for I D and I D. I D I Bias ( e V in V out ) V T e V in V out I D I Bias + ( ) V T ( e V in V out ) V T + (3.0) The differential current I D I D can be easily found as well I D ( ) V T e V in V out I D I Bias ( e V in V out ) V T + V in V out I Bias tanh V T (3.) According to equation 3.6, V D4 and V D3 are related to V in V out in the same manner as V D and V D resectively; therefore, I D3, I D4, and I D3 I D4 can be found by analogy to equations 3.0 and 3.. I D3 ( e V in V out ) V T I D3 I Bias ( e V in V out ) V T + I D4 I Bias ( e V in V out ) V T + V in V out I D4 I Bias tanh V T (3.) The following two equivalencies stemming from equation 3.0 and 3. should be noted: I D I D I D4 I D3 (3.3) and can be used to determine I out in terms of I in (where I in and I out are defined to flow into the

153 Chater 3 Samle-and-Hold Design diode bridge at the inut and outut nodes resectively), I in I D3 I D I D I D4 I out (3.4) Alternatively, equation 3. and 3.3 can be used to solve for I in I in I D3 I D I D I D V in V out I Bias tanh V T (3.5) Equation 3.5 redicts that I in is a function of V in V out which imlies that the diode bridge behaves identically to a non-linear resistor laced between the inut and outut orts. The incremental value of this conductance which deends uon the alied voltage can be found by differentiating equation 3.5 with resect to V in V out. g Bridge V d I d( I( V) ) Bias tanh ( ) V T dv dv I Bias sech V ( ) V T V T (3.6) I Bias sech ( V ) V T V T or alternatively r Bridge V T I Bias cosh ( V ) V T (3.7) Comaring this exression to that generated via small-signal analysis is instructive. In the smallsignal equivalent circuit of the diode bridge in track mode (Fig. 3.5b) each diode is relaced by r d, the diode small-signal resistance, which is equal to V T I D. Since each diode is nominally biased at I Bias, r d becomes V T ( I Bias ). The combination of the 4 resistors in figure 3.5b is equivalent to one resistor of value r d sanning from inut to outut also of value r d. The large-

154 3. Samling Bridge Toology and Oeration 3 r d r d V V V V r eq r d r d V V V T r eq r d cosh r d I Bias V T (a) (b) Figure 3.5. Diode-bridge models in track mode. (a) Large-signal model. (b) Small-signal model. signal model shown in figure 3.5a gives identical results; that is, a resistance of value V T ( I Bias ) when the voltage difference between inut and outut is 0 (since cosh ( 0) ). The large-signal non-linear model more accurately redicts bridge behavior for V in V out 0 with an attendant increase in comlexity. Intuitively, the bridge oerates by steering the bridge bias current under control of the alied voltage. When V out equals V in the bridge is balanced with equal current I Bias flowing in all diodes and I in I out 0 (Fig. 3.6a). If V in > V out, diodes D and D3 exerience Vin D D3 D D4 Vout Vin D D3 D D4 Vout Vin D D3 D D4 Vout (a) (b) (c) Figure 3.6. Diode bridge oeration in track mode. (a) t. (b) V in > V out. (c) V in < V out. V in V out

155 4 Chater 3 Samle-and-Hold Design larger voltage dros and consequently conduct more current than D and D4 resulting in current being drawn from the inut node and delivered to the outut (Fig. 3.6b). Conversely, if V in < V out, diodes D and D4 conduct more strongly than D and D3 with current sunk by the inut and sourced by the outut (Fig. 3.6c). In each of these cases I D I D4 and I D I D3. Also, when one ( current exceeds another, it does so by the factor e V in V out ) V T. The diode-bridge as described above forms the basis of a ractical switch which is suorted by a reamlifier and ostamlifier as well as circuitry to rovide the bridge with the aroriate ulsed bias current. A block diagram of such a configuration is shown in figure Bridge Driver Bridge Driver (a) Figure 3.7. (b) T/H toologies. (a) Single-ended. (b) Differential. which also includes a differential realization incororating two bridges and differential re- and ost-amlifiers. Differential imlementations enjoy several advantages over single-ended aroaches including: rejection of common-mode errors such as ower suly modulation and unwanted signals couled onto differential signal nodes; elimination (ideally) of all even order distortion roducts; imroved dynamic range since signal ower quadrules (due to the doubled signal amlitude comared to the single-ended case) while noise ower only doubles; and the availability of both signal olarities which can frequently be used advantageously to imrove linearity or oerating seed. These benefits are countered by the disadvantages that the differential aroach requires more comonents (and hence die area) and consumes more ower than a single-

156 3. Error Sources in Diode Samling Bridges 5 ended imlementation. For the resent alication, the advantages accrued by the differential aroach outweigh the disadvantages; therefore, the more comlicated method was used as will be detailed in section Error Sources in Diode Samling Bridges T/H erformance and hence A/D erformance are limited by the oeration of the diodebridge circuit. Understanding the factors constraining their behavior is therefore crucial to develoing bridges with otimum secifications. The next several sections analyze the various error sources which iminge uon diode-bridge T/H oeration. 3.. Aerture Jitter Random variations in the otherwise eriodic samling interval caused by electronic noise will limit A/D converter erformance because temoral errors in the samling instant manifest themselves as equivalent amlitude errors at the quantizer outut [0], [5], [6], [3], [4]. Whereas the exlanation of this effect in section.3.3 redicted erformance bounds as limited by / LSB amlitude errors, the resent analysis redicts SNR degradation based uon the statistics of the signal and the samling clock hase noise. If a T/H circuit oerates with a samling eriod T T nom + τ jitter where τ jitter is a zero mean Gaussian random variable such that P ( τ jitter ) e τjitter πσ τ σ τ (3.8) and an analog inut signal V in () t Asin ( ω in t), then the voltage error due to the timing jitter is the roduct of the derivative of the inut signal (with resect to time) and the jitter (Fig. 3.8). This relationshi can be exressed using the notation of figure 3.8: V dv in τ jitter dt Aω in cos ( ω in t)τ jitter (3.9) In this equation, arbitrary inut amlitude, A, is assumed rather the full-scale amlitude assumed

157 6 Chater 3 Samle-and-Hold Design V fs V() t V fs sin ( πf in t) Sloe dv() t dt 0 V fsr V fs dv dv T dt dt Q V fs N V fs Figure 3.8. Aerture jitter gives rise to amlitude error. in figure 3.8. The noise ower due to jitter is σ jitter E { V} (3.0) where the exectation is calculated over all values of t such that 0 t T f in and over all

158 3. Error Sources in Diode Samling Bridges 7 values of τ jitter. (In the equations below, τ jitter is relaced by τ for simlicity.) T σ jitter T 0 T T T T 0 T 0 ( V) P τ Aω in ( ) dτdt [ cos ( ω in t)τ] P( τ) dτdt Aω in [ cos ( ω in t) ] dt τ P( τ) dτ T Aω in 0 T Aω in [ cos ( ω in t) ] dt τ P( τ) dτ ( ) T 0 ( Aω in ) σ τ ( Aπf in σ τ ) cos ( ω in t) dt σ τ (3.) The above differs from Wakimoto et al [3] but agrees with Martin and Secor [0]. The SNR due to timing jitter is σ S SNR jitter σ jitter ( πf in σ τ ) A ( Aπf in σ τ ) (3.) which is indeendent of the inut signal amlitude. For a given time jitter, τ jitter, the hase error, θ clock, is θ clock ω clock τ jitter (3.3)

159 8 Chater 3 Samle-and-Hold Design where ω clock is the radian clock frequency. Therefore, σ θ ω clock σ τ (3.4) Using this exression in equation 3., the SNR due to jitter becomes SNR jitter ( πf in σ τ ) ω in σ ω θ clock (3.5) or in decibels SNR jitter 0log ω clock ω in f clock 0log f in 0log ( σ θ )db 0log ( σ θ )db (3.6) Under Nyquist conditions where f clock f in this exression simlifies to SNR jitter 0log ( ) 0log ( σ θ )db 6 0log ( σ θ )db (3.7) This very simle result is indeendent of inut amlitude redicting SNR degradation solely in terms of samle clock sectral urity as secified by hase noise. To attain 6 db SNR (consistent with 0 effective bits of resolution), equation 3.7 constrains the standard deviation of the integrated hase noise to be less than.6 milliradians. At 00 MHz clock rates this hase noise translates to.5s standard deviation of jitter (using equation 3.4). Since this noise source will combine in a root-mean-square fashion with the quantization noise, total SNR will decrease by 3 db under such circumstances. To maintain total SNR including effects of clock jitter and quantization at an accetable level, SNR due to jitter alone must be reduced to a fraction of the above levels. To assess the combined effects of clock jitter and quantization noise, equation 3. can be modified to include both error sources resulting in:

160 3. Error Sources in Diode Samling Bridges 9 SNR j σ S + Q σ jitter A + σ Q ( Aπf in σ τ ) + ( A N ) ( πf in σ τ ) + ( 3) N ω in σ ω θ + ( 3) N clock (3.8) Exressed in decibels this equation becomes ω in SNR j + Q 0 σ ω θ ( 3) N log + clock 0log ( σ θ 4 + ( 3) N ) (3.9) where the last equality assumes ω clock ω in. Equations 3.7 and 3.9 are lotted in figure 3.9 from which σ θ can be read for a given quantizer resolution, N, and desired SNR. σ θ.5 milliradians ( σ τ 0.8s at f clock 00 MHz) is reasonable for a 0-bit quantizer. Phase noise or samle jitter exists on the clock signal driving the T/H but is increased by electronics within the clock buffer and bridge driver circuitry. A tyical bridge drive imlementation (Fig. 3.3) utilizes a differential transistor air (Q,Q) to control the bridge current. The hase noise in equations 3.6 and 3.7 is that at the collectors of the differential air. Consequently, noise contributions from the differential air and from the receding clock buffer must be referred to the collector nodes when calculating SNR loss. Such erformance degradation constrains the clock buffer design and will be addressed in more detail in section Small Signal Bandwidth Small-signal oeration of the diode-bridge in track mode was discussed in some detail in section 3.. Here the bandwidth of a track-and-hold based uon a bridge switch will be determined. The small-signal equivalent circuit of such a S/H in track mode (Fig. 3.0) relaces each diode with a resistor, r d, of value V T ( I Bridge ). Because the bridge is modelled by two Tee networks in arallel the simlified circuit of figure 3.0b can be used to determine its frequency resonse. In the

161 30 Chater 3 Samle-and-Hold Design 0 SNR jitter 6 0log ( σ θ )db SNR (db) N σ θ (radians) Figure 3.9. SNR as limited by clock jitter and quantization noise. Quantizer resolution labelled on curves. analysis which follows the variables r d and R L from figure 3.0b will be written as r d and R L resectively to clarify the notation. Care will be taken to aroriately accommodate this change in notation once the desired results have been derived. The outut voltage, V out, is develoed through an imedance divider from node. V out V sc H + r sc d H + sr d C H (3.30) V is in turn develoed through an imedance divider from V in : V Z V in r d + Z (3.3)

162 3. Error Sources in Diode Samling Bridges 3 R L r d r d V in X X V out r d r d C H R L (a) V in X r d r d / r d V R L r d C H X V out R L R L / (b) Figure 3.0. Small-signal models of diode-bridge in track mode. (a) Full model. (b) Simlified model when arallel networks are combined. where Z is the imedance seen from node to ground. ( + sr d C H ) Z R L ( r d + ) R sc L H ( + s( R L + r d )C H ) (3.3)

163 3 Chater 3 Samle-and-Hold Design V V in can therefore be simlified to: V V in ( + sr d C H ) R L ( + s( R L + r d )C H ) ( + sr d C H ) r d + R L ( + s( R L + r d )C H ) R L ( + sr d C H ) r d ( + s( R L + r d )C H ) + R L ( + sr d C H ) R L ( + sr d C H ) ( + ) + sc H ( R L r d + r d ) R L r d R L R L + r d ( ) ( + sr d C H ) R L r d + sc H r d + + R L r d (3.33) And the track mode small-signal transfer function becomes V out V in V out V V V in ( ) + sr d C H R L R L + r d ( ) R L ( + sr d C H ) ( R L + r d ) R L r d + sc H r d + + R L r d + sc H r d + + R L r d R L r d (3.34) To account for the notational change introduced earlier r d and R L must be relaced by r d and

164 3. Error Sources in Diode Samling Bridges 33 R L resectively giving V out V in R L R L + r d ( ) + r d R L + sc H r d r d + sc H + R L r d + R L r d sc H r d r d R L (3.35) where the last aroximation assumes R L» r d. Since r d is a very low resistance (less than 50Ω in most cases) this assumtion is well justified. Also, since the hold caacitance, C H, is generally much larger than the device intrinsic caacitances, the single-ole aroximation of equation 3.35 is valid. Therefore, to a very close aroximation, the diode-bridge will exhibit unity-gain at low frequency and a single-ole roll-off with time-constant, τ Bridge r d C H. For values of bridge current on the order of ma and hold caacitances of a few F, bandwidths near GHz are attainable. Therefore, small-signal frequency resonse is rarely a limiting factor for diode-bridge T/H erformance Preamlifier Track Mode Distortion Dynamic distortion arises in the reamlifier and samling bridge during track mode because these elements must suly dynamic current to circuit caacitors (arasitic and nonarasitic) at the frequency of the inut to the T/H. Conversely, the ostamlifier need not exhibit good linearity in track mode but must settle to a relatively distortion-free value during hold mode. In fact, this state of affairs is the motivation for receding A/D converters with samle-and-hold circuits. Only the reamlifier and switch need to exhibit dynamic linearity. All subsequent comonents, including the ostamlifier, comarators, and any other signal rocessing circuitry can have very oor dynamic linearity so long as they settle within the allotted time to an aroriate DC value. Since fast settling and good DC linearity are much easier to achieve than dynamic linearity considerable savings in ower and circuit comlexity can be achieved by isolating the

165 34 Chater 3 Samle-and-Hold Design required dynamic erformance to the reamlifier and switch. These elements can then be suitably otimized to realize the desired erformance with a net savings in ower and circuit comlexity. This section analyzes the dynamic distortion which affects the reamlifier and bridge during track oeration. Figure 3. deicts schematically the rototye reamlifier used for this study which is an 50Ω V in V out 50Ω C Load V src Asin ω in t V src A ω in t I Bias Figure 3.. Emitter follower reamlifier with caacitive load used to simulate dynamic distortion. emitter follower with an ideal current source and caacitive load. Comuter simulations assessed the dynamic erformance of this toology for various values of inut amlitude and frequency, bias current, and load caacitance. Insection of the resulting data (lotted in figure 3.) reveals the following emirical relationshi between total harmonic distortion (THD) and the various circuit arameters. f in C Load THD 40log I Bias + 0logA 8dB (3.36) A theoretical basis can be found for this exression as follows. At the quiescent oerating oint the. This statement is only true for frequencies which are significant relative to the time-constants of the circuit under consideration. The term dynamic in this context, therefore, imlies oeration at such frequencies.. THD is taken to be the sum of the outut ower from all harmonics divided by the outut ower in the fundamental and is usually exressed in decibels.

166 3. Error Sources in Diode Samling Bridges 35 THD (db) I Bias f in ma 50MHz A 500mV C Load 0.F A 50mV f in 50MHz C Load F -90 A 50mV Load Caacitance (F) 0. 0 Bias Current (ma) THD (db) I Bias ma f in 50MHz 0F I Bias ma A 56mV C Load F -90 C Load F Amlitude (Volts) C Load 0.F Frequency (MHz) Figure 3.. Simulated THD of the emitter follower reamlifier with caacitive load versus load caacitance, C Load, bias current, I Bias, amlitude, A, and inut frequency, f in. In each case, the arameter is varied in a,, 5, 0 attern which aroximates exonential sacing (i.e. each value is about twice the revious one) while maintaining integer values. inut and outut voltages are related by V outq V inq V BEQ (3.37) where the Q subscrit denotes the quiescent value. At any other oerating oint the more general relationshi holds: V out V in V BE (3.38)

167 36 Chater 3 Samle-and-Hold Design Subtracting equation 3.37 from equation 3.38 gives V out V in V BE (3.39) where V is the incremental value of V; that is, its change from the quiescent condition. Exressing V BE in terms of the transistor current gives V out V in V T ln I C I CQ I CQ V in V T ln V in V T ln + + I C I CQ V out I CQ Z L (3.40) where Z L is the load imedance at the outut of the emitter follower. By defining the arameter V B I CQ Z L I Bias Z L this exression further simlifies to V out V in V T ln + V out V B (3.4) For clarity the V terms can be relaced by V giving V out V in V T ln + V out V B (3.4) This exression can be exanded through use of the identity ln ( + x) x x + 3 x3 4 x4 + (3.43) to give V out V out V out 3 V out V in V T + V B 3 V B V B (3.44)

168 3. Error Sources in Diode Samling Bridges 37 or after rearrangement V V T in + Vout V V out V out T 3 V B V B V B (3.45) This relation exresses V in as nonlinear function of V out. To exress V out in terms of V in series inversion is erformed with the following useful formulae. if y a x+ a x + a 3 x 3 + then x A y+ A y + A 3 y 3 + a where A A a A 3 5 a a ( a a 3 ) a 3 A 4 7 a 5a a a 3 ( 3 a a4 5a ) (3.46) This rocedure gives V ( out + V T V )V 3 ( in B + V T V ) B V V + in + B V T 5 ( + V T V ) ( V T V B ) 3 + V B 6 in + V T V B 4 (3.47) which uon rearrangement becomes V B V ( out + V T V )V 3 ( in B + V B V ) T V V + in + T 5 ( V ( + V B V ) B V T V B ) 3 + V T 6 in + V T 4 (3.48) This olynomial exansion of V out as a function of V in can be related to harmonic distortion by

169 38 Chater 3 Samle-and-Hold Design making the following observations. If y can be exressed as a olynomial exansion in x y a 0 + a x+ a x + a 3 x 3 + (3.49) and x is a sinusoidal function of time, x() t Asin ( ωt), then y can be exanded as y() t a 0 + a Asin ( ωt) + a A sin ( ωt) + a 3 A 3 sin 3 ( ωt) + a 0 + a Asin ( ωt) a A cos ( ωt) a 3 A 3 3sin ( ωt) sin ( 3ωt) + 4 a A a ( a A+ 3 4 a 3 A3 ) sin ( ωt) + a A a 3 A 3 cos ( ωt) sin ( 3ωt) + 4 (3.50) The last exression in equation 3.50 can be simlified by noting that for weakly non-linear functions of the tye under consideration, higher order coefficients are small comared to a 0 and a. Under this assumtion equation 3.50 becomes a A a 3 A 3 y() t a 0 + a Asin ( ωt) cos ( ωt) sin ( 3ωt) 4 + (3.5) From this relationshi, the ratio of second harmonic amlitude to the fundamental amlitude can be easily calculated in terms of the coefficients of the original olynomial exansion: amlitudeofndharmonic HD amlitudeoffundamental a A a a A a A (3.5)

170 3. Error Sources in Diode Samling Bridges 39 similarly amlitudeof3rdharmonic HD 3 amlitudeoffundamental a 3 A 4a a 3 A 3 4 a A (3.53) Higher order distortion roducts, HD n, can be found in like manner. Using the coefficients for the olynomial exansion of V out from equation 3.48 in the exressions for HD and HD 3 gives ( )V B V T HD ( + V B V T ) 3 ( + V T V B)A A 4V T ( + V B V T ) (3.54) and 4 6( V B V T V B ) ( V T ) HD 3 4 ( + V B V T ) 5 ( + V T V B )A 4V T ( V B V T ) ( + V B V T ) 4A (3.55) These distortion roducts can be calculated in terms of circuit arameters by noting that V B» V T and recalling that V B I Bias Z L. With caacitive loading V B I Bias ( ω in C Load ). Therefore, HD 4V T A V T ( + V B V T ) 4 A V B V T 4 ω in C Load A I Bias (3.56) π f in C Load V T A I Bias

171 40 Chater 3 Samle-and-Hold Design or in decibels f in C Load HD 40log + 0logA + 0log ( π V T )db I Bias f in C Load 40log + 0logA.8dB I Bias (3.57) Note that this exression is identical in form to that in equation 3.36 which emirically redicted THD based uon comuter simulations. The sole discreancy between the two is a 6 db constant term which arises because the amlitude, A, in equation 3.36 refers to the alied signal which is attenuated by 6 db before reaching the inut to the emitter follower. Therefore, equation 3.57 accurately redicts dynamic distortion for a caacitively loaded emitter follower. Further, since the emirical THD matches the theoretical HD, total distortion is dominated by the second order comonent which can be largely cancelled if a differential structure is used. The third-order distortion can be calculated easily as well. HD 3 4V T ( V B V T ) V T ( + V B V T ) 4A V B 3 A HD 3 V T ω in C Load 3 A I Bias (3.58) π 3 V T 3 f in C Load 3 A I Bias and in decibels f in C Load π 3 V T HD 3 60log + 40logA + 0 log db 3 I Bias f in C Load 60log + 40logA 5.4dB I Bias (3.59) The above simle exressions for HD and HD3 can be used to design a T/H inut reamlifier which meets distortion secifications while dissiating minimum ower. Normally, comlicated mathematical techniques such as Volterra series must be emloyed to redict dynamic distortion

172 3. Error Sources in Diode Samling Bridges 4 requiring extensive analysis and simulation while affording little design insight. The method used above accurately extends from the simler DC case to redict high-frequency distortion characteristics because one dominant storage element of constant value (in this case the hold caacitor) influences circuit behavior at frequencies well below those where the intrinsic device caacitances become imortant. This technique would not accurately redict erformance in RF systems where the non-linear device caacitances are imortant at frequencies of interest Diode Bridge Track Mode Distortion Two henomena adversely affect linearity of the diode bridge itself. Firstly, the finite imedances with which the bridge must inevitably be biased cause the quiescent current to vary with inut signal, and secondly, the dynamic current which charges the hold caacitor enabling the outut signal to track the inut also erturbs the bridge oerating oint in a signal-deendent manner. These effects will be discussed searately. In an ideal biasing arrangement, such as that deicted in figure 3.4, erfect sources suly the oerating current to the diode bridge. In actual imlementations, circuit elements with finite imedance will drive the to and bottom nodes of the bridge. These imedances allow signal current to flow through and erturb balance of the bridge diodes in resonse to voltage variations at the bridge inut. A large-signal model of the diode bridge in track mode including finite biasing imedances (Fig. 3.3) shows the relationshis among these quantities. Here an aroximation has been made that the incremental voltage seen at the to and bottom of the bridge is equal to the incremental inut voltage. Using the result from section 3. that I D I D3 I D I D4 (Eq. 3.5), the diode currents can be related as follows: I Bias V in Z B V in Z B I Bias I Bias + I + I + ( I) I Bias ( I) (3.60) This equation exands to give I Bias ( + I) V in Z B I Bias ( I) (3.6)

173 4 Chater 3 Samle-and-Hold Design Z B Z B I Bias + I V in Z B I Bias I Bias V in Z B I I Bias V in Z B D D V in + V in V out + V out V in Z B D3 D4 I Bias I I Bias + I + V in Z B I Bias Figure 3.3. Large-signal model of diode bridge in track mode with finite bias imedances,. Z B which can be solved for I I Bias. I Bias ( + I) I Bias ( + I) I Bias ( I) V in Z B I Bias ( I) V in Z B I Bias I V in Z B I V in V in I Bias I Bias Z B V B (3.6) where V B I Bias Z L. At the quiescent oint the outut voltage can be exressed as the sum of the

174 3. Error Sources in Diode Samling Bridges 43 inut voltage and two diode voltage dros which are known functions of the diode currents. V outq V inq V BE4Q V BE3Q (3.63) At any other oerating oint the more general exression can be written: V out V in V BE4 V BE3 (3.64) Subtracting these two equations (and using incremental variables V V Q + V ) gives the relationshi between the V out V in V BE4 V BE3 V T ln I Bias I VT ln I Bias + I+ V in Z B I Bias I Bias I Bias I V T ln I Bias + I+ V in Z B I I Bias V T ln + I I Bias + V in V B (3.65) Using the result of equation 3.6, I I Bias ( V in V B ), and droing the notation for simlicity gives V out V in ( V in V B ) V T ln + ( V in V B ) + V in V B ( + V in V B ) ( V in V B ) V T ln ( + V in V B ) ( + V in V B ) ( V in V B ) V T ln ( + V in V B ) (3.66) Again, the olynomial exansion of ln ( + x) can be emloyed advantageously to exress V out

175 44 Chater 3 Samle-and-Hold Design as a olynomial function of V in. V out V in V V in T V in V in 3 V in V in V T V T V B V B V B V B V in V in 3 V in 3 4 V in V B V in V B V in V B V B V B V in V B V B (3.67) V T Vin V T V B 3 V in V B V in V B The absence of even-order comonents in the last exression in equation 3.67 imlies that the finite imedances of the bias current sources give rise to only odd-order distortion roducts. The dominant 3rd-order comonent is a 3 HD 3 A 4 a 3 3( V T V B ) 4 [ V T V B ] A V T V B ( ) ( V B V T ) [ V B V T ] V B [ V B V T ] A V B V T V B A A (3.68) V T 6 V B 3 A Where the aroximation above assumes V B» V T, a condition which always holds in ractice, and the sign of the result can be ignored since only relative amlitudes are of interest. Recalling that

176 3. Error Sources in Diode Samling Bridges 45 V B I Bias Z B, the distortion becomes HD 3 V T 6 ( ) I Bias Z B 3 A (3.69) or in decibels HD 3 40logA 60log ( I Bias Z B ) + 0log ( V T 6) db 40logA 60log ( I Bias Z B ) 47.6dB (3.70) In most cases Z B is resistive in nature, either because it is imlemented with an actual resistor connected to an aroriate voltage suly or because the active current source exhibits a small arasitic outut caacitance. Therefore, odd-order distortion roducts due to finite current source outut imedances exist even at low frequencies and must evaluated to ensure they are accetably low. Similarly to the outut imedances discussed above, finite imedance at the bridge outut causes signal current to flow through the bridge, thereby modifying the quiescent currents and leading to distortion. The incremental currents flowing in this situation (Fig. 3.4) again adhere to the constraint of equation 3.5 resulting in the following relationshi: I Bias ( + I) I Bias ( + I + I in ) I Bias ( I) I Bias ( I + I out ) (3.7) This exression can be solved for I as follows: I Bias I Bias I + I in + I I in I Bias I+ I Bias I out I I out I Bias I + I ( I in + I out ) I Bias I out ( ) I in (3.7) I Bias ( I out I in ) I I Bias + ( I in + I out )

177 46 Chater 3 Samle-and-Hold Design I Bias I Bias + I I Bias I D D V in + V in V out + V out I in D3 D4 I out C H I Bias + I + I in I Bias I + I out I Bias Figure 3.4. current into. C H Diode bridge with current erturbations caused by dynamic As in the revious cases the incremental inut and outut voltages are simly related V out V in V BE V BE V T ln I Bias + I I Bias I V T ln + I I Bias I I Bias (3.73) Using the exression for I found in equation 3.7 and disensing with the cumbersome

178 3. Error Sources in Diode Samling Bridges 47 notation the above equation becomes V out V in + V T ln I out I in I Bias + I out + I in I out I in I Bias + I out + I in V T ln I Bias + I out + I Bias I in V T ln + I out I Bias + I in I Bias (3.74) I out Performing KCL on a closed surface enclosing all four bridge diodes leads to the conclusion that I in I out. Note also that in turn is constrained by the imedance connected between the bridge outut and ground, temorarily called Z L, to be V out Z L ; that is, I out V out Z L. Therefore, equation 3.74 roduces V out V in V T ln V out V B + V out V B (3.75) where V B I Bias Z L. The right hand side of equation 3.75 is identical in form to the right hand side of equation 3.66 and therefore admits the same olynomial exansion arrived at in equation The resulting relationshi is V out V in V T ln V out V B + V out V B V T V out V B V out V B V out V B (3.76) which uon rearrangement exresses V in as a olynomial function of V out V in V out + V T V out V B V out V B V out V B (3.77) This equation can be inverted to give V out in terms of V in using the series inversion formulae

179 48 Chater 3 Samle-and-Hold Design described earlier (Eq. 3.46). V out ( + V T V )V ( in B + V T V ) B V T 3 3 V V 3 in B 4 (3.78) Since V out contains no even-order owers of V in, no even-order harmonics are generated from the bridge due to outut current flow. The dominant odd-order harmonic, the third, is (3.79) ( + V T V ) B HD 3 4 ( + V T V ) B 4 V T HD V A B 4 3 ( + V T V ) B 3 3 V T V B 3 V T V B 3 A A where the aroximation relies uon V B» V T which usually holds in ractical imlementations. Substituting I Bias ( ω in C H ) for V B yields HD 3 V T 6 ω in C H 3 A 4π 3 V T 3 I Bias f in C H 3 A I Bias (3.80)

180 3. Error Sources in Diode Samling Bridges 49 or in decibels f in C H HD A 0 4π 3 V T log + log + log db 3 I Bias f in C H 60log + I Bias 40logA + 0.6dB (3.8) 3..5 Finite Aerture Time Ideally, the track-to-hold transition occurs instantaneously at the samling moment imlying that the bridge diodes are switched from the conducting state to the non-conducting state sending no time in any intervening artially conducting mode. In a real T/H, such a discontinuity is imossible, and the bridge diodes send some finite time in transition between these conditions. Two significant effects arise from the non-zero transition or aerture time. First, high-frequency signals are attenuated because the resultant outut signal is averaged during the aerture window. This averaging oeration is linear but acts as a low-ass filter imosing a limit on the frequency resonse of the bridge. Second, the time-varying nonlinear imedance of the diode bridge introduces distortion into the held signal. These two effects will be discussed searately. Ignoring the nonlinear asects of the switching rocess, the diode bridge can be modelled as a time-varying linear resistor, r d () t, which charges the hold caacitor, C H (Fig. 3.5). If the V in r d () t () t V out () t C H Figure 3.5. Linear, time-varying model of diode bridge and hold caacitor used for finite aerture analysis. bridge bias currents (Fig. 3.4) switch linearly from their nominal values, I o, to 0over an aerture

181 50 Chater 3 Samle-and-Hold Design time t A (Fig. 3.6a), the bridge resistance will increase from its nominal value to infinity over the I(t) r d (t) I O 0 t A Aerture Time (a) t V T I O 0 t A (b) t Figure 3.6. Resonse of bridge current (a) and small-signal bridge resistance (b) over finite aerture time. same eriod (Fig. 3.6b). The bridge current and small-signal resistance can be described analytically as: I Bridge () t I o ( t t A ) (3.8) and r d () t V T () t I Bridge V T I o ( t t A ) (3.83) Alternatively, the bridge can be described by its conductance which is g Bridge () t I Bridge () t I o ( t t A ) V T V T (3.84) This function is not lotted but is a scaled version of the bridge current, I Bridge () t, shown in figure 3.6a. The differential equation which governs the bridge turn-off behavior can be derived by

182 3. Error Sources in Diode Samling Bridges 5 alying KCL to the outut node of the RC circuit shown in figure 3.5 giving V in () t V out () t () t r d C d H Vout dt () t (3.85) which uon rearrangement results in d V out dt () t + r d V ()C t out () t H r d V ()C t in () t H (3.86) The above relationshi is a linear time-varying differential equation whose time-varying asect is reflected by the coefficients r d ()C t H which are not constant but which change according to the diode small-signal resistance, r d () t. These time-constants can be arameterized by their value at time t 0which is τ o ( V T I o )C H and which is the recirocal of the bridge 3 db radian bandwidth during track mode: ω track ω 3dB τ o I o V T C H (3.87) Equation 3.86, along with the constraint on bridge resistance, r d () t V T [ I o ( t t A )], can be solved numerically for an inut sinusoid of given frequency and hase, V in () t Asin ( ω in t + φ), yielding an outut voltage at t which reresents the held signal corresonding to the samle at the relative hase φ between the inut sinusoid and the samling clock. By erforming this analysis for several equally-saced hases along the inut waveform a set of outut voltages reresenting a samled sinusoid results. The Fourier transform of this samled signal gives the outut amlitude and hase at frequency ω in. Assembling these results for many values of ω in, the frequency resonse of the system is found. Figure 3.7 dislays the results of such analysis comared with the simle single-ole frequency resonse of the bridge in track mode for several values of the normalized arameter ω track t A. The frequency resonse curves including the effects of finite aerture time follow closely the single-ole resonse until f t A 5; that is, until the aerture time is one fifth the eriod of the inut signal. Beyond this frequency the samling gain dros raidly exhibiting a null at f t A which aears because the inut sinusoid is integrated over exactly one eriod ( t A f T). Additional nulls exist whenever f t A equals an integer value, since the inut signal is then integrated over an integer number of eriods thereby generating outut equal to zero. Figure 3.7 shows that for reasonable

183 5 Chater 3 Samle-and-Hold Design 0-0 Magnitude (db) ω Track * t A /3 /6 /8 / f * t A Figure 3.7. Frequency resonse induced by finite aerture time assuming a linear small-signal bridge model. Uer curves reresent frequency resonse with constant bridge resistance, r d () t r d V T I o. Lower curves include the effect of bridge turn-off governed by r d () t V T [ I o ( t t A )]. frequency resonse the following conditions must revail: t A < 0f in (3.88) and ω track» π f in ω in (3.89) where f in is the desired oerating frequency of the track-and-hold. ω track must be much larger than π f in, otherwise significant attenuation occurs (even in track mode) since at ω track π f in signal attenuation is unaccetable (3 db). For a desired oerating frequency, f in, equal to 50 MHz, equations 3.88 and 3.89 mandate that t A ns and f track» 50MHz 500MHz. The first of

184 3. Error Sources in Diode Samling Bridges 53 these constraints generally does not ose a difficult roblem for a modern silicon biolar rocess like Tektronix SHPi. The second constraint laces a lower limit on the bridge bias current required for a given value of hold caacitance, C H. That is, I o ω track» τ o V T C H I o» V T C H f in f in (3.90) In the receding analysis, a simle ram was assumed for the bridge current waveform; however, the exact form of the turn-off mechanism is not critical so that if different switching characteristics are used (e.g. exonential decay rather than linear decay of the bridge current) qualitatively similar results obtain. The nonlinear effects of finite aerture time are more deleterious than the simle bandlimiting henomenon just described [6], [7], [5], [6]. The large-signal behavior of a diode bridge during the turn-off transient can be analyzed with the aid of equations 3.4 and 3.5 from section 3. which aly to figure 3.8a. These equations redict the bridge transfer characteristics during I(t) I O I(t) Vin(t) C H dvout dt Vout(t) C H I(t) 0 0 Aerture Time t A t (a) Figure 3.8. (b) Large-signal model for simulating finite aerture effects. track mode and are reeated here:

185 54 Chater 3 Samle-and-Hold Design V in V out I in I Bias tanh V T and I out I in (3.9) When combined, the two lines in equation 3.9 redict the outut current as a non-linear function of the inut and outut voltages. (By the associated reference convention both I in and I out are assumed to flow into the diode bridge in figure 3.8a.) V in V out I out I Bias tanh V T (3.9) The outut current is further constrained by the hold caacitor to be I out dv out C H dt (3.93) Equations 3.9 and 3.93 combine to give dv out () t dt I Bias C H V in () t V out () t tanh V T (3.94) Since I Bias is not constant but decreases from I o to 0 over the aerture time, t A, according to I Bias I o ( t t A ) (Fig. 3.8b), equation 3.94 becomes dv out () t dt I o C H V in () t V out () t tanh ( t V T ta ) (3.95) which is the non-linear, time-varying differential equation governing bridge turn-off with finite aerture time and a linearly ramed current decay. This equation deends exlicitly on the aerture time, t A, and the bridge slew-rate, I o C H ; and imlicitly uon the inut sinusoid amlitude, A, and frequency, f in (through the definition of V in () t assumed here to be a sinusoid). Intuitively, the nonlinear nature of the bridge gives rise to distortion because in the resence of a non-zero hold caacitor, the bridge outut voltage will not equal the bridge inut. The bridge outut current is a nonlinear function of this voltage difference and integrates on the hold caacitor resulting in a held voltage which is a nonlinear function of the inut signal. This henomenon (described in section

186 3. Error Sources in Diode Samling Bridges with reference to figure 3.4) is further exacerbated by the diminution of the bridge bias current over the aerture window. Equation 3.95 describes both of these effects and can be solved numerically for inut sinusoids of various hases and frequencies (as in the case above where the band-limiting effects of finite aerture time were investigated). Fourier transforms calculate the harmonic content of the resultant samled outut waveforms from which total-harmonic-distortion (THD) can be easily ascertained. Results from such analysis agreed very closely with those obtained via SPICE circuit analysis and are lotted in figure 3.9 as functions of the circuit arameters mentioned above; t A, B slew I o C H, A, and f in. The THD curves in figure 3.9 can be seen emirically to follow the relationshi THD [ 40logA + 60logf in + 30logt A 30log ( I o C H ) + 30]dB (3.96) within a few decibels over all regions of interest. This exression rearranges giving a form containing normalized arameters: THD 40logA + 60log ( f in t A ) + 30log ta + 30 db I o C H (3.97) Equations 3.96 and 3.97 can be used as guides when designing diode bridge switches and selecting circuit arameters which govern bridge oeration Hold Pedestal While the bridge diodes are conducting during track mode, they store charge on both their deletion caacitance and their diffusion caacitance. After the bridge switches to hold mode and all transients settle, the bridge diodes conduct no current with their terminal voltages determined by a mechanism deendent uon the articular imlementation of the switch. Regardless of the articular diode terminal voltages in this state, reduced charge is stored on the deletion caacitance, and the diffusion storage is zero. The difference in charge stored during track mode and hold mode is therefore exelled from each diode during the turn-off transient. If the charges exelled from the two diodes connected to the hold caacitor are not equal, the net charge injected onto that caacitor imarts an outut voltage erturbation called hold ste or hold edestal which,. The diodes can still conduct a small dislacement current owing to their non-zero junction caacitance. This effect is ignored here but will be discussed in section 3..7 which addresses bridge feedthrough in hold mode.

187 56 Chater 3 Samle-and-Hold Design A THD (db) f in t A 0.0 A 0. THD (db) THD (db) fin * ta A 0.56 f in t A Bslew * ta (Volts) ( I 0 C H )t A f in t A 0. ( I 0 C H )t A 0. A Bslew * ta (Volts) A.0. fin * ta f in t A 0.05 A 0. ( I 0 C H )t A Amlitude (Volts) ( I 0 C H )t A 0.. Amlitude (Volts) Figure 3.9. Simulated THD due to finite aerture time as a function of inut amlitude, A, inut frequency, f in, aerture time, t A, and bridge slew rate, I 0 C H. Parameters are swet in a,, 5, 0 fashion to aroximate an exonential swee with integer values. if non-linearly deendent uon the inut signal, introduces distortion into the samled outut stream. This distortion mechanism can be analyzed by determining the diode oerating voltages

188 3. Error Sources in Diode Samling Bridges 57 before and after the track-to-hold transition. In a tyical embodiment (Fig. 3.0a), the diode bridge C j D D V in V out 3 C jo D3 D4 C H -V d -V out -V d +V out -Vd 0 +V d (a) (b) Figure 3.0. Charge injection at bridge turn-off gives rise to hold edestal distortion. (a) Tyical bridge circuit showing auxiliary diodes which control bridge bias voltages in hold mode. (b) Diode small-signal caacitance-voltage characteristic. is turned off by reversing the olarity of the bias current, thereby forcing this current to flow through two auxiliary diodes which in turn reverse bias the bridge diodes. While tracking, diodes D through D4 conduct nominally equal currents corresonding to the bias voltage + V d (oint on the diode small-signal deletion caacitance curve of figure 3.0b). During hold mode the bridge current forward biases the two auxiliary diodes which now control the uer and lower bridge node voltages. If the auxiliary diodes have twice the area as the bridge diodes, then the uer bridge node moves to V d Volts and the lower bridge node to + V d Volts. Therefore, the voltage across D4 becomes V out V d while D sees V d V out Volts (figure 3.0b oints and 3 resectively). Notice that in the imlementation deicted in figure 3.0a the maximum allowable inut amlitude is V d. If the inut signal exceeds this value, diodes D and D3 will become at least slightly forward biased severely reducing the isolation rovided by the bridge in the hold mode. If larger signal. This constraint ensures that the auxiliary diodes oerate at the same current density in hold mode as do the bridge diodes in track mode. Without this restriction, the auxiliary diodes forward bias otential will be lower than bridge diodes by V T ln Volts. This difference does not materially affect the analysis or results resented here. In fact, the auxiliary diodes are usually made larger than the bridge diodes for another reason to reduce arasitic resistance which increases feedthrough during hold mode.

189 58 Chater 3 Samle-and-Hold Design swings are required, multile diodes in series can relace each auxiliary diode. Since the diode caacitance-voltage characteristic is a small-signal quantity, the difference in stored charge at two oerating oints can be calculated by integrating the C-V function between the voltages of interest. dq C j ( V) dv dq C j ( V) dv Q Q dq V V C j ( V) dv (3.98) Q Q Q V V C j ( V) dv Therefore, the net charge injected onto the hold caacitor which is the difference between the charges injected by diodes D and D4 can be exressed as Q inj Q D4 Q D V d + V out V d V d + V out V d V out C j4 C j ( V) dv ( V) dv V d V d V out C j ( V) dv (3.99) where the C-V curves of diodes D and D4 are assumed identical, i.e. C j ( V) C j4 ( V) C j ( V). The last integral in equation 3.99 reresents the shaded area under the C-V curve in figure 3.0b. The diode diffusion caacitance does not contribute to Q inj because the stored diffusion charge due to diodes D and D4 is nominally equal and will therefore sum to zero at the outut node. Any small differences in this charge due to device mismatches result in a signal indeendent edestal which disturbs every outut samle and therefore aears as an offset comonent of the T/H circuit. In the absence of other error sources, the injected charge, Q inj,

190 3. Error Sources in Diode Samling Bridges 59 will revent the held outut from equalling the inut according to Q inj V out V in C H (3.00) so that the inut signal can be exressed as a function of the outut signal: Q inj V in V out + C H V out + C H V d + V d V out V out C j ( V) dv (3.0) Notice that V in is a urely odd function of V out regardless of the nature of C j ( V) since V in ( V out ) V out + V out C H C H V in ( V out ) V d V d + V + d V d V out V out V out V out C j C j ( V) dv ( V) dv (3.0) Therefore, by insection of the formulae for series inversion (Eq. 3.46), V out will also be an odd function of V in and only odd-order harmonics can arise from the hold edestal henomenon. This claim is invalid if comonent mismatches are encountered such that C ( V) C j j4 ( V). Nonetheless, reasonable comonent matching should minimize even-order distortion roducts. V in can be exressed as a olynomial function of V out by forming the Taylor series exansion of the relationshi found in equation 3.0. That is, 3 V in a V out + a V out + a 3 V out + where n a n d Vin ( V n! n out ) dv Vout 0 out (3.03)

191 60 Chater 3 Samle-and-Hold Design a can be found directly from equations 3.0 and 3.03 by recalling Leibnitz Rule: if bx () ϕ() x ft (, x) dt ax () then (3.04) bx () d ϕ() x dx ft, x x ax () ( ) dt+ f[ b()x x, ] d bx dx () f[ a()x x, ] d ax () dx Alying Leibnitz Rule to equation 3.0 gives dv in + dv out C H V d V d + d CV ( ) dv + d V out V out V out + [ C( V d + V out )( ) C( V d V out )( ) ] C H + [ C( V d + V out ) + C( V d V out )] C H (3.05) So that a dv in d Vout V out 0 + [ C( V d ) + C( V d )] C H C ( V d) + C H (3.06)

192 3. Error Sources in Diode Samling Bridges 6 The higher order derivatives can be found in a straightforward manner. n dv in d n V out C H d ( n ) d C( V d + V out ) + d ( n ) Vout ( n ) d C( V d V out ) ( n ) V out ( n ) C Vd d ( + V out ) C ( n ) H d( + ) + C H V d V d V out d ( n ) C( V d V out ) ( n ) d( ) V out d( ) V d + V out dv out d( ) V d V out dv out n + n (3.07) C H d ( n ) C Vd V d ( + ) d( + ) V out V out ( n ) ( ) n d n ( ) C( V d V out ) + ( n ) d( ) V d V out ( ) n C H d ( n ) C Vd V d 0 forneven ( + ) d( + ) V out V out ( n ) fornodd All even coefficients of the olynomial exansion of V in are therefore zero as noted earlier, and the odd coefficients become n a n d Vin ( V n! n out ) dv Vout 0 out n! n! C H d ( n ) C Vd V d ( + ) d( + ) C H dv d n V out ( ) CV ( ) ( n ) V out ( n ) V V d V out 0 (3.08) If the diode small-signal caacitance can be described by C j ( V) where C j ( V) dq dv C jo V ( ) V BI m (3.09)

193 6 Chater 3 Samle-and-Hold Design where C jo is the zero-bias caacitance, V BI is the built-in otential usually near 0.7 Volts, and m is a factor equal to about / which deends uon the junction doing rofile, then the odd coefficients can be exressed as: d n a n n! C H d( V) ( ) CV ( ) C jo m m + n! C H ( n ) V V d ( ) ( m+ n ) n V BI C jo Γ( m + n ) n! C H Γ( m) n V BI ( + V d V BI ) m+ n ( + V d V BI ) m+ n (3.0) where Γ() x is the Gamma or generalized factorial function. With the coefficients known for the olynomial exansion of V in in terms of V out, the series can be inverted using the formulae listed in equation 3.46 to give 3 V out A V in + A V in + A 3 V in + (3.) where A a C ( V d) + C H C jo + C H ( + V d V BI ) m (3.) and a a a 3 a 3 A a a C jo m( m + ) 3 C H V BI ( + V d V BI ) m+ C 4 jo + C H ( + V d V BI ) m (3.3) The exressions for A and A 3 can be used to calculate the gain and third harmonic distortion

194 3. Error Sources in Diode Samling Bridges 63 comonent due to hold edestal. If V d V BI, simlifications in the resulting equations arise. A V A C jo + C H ( + V d V BI ) m C jo + C H ( m) (3.4) C jo m C H ( ) where the last exression is based uon the binomial exansion and the assumtion that C H» C jo ( m) which is well founded in ractical circuits since m is a constant near / and C H is usually more than an order of magnitude greater than C jo. A 3 HD 3 A 4 A C jo m( m + ) 3 C H V BI ( + V d V BI ) m+ 4 C 3 jo + C H ( + V d V BI ) m C jo m( m + ) C H V BI HD 3 C jo + C H C jo ( m) m + 3 A m( m + ) C + A H m V BI A (3.5) If m is assumed to equal /, and V BI is 750mV (3/4 V) then the equations for gain and third order distortion further simlify to A V C jo C H (3.6)

195 64 Chater 3 Samle-and-Hold Design and C jo HD 3 A 36 C H (3.7) or in decibels A V 0 C jo log 0ln C jo C H C H 0 C jo db ln 0 C H.3 C jo db C H ln 0dB (3.8) and C jo HD 3 40logA + 0log + 0log ( )db 36 C H C jo 40logA + 0log 34.dB C H (3.9) The accuracy of this analysis is demonstrated in figure 3. which lots gain and HD 3 as calculated analytically and as redicted by SPICE. The to lot in the figure comares SPICE results with those obtained by included many higher-order terms in the olynomial exansion and series inversion of equation 3.0, while the bottom lot uses the simler aroximations from equations 3.4 and 3.5. Note that in all cases the redicted erformance is within a few decibels of the simulated result, thereby ensuring fast but accurate rediction of distortion due to the hold jum henomenon. If excessive distortion or gain loss results from hold edestal, a unity-gain amlifier driving the bridge center ta from the outut node (Fig. 3.a) can reduce the effects to a ossibly accetable level [5], [6], [0]. Analysis of hold edestal with feedback roceeds as in the case without feedback with the modification that the center-ta voltage is no longer grounded but is assumed to be a function of the outut voltage. In this case, diodes D and D4 switch between the

196 3. Error Sources in Diode Samling Bridges T/H Harmonics Due to Hold Jum (SPICE & Analysis) Av -40 dbc HD HD Cjo/Ch 0-0 T/H Harmonics Due to Hold Jum (SPICE & Aroximations) SPICE Av Aroximation dbc HD3-70 Aroximation SPICE Cjo/Ch Figure 3.. Comarison between distortion due to hold edestal redicted by analysis and simulation (uer); and between distortion redicted by simle aroximations and simulation (lower). track mode with each biased at + V d, and hold mode where D is biased at ( V CT V d ) V out Volts and D4 at V out ( V CT + V d ) Volts. The feedback amlifier is assumed for simlicity to be memoryless with a linear transfer function described by its outut-referred offset, V off, and its gain, α, which is ideally unity. Therefore, V CT V off + αv out, and the diode voltages in hold mode become V D V d + V off ( α)v out and V D4 V d V off + ( α)v out as shown in figure 3.b. The equation governing the edestal (analogous to equation 3.0) is therefore

197 66 Chater 3 Samle-and-Hold Design C j D D A V V in V out 3 C jo D3 D4 C H (a) 0 -V d +V d -V d -V out (-A ) -V V d +V out (-A ) V (b) Figure 3.. A bootstraed bridge center-ta reduces hold edestal distortion. (a) Unity-gain buffer drives bridge center-ta from outut node. (b) Diode C-V characteristic still determines residual charge injection. Q inj V in V out + C H V out + C H V d V off + V out ( α) C j V d + V off V out ( α) ( V) dv (3.0) This equation can be slightly modified to attain the same form as equation 3.0 so that the coefficients of the Taylor series exansion, found for the case of a grounded center ta node, can be alied directly to the resent case. V in V out + C H V in αv out V off V out αv out V off V in αv out V off V out ( α) V off V x + C H V d V off + V out ( α) C j ( V) dv V d + V off V out ( α) V d V off + V out ( α) + C C j H V d + V off V out ( α) V d V off + V out ( α) + C C j H V d + V off V out ( α) V d + V d V x V x C j ( V) dv ( V) dv ( V) dv (3.)

198 3. Error Sources in Diode Samling Bridges 67 where V x V out ( α) V off and the right hand side of the last equation in 3. is identical in form to equation 3.0. Since the coefficients, a n, of the Taylor series exansion of this form are known (Eqs and 3.08), The exansion in terms of V x can be written immediately: 3 V in αv out V off a V x + a V x + a 3 V x + (3.) C j( V d ) + C H Vx + n! n 3 nodd C H d ( n ) Cj V dv ( n ) ( ) V V d Vx n If V off is negligibly small, then V x becomes V out ( α) and 3. can be written V in αv out C j( V d ) + C H Vx + n! n 3 nodd C H d ( n ) Cj V dv ( n ) ( ) V V d Vx n C j( V d ) + ( α)vout + C H + n 3 nodd n! C H d ( n ) Cj V dv ( n ) ( ) V V d [ ( α)v out ] n (3.3) V in ( α) C j( V d ) + Vout + C H ( α) n n d + n! C n 3 H dv nodd ( ) Cj V ( n ) ( ) V V d n Vout So the Taylor series coefficients for the exansion of V in as a function of V out are ( α) n a n n! a ( α) C j( V d ) + C H d ( n ) Cj V dv ( n ) ( ) C H V V d n 3 nodd (3.4)

199 68 Chater 3 Samle-and-Hold Design If the diode caacitance-voltage relationshi, coefficients become C j ( V), is described by equation 3.09, then the C jo a ( α) C jo + C H ( + V d V BI ) m Γ( m+ n ) a n n! C H Γ( m) n V BI ( α) n ( + V d V BI ) m+ n n 3 nodd (3.5) With the coefficients known for the olynomial exansion of V in in terms of V out, the series can be inverted using the formulae listed in equation 3.46 to give 3 V out A V in + A V in + A 3 V in + (3.6) where A a ( α) C jo + C H ( + V d V BI ) m (3.7) and a a a 3 a 3 A a a C jo m( m+ ) 3 C H V BI ( α) 3 ( + V d V BI ) m+ ( α) C jo + C H ( + V d V BI ) m 4 (3.8) The exressions for A and A 3 can be used to calculate the gain and third harmonic distortion

200 3. Error Sources in Diode Samling Bridges 69 comonent due to hold edestal. If V d V BI, simlifications in the resulting equations arise. A V A ( α) C jo + C H ( + V d V BI ) m ( α) C jo + ( m) C H (3.9) ( α) C jo m C H ( ) where the last exression is based uon the binomial exansion and the assumtion that C H» ( α)c jo ( m) which is well founded in ractical circuits. A 3 HD 3 A 4 A 4 HD 3 C jo m( m + ) 3 C H V BI ( α) 3 ( + V d V BI ) m+ ( α) C jo + C H ( + V d V BI ) m C jo m( m + ) C H V BI ( α) 3 m+ ( α) C jo + C H ( m) 3 A C jo m( m+ ) ( α) 3 C + A H m V BI 3 A (3.30) If m is assumed to equal /, and V BI is 750mV (3/4 V) then the equations for gain and third order distortion further simlify to A V ( α) C jo C H (3.3)

201 70 Chater 3 Samle-and-Hold Design and HD 3 36 ( α)3c jo A C H (3.3) or in decibels A V 0 ( α) C jo log C H 0 ( α) C jo db ln 0 C H (3.33).3 ( α) C jo db C H and C jo HD 3 40logA + 0log + 60log ( α) + 0log ( )db 36 C H C jo 40logA + 0log + 60log ( α) 34.dB C H (3.34) Notice that both gain loss (in db) and third harmonic distortion are greatly reduced by the resence of the ( α) term. Also, if α, then A V 0dB and HD 3 db as desired. If V off is not negligible but α is very near unity then V x V off and 3 V in V out V off a V x + a V x + a 3 V x + C j( V d ) + + n 3 nodd n! C H C H V out V in C j( V d ) + V C off + H n! n 3 nodd ( V off ) + d C H ( n ) Cj V dv d ( n ) ( ) ( n ) Cj V dv ( n ) ( ) V V d V V d ( V off ) n n Voff (3.35)

202 3. Error Sources in Diode Samling Bridges 7 In this case the held samle, V out, equals the inut lus an offset term which is the indicated function of the auxiliary amlifiers outut offset voltage, V off. Therefore, hold edestal with unity gain feedback to the bridge center ta results in an offset error at the bridge outut but no gain error or distortion Feedthrough When the samling bridge is in hold mode, current is revented by aroriate means from flowing through the bridge diodes so that ideally the bridge imedance becomes infinite, thereby isolating the hold caacitor from the inut signal. Because of non-idealities in the bridge diodes, notably finite junction caacitance, the isolation is not comlete. The extent to which the inut signal affects the held outut voltage in hold-mode is characterized by feedthrough which is the gain of the bridge, ideally zero, and which is usually exressed in decibels. In a tyical diode bridge (shown with its concomitant switching circuitry in figure 3.3) all bias current is caused to flow in I Bridge I Bridge D D Vin X D6 V CT X Vout D3 D5 D4 C H I I Hold Q Q Track I Bridge Figure 3.3. Diode-bridge track-and-hold with differential air controlling bridge current. Diodes D5 and D6 conduct during hold-mode while diodes D through D4 are cut-off. the auxiliary diodes thereby forcing current in the bridge diodes to zero. In the examle shown, I I Bridge, I 0, I D5 I D6 I Bridge, and I D I D I D3 I D4 0.

203 7 Chater 3 Samle-and-Hold Design Therefore, the bridge diodes small-signal resistance, V T I D, becomes very large and the auxiliary diodes small-signal resistance becomes small. The bridge and auxiliary diodes now form a voltage divider severely attenuating signals as they ass from inut to outut. Because of the diode junction caacitance in arallel with the small-signal resistance this attenuation characteristic is frequency deendent. A small-signal model of the switch in hold mode (Fig. 3.4a) includes all of the Cd Cd r d Vin r d r 0 Av C H Vout Cd Cd (a) Vin Cd V To Cd r d / V FB r 0 Av C H Vout (b) Figure 3.4. Small-signal models of bridge in hold mode. (a) Model including all comonents. (b) Equivalent model simlified through symmetry. significant circuit elements necessary to analyze the nature of hold-mode behavior. Note that distortion in this mode is unimortant since any signal at the bridge outut is unwanted; and since the bridge outut is greatly attenuated leading to signals which are largely distortion free. Therefore, small-signal models adequate describe circuit behavior in hold mode. The bridge model (Fig. 3.4a) includes C d, the diode small-signal junction caacitance, for those diodes which are nonconducting, and rd, the diode small-signal resistance, for those diodes which are conducting during hold mode. Also included in the model is an amlifier with A V gain and r o outut resistance feeding its signal from the bridge outut to the bridge center ta. These arameters can be set to zero if the bridge center ta is grounded directly rather than driven by an amlifier. Bridge feedthrough

204 3. Error Sources in Diode Samling Bridges 73 analysis roceeds by noting that this model includes identical elements mirrored above and below a horizontal line of symmetry. By combining in arallel those elements which by symmetry are seen to exhibit identical node voltages, the simlified network of 3.4b results which can be solved most easily by nodal analysis. The 3 equations which govern circuit oeration are: ( V in V To )sc d V out V To ( V To V out )sc d V out + ( )sc d + ( V FB V To ) r b 0 V FB sc H 0 A V V out (3.36) where r b r d + r o. The second constraint above can be solved for V out in terms of V To and the third constraint gives V FB in terms of V out. V out V FB C H C d + C d A V C d + C d C H V To V To (3.37) These two relations allow V in to be exressed solely as a function of V To : V in V To sc d ( C H + C d ) s4c d ( C H + C d ) + ( C r H + C d ( A V )) b (3.38) When the above equation is combined with the first exression in 3.37 the hold mode gain results. V out V in C d C H + C d s + s ( A V )C d + C H 4r b C d ( C H + C d ) (3.39) where r b r d + r o This equation indicates that the inut-outut transfer function exhibits a zero at DC and a ole at a frequency deendent uon the circuit arameters. The exression for this ole frequency can be

205 74 Chater 3 Samle-and-Hold Design simlified if C H» C d in which case ( A V )C d + C H τ ft 4r b C d ( C H + C d ) 4r b C d 4r b C d τ ft (3.40) Therefore, the inut-outut characteristic simlifies to V out V in C d C H + C d s s + τ ft (3.4) The magnitude of this transfer function is V out V in s jω C d C H + C d C d C H + C d ω + τ ft + ( ωτ ft ) ω (3.4) which is lotted in figure 3.5. Since, r b is a few tens of ohms and C d is a few tens of femtofarads, C d C d + C H 0log H( jω) C d ωτ C d + C ft H 0 db/decade τ ft 4r b C d V out V in s jω ω Figure 3.5. Small-signal frequency resonse of diode bridge in hold mode.

206 3. Error Sources in Diode Samling Bridges 75 the ole frequency, τ ft, is many tens of Gigahertz; therefore, at all frequencies of interest ωτ ft «and the exression for feedthrough can be simlified: V out V in s jω C d C H + C d + ( ωτ ft ) C d C H + C d ( ωτ ft ) C d ωτ C H + C ft d C d C H + C d 4r b C d C H ω 4r b C d ω (3.43) where C H» C d was assumed in the last simlification. The frequency-deendent feedthrough in hold mode is simly: C d Feedthrough( ω in ) 4r b ω C in H (3.44) Notice that hold caacitance, C H, is the only arameter which can be freely varied since r b cannot reasonably be made smaller than about 0Ω; C d is a fixed device constant deendent uon the rocess being used; and ω in is a arameter of the erformance goals for the circuit. Feedthrough can be made arbitrarily low by increasing the value of C H which will also decrease distortion due to hold edestal, but at the exense of increased track mode distortion in both the reamlifier and the diode bridge itself. If a satisfactory trade-off cannot be made with this aroach and a differential imlementation is used, caacitively couling signals from the comlementary bridge can artially cancel the residual signal at the hold caacitor affording an added degree of signal attenuation [0]. An embodiment of this concet (Fig. 3.6) entails couling caacitors from the to and bottom nodes of each bridge to the outut node of the comlementary bridge. Cancellation of the outut signal occurs during hold mode if the value of the couling caacitance equals the value of the corresonding diode junction caacitance. If this condition holds, caacitor CB coules a signal from the to of bridge B onto hold caacitor C HA equal in magnitude to the signal couled through diode DA onto C HA ; however, since bridge B receives an inut signal comlementary to

207 76 Chater 3 Samle-and-Hold Design CA CB DA DA DB DB VA VB D3A D4A CHA CHB D4B D3B Bridge A C4A +Vout C4B Bridge B Figure 3.6. Cross-couled caacitors between comlementary bridges reduce feedthrough and hold edestal error. bridge A, the signal couled through CB is comlementary to that couled through DA. Therefore, the net couling onto the hold caacitor is zero. Similarly, CA cancels the couling through DB; C4A cancels D4B; and C4B cancels D4A. These cancellations also oerate during track mode but since the bridge imedance is then very low, the effect is negligible. The bridge diode bias voltages vary from track mode to hold mode and also deend uon the signal at the bridge center tas, labelled V A and V B in figure 3.6. Diode and cross-couling bias voltages are tabulated for reference in table 3.. If the bridge center tas are grounded (or more generally set to the inut Element Track Mode Potential Hold Mode Potential V Hold V V Track DA V d ( V A V d ) ( V in ) V A V d V in D4A V d ( ) ( V A V ) V in + d V A V d + V in DB V d ( V B V d ) ( V in ) V B V d + V in D4B V d ( V in ) ( V B V ) + d V B V d V in CA C4A Table 3.. ( V in + V d ) V in ( V in V d ) V in ( ) ( V A V d ) ( V in ) V A V d Bias voltages across bridge elements in track mode and hold mode. V in ( ) ( V A + V d ) ( V in ) V A + V d V in

208 3. Error Sources in Diode Samling Bridges 77 Element Track Mode Potential Hold Mode Potential V Hold V V Track CB C4B Table 3.. ( V in + V d ) ( V in ) ( V B V d ) ( V in ) V B V d + ( V in V d ) ( V in ) ( V B + V d ) ( V in ) V B + V d + V in Bias voltages across bridge elements in track mode and hold mode. V in common-mode voltage) then the diode bias otential in hold mode is that listed in table 3. evaluated with V A V B 0 and each air of diodes, (DA, D4A) and (DB, D4B), coules from the bridge to and bottom nodes to the bridge oututs with caacitances C j ( V d + V in ) and C j ( V d V in ). The sum of these caacitances (reresenting the net caacitance couled from the bridge to and bottom to the bridge outut) will equal to a first order aroximation C j ( V d ). Therefore, if CA, C4A, CB, and C4B are equal in caacitance to C j ( V d ) significant cancellation in bridge feedthrough results. If the bridge center tas are driven with unit-gain amlifiers from their resective bridge oututs ( V A V in and V B V in ), the resultant hold mode bias voltage on each of diodes DA, D4A, DB, and D4B is V d. Therefore, these diodes junction caacitances are each C j ( V d ) and erfect feedthrough cancellation occurs if the crosscouling caacitors take on this same value. Mismatches in the cross-couling caacitors from their ideal values, C j ( V d ), will be relatively large because the added caacitors will most likely be imlemented with metal-insulator-metal (MIM) or metal-insulator-semiconductor (MIS) structures which do not track diode caacitance well. Simulations which redict bridge feedthrough as a function of cross-couling caacitance (Fig. 3.7) indicate high sensitivity to mismatches. For examle figure 3.7 indicates that a nearly 40 db increase in feedthrough arises when the crosscouling caacitance deviates from the ideal value by 5%. Better matching can be obtained by constructing the cross-couling caacitors from diodes similar to those comrising the bridge. Simle diodes are inaroriate because they will become forward biased interfering with normal bridge oeration so structures involving multile diodes connected to revent current flow are necessary (Fig. 3.8). Such realizations incur arasitic substrate caacitances which inevitably detract from the achievable signal cancellation, but better matching can indeed be achieved (Fig. 3.9) The simulation leading to the data lotted in figure 3.9 relaced each couling caacitor with. Substrate caacitances are significantly reduced if a fully oxide-isolated rocess is used or if a semi-insulating substrate such as in Gallium-Arsenide (GaAs) is used.

209 78 Chater 3 Samle-and-Hold Design Feedthrough (db) Cross Couling Caacitance (normalized to otimum) Figure 3.7. Feedthrough versus cross-couling caacitance normalized to otimum value. Figure 3.8. Cross-couling scheme for reduced feedthrough with series connected diodes as couling elements. two diodes connected in series but with oosite olarity. The figure indicates that such an arrangement can achieve feedthrough near 00 db even with diode area deviations of a few ercent, matching which is easily attained in most modern semiconductor rocesses. The hold edestal henomenon described in section 3..6 can also be mitigated somewhat

210 3. Error Sources in Diode Samling Bridges Feedthrough (db) Cross Couling Diode Area (normalized to otimum) Figure 3.9. Feedthrough versus area of cross-couled diode structure normalized to the otimum area. with this cross-couling arrangement. In this case, the charge which is cancelled is that exelled from the bridge diodes when switched from the conducting to the non-conducting state. Figure 3.30 indicates how the cross-couling caacitances can artially cancel the charges exelled by the bridge diodes during bridge turn-off. For this cancellation to be comlete however, the crosscouling elements must exhibit the same non-linear C-V characteristics as the bridge diodes and must also exerience the same voltage transitions during the turn-off transient (see for examle figure 3.0). The initial and final voltages across the diode and cross-couling elements at the trackto-hold transition comiled in table 3. are again helful in studying such oeration. The last column of this table indicates that with V A V B 0, the bridge diodes exerience the same voltage transitions as do the ertinent cross-couling elements; however neither fixed caacitors nor series couled diodes rovide the aroriate C-V characteristic to achieve exact charge injection cancellation. Therefore, only first-order cancellation is ossible with this method, imroving gain loss due to hold edestal but leaving distortion unaffected. If the bridge center tas are driven by amlifiers from the resective bridge oututs such that V A V out and V B V out, then hold edestal is negligible anyway (recall the analysis from section 3..6) so this cross-cancelling

211 80 Chater 3 Samle-and-Hold Design Figure Cross-couling can artially cancel hold edestal error by cancelling charge exelled by bridge diodes during bridge turn-off. Note that charge injection from a bridge diode connected to the to node of one bridge is cancelled by the cross-couled element connected to the bottom node of the comlementary bridge. Likewise, injection from a diode connected to the bottom of one bridge is cancelled by the cross-couled element connected to the to of the comlementary bridge. aroach is unnecessary. Although the cross-couling scheme described here can reduce feedthrough and gain loss from hold edestal, its several drawbacks including sensitivity to device mismatches, added arasitic caacitances loading the bridge, and increased layout comlexity call into question the utility of the technique; therefore, this aroach was not utilized in the resent design Noise Electronic noise generated by the elements within the track-and-hold contaminates the inut signal before digitization. Therefore, this noise must be negligible comared to quantization noise to revent the T/H from limiting the achievable SNR of the A/D converter. Moreover, several noise sources affect T/H oeration in ways that are unique from more general urose circuits. Such sources which comrise T/H noise include: Samle clock jitter as exacerbated by noisy clock buffer electronics within the T/H itself

212 3. Error Sources in Diode Samling Bridges 8 Electronic noise seen at the hold caacitor during track mode Electronic noise which adds to the held voltage during hold mode Shot noise from the ostamlifier bias current which is integrated on the hold caacitor during the hold eriod These sources are summarized in figure 3.3 and will be described searately below. Since the noise Clock Clock Buffer σ τ +V in -V in Pream and Bridge Pream and Bridge C H C H kt C noise I B V out Figure 3.3. Noise sources affecting track-and-hold oeration. reresents the total jitter noise ower on the drive signals to the diode bridge including the jitter on the incoming clock and that added by the clock buffer circuitry. kt C reresents the mean-square noise voltage at the hold caacitors. This is an aroximation assuming that the dominant comonent is thermal noise and exists during both track mode and hold mode. I B causes base shot noise which is integrated on the hold caacitor during hold mode giving rise to voltage noise. σ τ sources listed are uncorrelated, the total noise ower emanating from the T/H is the sum of all of these comonents. Total noise from an A/D converter includes this electronic noise from the T/H lus quantization noise so that SNR can be exressed as SNR σ Q σ Jitter σ Signal σ Track σ Hold σ Shot (3.45) where σ Track is the noise ower added to the signal during track mode, σ Hold is the noise ower

213 8 Chater 3 Samle-and-Hold Design added to the held signal during hold mode, and σ Shot is the shot noise integrated on the hold caacitor during hold mode. The comonents of noise ower found in the denominator of equation 3.45 are now discussed with the excetion of the quantization noise ower, σ Q, which was described in detail in section.3.. The effect of clock jitter on SNR was treated in section 3.. from a theoretical standoint. Here the deleterious effects of electronic noise in the clock buffer on the incoming clock signal are discussed. The function of the clock buffer circuitry is to rovide gain and level shifting so that a standard logic-level signal can switch the diode bridge. In so doing, noise within the buffer will exacerbate the jitter of the samling signal seen at the to and bottom nodes of the diode bridge. The resultant clock noise at the bridge drive nodes (which was the subject of section 3..) derives from the slew rate of the incoming clock signal and the inut-referred noise voltage of the clock buffer according to σ τbridge σ Vin dv clock dt (3.46) σ τbridge where is the standard deviation of the clock jitter at the bridge drive nodes (this entity was called σ τ in section 3..), and σ Vin is the standard deviation of the inut-referred clock buffer noise voltage. Notice that this comonent of clock jitter ower adds to the jitter ower already existing on the incoming clock signal. dv clock dt, the inut clock signal s slew rate, is difficult to redict in ractice so a essimistic aroximation can be made by assuming that the incoming clock signal is a sinusoid at the clock frequency with aroriate amlitude and offset to alternate between the exected logic levels. dv clock dt can then be determined analytically. Under these conditions, equation 3.46 laces an uer limit on the inut-referred clock buffer noise since dv clock σ Vin σ τbridge dt (3.47) and dv clock dt is known from the assumtion given above, and σ τbridge can be selected based on its effect on A/D SNR as detailed in section 3..., the standard deviation of the inut referred noise voltage, can be calculated using standard methods of circuit analysis and should include all noise sources including thermal noise, shot noise, f noise, etc. In the resent design, thermal noise from transistor intrinsic base resistance dominates the inut-referred noise but does not resent a limit to A/D converter oeration at 0 bits of resolution and 00 Mss. The clock buffer σ Vin

214 3. Error Sources in Diode Samling Bridges 83 circuitry will be discussed in more detail in section σ Track Noise ower roduced by the track-and-hold electronics during track mode (called above) can be calculated in ordinary fashion and referred to any convenient node in the circuit for uroses of later analysis. This noise reresents erturbations which are added to the desired signal and which are samled and then held when the S/H switches into hold mode. Once in hold mode, electronic noise further erturbs the held signal so that three comonents contribute to the signal which is eventually quantized: the desired signal itself, additive noise from the circuit in track mode, and additive noise from the circuit in hold mode. Because the bias levels for many T/H circuit elements are different in track mode than in hold mode, the noise contributions during these two states are not necessarily σ Track equal. Further, since contributes at the time of the track-to-hold transition while σ Hold contributes at the quantization instant, the two sources are indeendent (assuming for simlicity white noise). Therefore, the noise ower from the two sources simly adds to the desired signal to give σ Total σ Signal σ Track + + σ Hold (3.48) If the track-mode noise and the hold-mode noise are nearly equal, the total noise ower added to the signal is twice that encountered in a continuous-time circuit. Therefore, low noise design of the T/H electronics is articularly imortant mandating use of extreme care to ensure otimum erformance. Although standard techniques of noise analysis ertain to calculation of the noise ower at any circuit node, and comuter simulation enables raid and accurate analysis of very comlicated circuits; determination of the noise in a very simle network serves as a crude but illustrative examle enlightening analysis of the T/H circuit discussed here. Such a simle network is now investigated. In a simle single-ole system consisting of a resistor driving a shunt caacitor (Fig. 3.3), the noise ower sectral density outut from the circuit is the low-ass filtered white, thermal noise ower sectral density from the resistor whose mean square is v n 4kTR df. The frequency resonse of the system is

215 84 Chater 3 Samle-and-Hold Design R V out v n 4kTR f C Figure 3.3. Single-ole RC low ass filter for analysis of kt/c noise. V out () s V in () s + src (3.49) so that the outut ower sectral density becomes V in V out + ω R C 4kTR df + ω R C (3.50) and the mean-square noise voltage at the caacitor can be found by integration: V ot V out 4kTR + ω R C df kTR + ( πfrc) df (3.5) where the subscrit ot imlies total outut noise ower as distinct from outut noise ower sectral density. By substituting x πfrc, this integration simlifies to V ot ( kt) ( Cπ) + x dx 0 kt πc + x dx 0 (3.5) which is easily solved to give kt πc kt π + x dx πc V ot 0 kt C (3.53)

216 3. Error Sources in Diode Samling Bridges 85 This equation imlies that the integrated mean-square noise voltage arising from any single-ole RC network is kt C regardless of the resistor value and bandwidth of the system. Or stated more simly, the RMS noise voltage is kt C. By generalizing the results of the above analysis, it can be shown that in any assive circuit where noise arises exclusively from thermal sources, the mean-square integrated noise voltage at any node with shunt caacitance to ground can be conservatively aroximated by kt C where C is the shunt caacitance. Although this concet does not extend in any rigorous way to active circuits, most ractical circuits exhibit noise voltages on the order of this amount. By simulation, the T/H circuits investigated here demonstrated mean-square noise voltages at the hold caacitor within a factor of about 3 of kt C H for a wide range of circuit arameters. This emirical result allows raid aroximations of circuit noise erformance during reliminary design studies. Since similar noise ower levels exist at the hold caacitor in both track and hold modes, and since these comonents arise from indeendent noise sources, the resultant contribution to the total noise from σ Track and σ Hold is twice the value quoted above; therefore, mean-square noise voltage referred to the hold node can be aroximated as σ Track + σ Hold 5kT C. The differential asect of the T/H designed here affects the noise analysis. Since two identical half-circuits comrise the T/H, kt C noise as just describes exists at each hold caacitor. These noise sources are indeendent so + Vin - Pream & Bridge Pream & Bridge C H C H + V + H - - Postam kt V nt V nt C H kt C H Figure kt/c noise at the hold caacitors. In the differential imlementation the two indeendent sources contribute to the total noise ower erturbing the held voltage, V H resulting in doubled noise ower comared to a single-ended version. Signal amlitude is also doubled, thus quadruling signal ower and increasing SNR by 3 db over the single-ended case.

217 86 Chater 3 Samle-and-Hold Design their owers add when affecting the differential held voltage, V H. Therefore, the mean-square differential noise comonent of the held voltage is V HT kt C (where the HT subscrit refers to the total integrated mean-square noise voltage at the hold node as distinct form the noise ower sectral density). In site of this increase in noise ower, the differential imlementation exhibits suerior SNR comared to a single-ended version because while the noise ower doubles as shown, the signal ower quadrules (since the signal amlitude doubles and the ower is roortional to A ). Therefore, a differential T/H circuit is caable of increased SNR by 3 decibels over a singleended version. During hold mode, base shot noise from the ostamlifier integrates on the hold caacitor, C H, giving rise to a noise voltage which adds to the held signal further degrading achievable SNR. + V Held _ V Held CH Ib Ib CH I bias I bias Figure Base shot noise integrates on the hold caacitors during the hold interval adding a noise comonent to the held voltage. The mean square of the shot noise is qi B df where q is the electron charge and I B is i n the base current flowing to the inut transistor of the ostamlifier. When integrated over the hold eriod, T S f S (where f S is the samle rate of the converter), the resultant mean-square noise voltage on the hold caacitor, C, is H σ qi B Shot C H fs (3.54). My thanks to Aaron Buchwald for deriving this result.

218 3. Error Sources in Diode Samling Bridges 87 Since the shot noise source is indeendent from the others reviously described, this noise ower adds to the total signal ower which is eventually quantized. Notice that increased hold caacitance, C H, decreases the shot noise contribution as does decreased ostamlifier inut bias current, I B. The integrated shot noise comonent decreases with increasing samle rate, f S, since the noise current sends less time integrating on the hold caacitor forming a noise voltage. Only C H and I B are arameters under designer control which affect the integrated shot noise. Therefore, these factors must be chosen judiciously to kee σ Shot accetably small Droo Inut bias current flowing to the ostamlifier during hold mode deletes the hold caacitor of charge resulting in a change in the held voltage called droo (Fig 3.35a). The held voltage varies V Held V Held Sloe / C H Ib C H Ib I bias 0 time (a) (b) Figure Postamlifier inut bias current causes droo on hold caacitor. with the ostamlifier inut current according to: dv Held () t dt I b C H (3.55) where I b is the ostamlifier inut current. If I b is constant, the held voltage changes at a fixed slew rate (Fig. 3.35b), and in a T/H circuit oerating at samle rate f S T S the voltage deviation

219 88 Chater 3 Samle-and-Hold Design during the hold eriod becomes V Held I b t C H I b C H T S (3.56) If the inut bias current, I b, is truly constant, then V Held will not vary from samle to samle, and therefore will not affect oeration of the T/H excet by adding an offset to the stream of held samles. This offset must be ket reasonably small to revent bias roblems in succeeding circuitry but does not hinder erformance in any other way. If, however, the ostamlifier inut bias current deends uon the held signal then equation 3.55 modifies to dv Held () t dt I b ( V Held () t ) C H (3.57) where I b ( V Held ) indicates the functional deendence of I b on V Held () t. For a known function, I b ( V Held ), equation 3.57 can be solved for V Held ( T S ), the held voltage at the end of the hold mode. If I b is a linear function of V Held () t, say I b αv Held () t (3.58) then V Held ( T S ) can be solved for analytically using equation 3.57: dv Held () t V Held ( T S ) V o dt dv Held () t V Held () t dv Held () t V Held () t αv Held () t C H α C H dt α C H T S ln V Held T S ( ( ) α T S ) C H V o V Held ( T S ) V o e o α T S C H dt (3.59)

220 3. Error Sources in Diode Samling Bridges 89 The last line of equation 3.59 indicates that the held voltage at the end of hold mode, V Held ( T S ), equals the initial held voltage, V o, multilied by a constant factor, ex( αt S C H ). Therefore, when I b is a linear function of V Held, the effect of droo is to attenuate the stream of samled signals from the T/H without introducing any distortion. In general, however, deendency of I b on V Held causes distortion at the T/H outut because signals of different amlitudes exerience different deviations during hold mode. This otential error source can be mitigated by ensuring that I b is small enough and C H is large enough that any distortion resulting from droo is accetably small. Mandating low ostamlifier inut bias current, I b, and large hold caacitance, C H, as just suggested reduces droo-induced distortion but ossibly at the exense of increased settling time of the ostamlifier due to its low bias current, and at the exense of increased track-mode distortion because of the increased dynamic load on the reamlifier. Alternatively, the natural common-mode rejection of a differential imlementation can be used advantageously to eliminate most effects of the droo henomenon. In a differential realization of the T/H, both held voltages will exerience nominally equal droo so that the resulting differential signal is largely (if not totally) indeendent of ostamlifier inut bias current (Fig. 3.36). Since each side of the differential circuit still + V Held - V Held C H Ib Ib C H I bias I bias + V Held (a) sloe I b / C H Voltage _ V Held sloe I b / C H sloe ~ 0 _ + _ V Held V Held Time (b) Figure A differential T/H imlementation largely cancels droo effects.

221 90 Chater 3 Samle-and-Hold Design exeriences a voltage dro during the hold mode equal to aroximately I b T S C H care must be taken to ensure that bias levels of succeeding circuitry remain suitable. Cancellation of droo effects relies uon I b I b in figure Otherwise, a residual differential droo signal will erturb the held signal according to V Held + V Held V Held I b I b C H ( ) T S (3.60) If the current difference I b I b is constant, then (as in the single-ended case with constant I b ) V Held will not vary from samle to samle but will merely add a fixed offset to each samle of the outut data stream. Likewise, if I b I b varies linearly with V Held, then attenuation of the samled data stream results. Again, as in the single-ended case, distortion arises when I b I b is a nonlinear function of V Held. The chief advantage of the differential imlementation regarding droo behavior is that I b I b is usually quite small so that the slew rate of the differential outut from the ostamlifier is near zero. In contrast, the ostamlifier can traverse many A/D LSBs during the hold mode if a single-ended circuit T/H is used Thermal Distortion Power dissiated in an integrated circuit induces temerature gradients across the surface of the silicon chi. These gradients in turn affect device oeration because the underlying semiconductor hysics follow either Fermi-Dirac or Maxwell-Boltzmann distributions both of which deend exonentially on temerature. Such temerature deendence is exhibited by, among other things, I S, the saturation current of a n junction, and V T, the thermal voltage equal to kt q. These two deendencies combine to determine the temerature coefficient of the n junction TC VBE otential under constant current conditions,, which is well known to be aroximately mv/ C. This extreme sensitivity of the biolar transistor s oerating characteristic frequently degrades circuit oeration by causing unwanted erturbations in base-emitter otentials when temerature gradients exist. For examle, thermal effects can induce offsets in comarators when one transistor of the inut differential air oerates at a different temerature than the comlementary transistor. This temerature difference can be caused by ower dissiation within the comarator itself which, in turn, deends uon the inut signal to the circuit. Since dynamic thermal behavior in silicon exhibits natural frequencies in the audio range, signal-deendent

222 3. Error Sources in Diode Samling Bridges 9 thermal gradients result in unwanted comarator hysteresis [34], [35]. To quantify the magnitude of electro-thermal interaction, the thermal resistance from a device s junction to the substrate, θ js, must be known. θ js can be calculated by solving the steadystate thermal diffusion equation for a device of given geometry and ower dissiation [36],[37]. When erformed for a minimum-size SHPi transistor with a µm X8µm emitter area not located near any adiabatic edges and dissiating mw in a 50 µm thick substrate, such analysis yields a temerature contour exhibiting a C temerature rise from the substrate to the emitter center (Fig. 3.37). Therefore, for a minimum-size SHPi device, θ js C mw. The contour Temerature Rise (C) y axis (microns) x axis (microns) 0 Figure Thermal contour of minimum-size SHPi device ( µm X 8 µm emitter area) dissiating mw on a 50 µm thick substrate. of figure 3.37 also indicates that temerature erturbations of the substrate are localized to an area a few times larger than the emitter itself, indicating that modest ower dissiated in one device will only marginally increase the temerature of adjacent devices. For comarison, a large device with a 75 µm X75µm emitter area dissiating 00 mw also in a 50 µm thick substrate shows an increase in emitter temerature of aroximately 0 C although the ower density is only about

223 9 Chater 3 Samle-and-Hold Design half of that in the revious case (Fig. 3.38). θ js for this device is therefore 0. C/mW. Again, 0 Temerature Rise (C) y axis (mm) x axis (mm) Figure Thermal contour of large device (75 µm X75 µm emitter area) dissiating 00 mw. significant temerature changes are limited to an area a few times larger than the emitter region. Note that although the area of the larger device is 350 times that of the minimum device, its thermal resistance to the substrate, θ js, is only 0 times lower. Nonetheless, when high ower dissiation is required, larger devices are necessary for their lower thermal resistance. Electro-thermal interaction gives rise to distortion when an electrical inut signal modulates device ower. The ower modulation induces temerature fluctuations within the device resulting in electrical erturbations which distort the original signal. This henomenon, called thermal distortion, is articularly troublesome in recision circuits where even small deviations from ideal erformance are unaccetable. The T/H circuit under consideration reresents such a recision circuit, and even a simle emitter follower buffer comrising the reamlifier and/or ostamlifier is suscetible to excessive thermal distortion. Emitter follower device ower is determined exclusively by the inut voltage since the bias current is ideally constant (Fig. 3.39). Power dissiation in a transistor can be exressed by

224 3. Error Sources in Diode Samling Bridges 93 V CC V in P D I c V ce + I b V be V out I Bias Figure Emitter follower buffer. P D I c V ce + I b V be I c V ce (3.6) where the aroximation assumes I c» I b. In an emitter follower such as deicted in figure 3.39 the ower dissiation becomes P D I Bias ( V CC V out ) I Bias [ V CC ( V in V be )] (3.6) If the inut voltage, V in, changes to a new value, V in + V in, then the ower dissiation will change corresondingly to P D + P D I Bias { V CC [ ( V in + V in ) V be ]} (3.63) where any changes in V be are assumed to be negligible. Subtracting equation 3.6 from equation 3.63 gives the change in ower, P D, as a function of the change in inut voltage, V in : P D I Bias V in (3.64) This change in the emitter follower ower dissiation will cause a change in the base-emitter junction temerature which will in turn cause a change in V be. The change in V be can be determined from the device thermal resistance, θ js, and the temerature coefficient of the n TC VBE junction otential,. V be TC VBE θ js P D (3.65) By substituting the exression in equation 3.64 for P D the incremental base-emitter voltage as

225 94 Chater 3 Samle-and-Hold Design a function of the incremental inut voltage results: V be V be V in TC V θ BE js I Bias V in TC V θ BE js I Bias (3.66) Since V be is an error term caused when V in is alied to the T/H, and since this error term must be small comared to a quantization ste, Q, of the following quantizer, the ratio V be V in must smaller than N. This laces an uer bound on the emitter follower bias current before thermal distortion leads to errors larger than one quantization ste. V be V in < N TC V θ BE js I Bias < N I Bias N < TC V θ BE js I Bias < N TC VBE θ js (3.67) The last line of equation 3.67 reresents a severe limitation on bias current for emitter followers in high-resolution circuits. For examle, in the T/H under consideration with N 0, TC VBE mv C, and θ js C mw, bias current is limited to I Bias < N TC VBE θ js ( 0 ) mv ( ) C C ( ) mw 50 µa (3.68) This low value of bias current can be roblematic when driving caacitive loads because both bandwidth and dynamic linearity degrade with reduced bias (as exlained in section 3..3). Therefore, simly selecting low bias levels is not a viable method for reducing thermal distortion to accetable levels. Rather, techniques must be emloyed to enable oeration at higher bias levels without thermal distortion effects. Circuits based on negative feedback can achieve insensitivity to thermal gradients, but this method is rejected for the resent alication because oen-loo

226 3.3 Track-and-Hold Design 95 imlementations offer otentially higher-seed oeration. Instead, aroaches are utilized which maintain constant ower dissiation in ertinent devices indeendent of signal level, or which constrain signal-deendent ower to be matched between comlementary devices in differential imlementations [38]. Both of these techniques have been used in the T/H circuit and will be described in detail. 3.3 Track-and-Hold Design Sections 3. and 3. discussed oeration and limitations of diode-bridge track-and-hold circuits from a general ersective. This section describes in detail the secific circuits imlemented during this roject to realize a 0-bit 00 Mss A/D converter with on-chi T/H. Two such circuits are required in the feedforward architecture used: the first, the inut T/H, tracks the 50 MHz inut signal with adequate dynamic linearity to assure 0-bit oeration at 00 Mss while the second, the interstage T/H, is required for ielined oeration of the A/D converter and requires only linearity consistent with 7-bit quantization but must also oerate at 00 Mss Preamlifier and Samling Bridge The inut T/H circuit is based uon a diode-bridge with a differential air current switch and resistive loads. Both the reamlifier and ostamlifier are based uon emitter followers to achieve a simle design with high-seed erformance and good linearity (Fig. 3.40). This circuit suffers from several drawbacks which were discussed in section 3. and which can be at least artially alleviated by resorting to a differential imlementation. Additional circuit modifications are required to overcome other shortcomings. The imortant error sources afflicting the T/H of figure 3.40 include: Track mode distortion due to dynamic load current flowing through the inut emitter follower and diode-bridge and into load caacitor C L (these effects are analyzed in sections 3..3 and 3..4) Track mode distortion caused by finite load imedances, R L, as described in section 3..4 Thermal distortion resulting from signal-deendent ower modulation in the reamlifier and ostamlifier (section 3..0)

227 96 Chater 3 Samle-and-Hold Design R L R L Vin Vout C H Hold Track Figure A single-ended T/H circuit based on a diode-bridge with emitter follower reamlifier, differential air current switch with resistive loads, and emitter follower ostamlifier. Excessive droo caused by ostamlifier bias current discharging the hold caacitor (section 3..9) Exacerbated hold edestal error which arises because the bridge center-ta node is not centered at the same voltage as the inut signal. The inut source is assumed to be ground-centered with 50 Ω imedance. (See section 3..6.) The differential circuit imlemented to mitigate these errors (Fig. 3.4) includes two identical diode-bridge switches driven by a common clock buffer, two hold caacitors connected to ground, a differential ostamlifier, and a comensation network between the comlementary inut emitter followers to decrease both static and dynamic track-mode linearity. The differential nature of the circuit naturally cancels even-order error terms including even-order distortion comonents and droo. Additionally, the SNR of this aroach is imroved over the single-ended version because while the noise ower is doubled, so is the signal amlitude resulting in quadruled signal ower. Aside from these advantages which accrue for all differential circuits, the available comlementary

228 3.3 Track-and-Hold Design 97 Vin + Inut Buffer X Diode Bridge Switch Comensation Network Track Hold Clock Buffer + - Vout Differential Postamlifier - Vin X Inut Buffer Diode Bridge Switch Figure 3.4. A differential track-and-hold imlementation with linearity comensation. signals can be used judiciously to cancel some mechanisms of distortion. The technique used here (Fig. 3.4) reduces track mode distortion by injecting a comensation current at the emitters of the two main emitter followers. This comensation current is generated by a transconductance cell comrising a degenerated differential air whose inuts are develoed by an auxiliary air of emitter followers. The outut of each auxiliary emitter follower drives the comlementary inut of the transconductance cell so that the effective olarity of transconductance is inverted. The magnitude of the transconductance is determined by the cell s degeneration resistance, R E, which is set equal to the diode-bridge load resistors, R L. By selecting this olarity and value of transconductance, signal current is injected into the inut node of the bridge exactly equal to that required to flow through the arallel combination of the two bridge load resistors, R L, in resonse to the inut signal. This arrangement therefore cancels the static signal current flowing from the main emitter follower eliminating its signal-deendent V be modulation and hence its static distortion. Dynamic distortion caused by signal current flowing from the main emitter followers into the hold caacitors is also reduced with this mechanism by connecting a shunt caacitor around the transconductance s degeneration resistor. The value of this caacitance should nominally equal one half the hold caacitance, but the actual value, determined emirically via simulation, is

229 98 Chater 3 Samle-and-Hold Design R L R L R L R L Vin+ A4 To Postamlifier A4 Vin- Vout+ Vout- Hold Track Track Hold.5 ma.5 ma RE 00 ua 800 ua 800 ua 00 ua Figure 3.4. Differential reamlifier and bridge with comensation. somewhat different to otimally cancel not only dynamic distortion from the main emitter follower, but from other dynamic effects within the bridge as well. Because the bias and signal currents flowing through the bridges are unaffected by this scheme, distortion arising from current modulation in the bridge diodes (both static and dynamic) is not eliminated. These distortion sources are analyzed in section 3..4, and along with finite aerture time remain as the dominant error sources in the T/H. In addition to generating the inut signals for the comensating transconductance cell, the auxiliary emitter followers feed a level-shifted signal to the base of a bootstra device which maintains a constant V ce across the main emitter followers indeendent of the inut signal level. This method eliminates thermal distortion in the inut devices. To reduce thermal noise which is dominated by intrinsic base resistance in the main emitter followers, these devices are selected to be 4 times the minimum device size, thus reducing the contribution of these noise sources by a like factor. The center-ta nodes of the comlementary bridges are biased at one diode dro below ground otential. This voltage dro matches that of the inut emitter followers so that the centerta nodes are biased at the common-mode voltage of the differential inut signal. The reamlifiers consisting of main and auxiliary emitter followers, the comlementary diode-bridges, the transconductance cell, and the two hold caacitors are laid out in symmetric fashion occuying an area of aroximately 600 µm 500µm(Fig. 3.43).

230 3.3 Track-and-Hold Design Postamlifier Design The urose of the ostamlifier is to rovide high inut imedance with low bias current to revent leakage of charge from the hold caacitor during hold mode. In addition, an ideal ostamlifier should exhibit low outut imedance for driving caacitive loads with low distortion and short settling time. Of course, low ower dissiation, and low-noise oeration are desirable as for any analog comonent. In some instances, the ostamlifier also rovides voltage gain, but the first T/H in the resent A/D converter does not require gain greater than unity (the voltage gain of the ostamlifier in the second T/H from this design is however). A rototye ostamlifier fulfilling all of the above characteristics derives from an ideal oerational amlifier (o-am) configured as a voltage follower (Fig. 3.44a). This circuit rovides infinite inut imedance, unity gain, and zero outut imedance, but is unrealizable in ractice. A simle but crude aroximation to this ideal relies on a resistively loaded differential air to form a basic one-stage o-am (Fig. Figure Layout of differential reamlifier and diode bridge with feedforward comensation. xsam Size: 59 x 480 microns

231 00 Chater 3 Samle-and-Hold Design RL Vcc Vin Vout Vin Vout I bias (a) (b) Auxiliary Amlifier X RL Level Shift RL RL Vin Vout Vout- Vin+ RE Vin- Vout+ I bias (c) (d) Figure Postamlifier imlementations. (a) An oerational amlifier connected as a voltage follower. (b) A differential air configured as a voltage follower. (c) A differential air-based follower with enhanced erformance. (d) An oen-loo unity-gain ostamlifier with linearity comensation. 3.44b). The chief limitation of this aroach is the relatively low gain achievable with resistive loading which is exressed by I C A V g m R L R V L T V RL V T (3.69) where V RL is the bias voltage across load resistor R L. Since a 5 Volt ower suly is used, V RL is limited to about.5 Volts so that the maximum gain is A V V RL.5V 00 5mV V T (3.70)

232 3.3 Track-and-Hold Design 0 With oen-loo gain of 00, the follower s closed-loo gain is only aroximately 0.99, and the imrovements from feedback in inut and outut imedance are modest. The effective resistance, R L, can be increased, and the amlifier gain imroved roortionately, if the to node of the load resistor is driven by a level-shifted relica of the outut voltage rather than connected to the ositive ower suly (Fig. 3.44c). In this arrangement, a constant bias equal to the level-shift voltage is maintained across R L thus resenting an infinite imedance to the differential air. Higher oenloo gain and imroved closed-loo erformance result. If the gain of the auxiliary amlifier in figure 3.44c is α rather than, the effective imedance looking into the load resistor is R L α and the oen-loo gain becomes A V I C V RL R L R L g m α V T α αv T V LS αv T (3.7) where V LS is the value of the level-shifting voltage. Therefore, even with a non-ideal bootstra amlifier significant imrovements in gain can be achieved. A suitable circuit for roviding the level-shifting and near-unity gain necessary in figure 3.44c is shown in figure 3.44d. This buffer amlifier relies on a degenerated differential air with resistive loads to attain voltage gain near unity, and emloys diode-connected transistors in its loads to enhance linearity. The load diodes imrove linearity by eliminating the deendence of amlifier gain uon transistor transconductance of the degenerated differential air is g m. The G m g m + g m ( R E ) ( R E ) + g m (3.7) where R E aears instead of R E because differential half-circuit is used for calculating the gain. The load imedance seen in figure 3.44d is Z L R L + g m (3.73) so that the amlifier gain becomes A V R L + g m G m Z L ( R E ) + g m (3.74)

233 0 Chater 3 Samle-and-Hold Design If R L R E then the gain exression simlifies to ( R E ) + g m A V ( R E ) + g m (3.75) Since the voltage gain, A V, is indeendent of g m, distortion-free oeration results. Finite transistor β reduces the actual gain of this amlifier to slightly less than unity for two reasons. First, β losses reduce the G m given above by the factor β ( β + ), and second, g m of the load diodes is lower than that of the differential air transistors by the same factor, β ( β+ ), since the collector current of the differential air devices equals the emitter current of the diode-connected load transistors. Equation 3.75 indicates that the buffer amlifier voltage gain is negative, however, since the realization is fully differential, either inverting or non-inverting oeration is easily obtainable. This differential auxiliary buffer is combined with two comlementary followers from figure 3.44c to form the T/H ostamlifier (Fig. 3.45). In this imlementation, each of the transistors Vcc Vin+ A4 A4 A4 A4 Vin- + Vout - Figure Differential ostamlifier imlementation. comrising the o-am followers is increased in area to reduce thermal noise from intrinsic base resistance. Additionally, the high gain achieved with the bootstraing technique will increase the

234 3.3 Track-and-Hold Design 03 inut imedance and decrease the outut imedance significantly. Each transistor in the o-am differential airs exeriences constant so thermal distortion is eliminated (any residual thermal effects are further reduced because of the closed-loo nature of the amlifier). The ostamlifier layout is symmetrical; is itch aligned with the reamlifier and bridge circuits; and occuies an area of (Fig. 3.46) Clock Buffer The clock buffer circuit rovides suitable gain and level-shifting to accet a standard Figure Layout of differential ostamlifier with feedback bootstraing. V ce 300 µm 500 µm

235 04 Chater 3 Samle-and-Hold Design emitter-couled-logic (ECL) inut signal and drive the differential air switches which control the comlementary diode-bridge. The buffer must erform this function while adding minimal noise to the incoming clock signal (as discussed in sections 3.. and 3..8) and while dissiating minimal ower. The imlementation used for this roject (Fig. 3.47) incororates inut emitter followers to + Vin - -V Vout + - Vref Figure Clock buffer schematic diagram. rovide high inut imedance and level-shifting, a resistively loaded differential air to rovide gain and common-mode rejection, and emitter follower outut buffers to rovide low outut imedance. Two series connected diodes ensure the correct common-mode bias voltage at the outut of the differential air where on-chi caacitors filter broadband noise and revent ringing of the outut emitter followers when driving caacitive loads. The inut emitter followers are 4 times larger than minimum devices to reduce their base resistance associated thermal noise which roves to be the dominant noise source in this amlifier. The clock buffer is itch-aligned with the

236 3.3 Track-and-Hold Design 05 rest of the T/H circuitry and occuies an area of (Fig. 3.48) Design Summary The differential reamlifier, comlementary bridges, and differential ostamlifier combine to form the T/H circuit used for this A/D converter (Fig. 3.49) which oerates from +5 V and 5 V sulies dissiating aroximately 00 mw. (The clock buffer and bias generation circuitry are not included in figure 3.49 for simlicity but are included in the 00 mw ower figure.) The two hold caacitors are F metal-oxide-semiconductor (MOS) structures which occuy around 0% of the T/H area which is (Fig. 3.50). The full-scale inut signal Figure Layout of first track-and-hold clock buffer circuit. 0 µm 45 µm ckbuf Size: 0 x 44 microns 00 µm 500 µm

237 06 Chater 3 Samle-and-Hold Design to the T/H is designed to have 5 mv differential amlitude. Alternatively, the full-scale range can be secified as.04 V differential. Simulations indicate that for a full-scale sinusoidal inut at a frequency near 50 MHz and samled at 00 Mss, the sectrum of the outut samle stream contains harmonics which are over 80 db below the fundamental frequency (Fig. 3.5). The rominent odd-order harmonic is the 3rd, located at 85.7 dbc, while the odd-order total harmonic distortion (THD) is 84.4 db. These figures aroach the ideal distortion level of a 0-bit quantizer which is. Because the differential architecture of the T/H rejects all even-order distortion roducts, only odd comonents aear in the differential outut sectrum. Anticiating imerfect cancellation of even-order comonents due to mismatches in the T/H comonents, the single-ended outut sectrum was also investigated. The worst-case even-order harmonic in the Figure Comlete track-and-hold circuit (with ostamlifier shaded). The clock buffer has not been drawn for simlicity. Figure Layout of first track-and-hold circuit. V in + V out V in th Size: 3 x 480 microns 9N 90dBc

238 3.4 Interstage Track and Hold Design Relative Amlitude (dbc) Harmonic Figure 3.5. Simulated T/H outut sectrum. Fs00 Mss, Fin43.75 MHz. single-ended sectrum is the nd at 67 dbc. This distortion roduct, along with all other evenorder comonents, will be attenuated significantly by the common-mode rejection of the succeeding circuits within the A/D so that the overall distortion erformance of the T/H is accetable for alication in a 0-bit converter. 3.4 Interstage Track and Hold Design The second (or interstage) track-and-hold circuit receives a signal from the residue amlifier in the A/D converter which must be quantized with 7-bit resolution. As in the first T/H, oeration at 00 Mss is required, but the inut to the second T/H is not a dynamically changing signal. Rather, the inut here is a signal which stes raidly at the hold-to-track transition (as the reconstruction DAC switches to its new state) and then settles slowly during track mode. Therefore, good dynamic linearity in track mode is unnecessary and only static linearity consistent with 7-bit quantization (imlying SFDR 9N 63dBc ) is required. Unlike the inut T/H, gain accuracy is critical in the interstage T/H and its design is modified accordingly. The interstage T/H is modelled after the inut T/H with slight modification as indicated in figure 3.5. This block diagram indicates that the interstage T/H is identical to the inut T/H with the addition of two feedback amlifiers from the two outut nodes to the bridge center-ta nodes.

239 08 Chater 3 Samle-and-Hold Design Feedback Amlifier X Vin + Inut Buffer X Diode Bridge Switch Comensation Network Track Hold Clock Buffer + - Differential Postamlifier Vout - Vin X Inut Buffer Diode Bridge Switch X Feedback Amlifier Figure 3.5. Second stage track-and-hold block diagram with feedback to bridge center-ta nodes to reduce gain-loss due to hold edestal error. These amlifiers reduce hold edestal error which would otherwise cause unaccetable gain loss (see section 3..6). The feedback amlifiers are simle, one-stage o-ams configured as voltage followers like that deicted in figure 3.44b. When connected between bridge outut and center-ta node (Fig 3.53), these buffers significantly reduce the deleterious effects of hold edestal. The layout of the interstage T/H is symmetrical and occuies an area equal to (Fig. 3.54). 00 µm 500 µm The ostamlifier of the interstage T/H must resent a high imedance to the hold caacitors to revent excessive droo, and must rovide voltage gain of in order for the amlitude of the residue signal to correctly align with the full-scale voltage of the fine quantizer. This gain

240 3.4 Interstage Track and Hold Design 09 must be accurate to within about % to revent missing codes in the A/D transfer function. The Figure Second track-and-hold with bootstraed center-ta. Figure Layout of second T/H. Hold Track Vout Vin C H xsam Size: 6 x 556 microns

241 0 Chater 3 Samle-and-Hold Design circuit imlemented here resembles that described in section 3.3. and shown in figure 3.44d with the excetion that the load imedances are doubled to achieve the increased gain necessary (Fig. 3.55). In this circuit, the outut common-mode voltage is set by a diode reference string (D-D3) Vcc D3 Qull-u D QlA QlB D QlA QlB Rl Vin- +Vout- Rl Vin+ Ree Figure Interstage ostamlifier schematic which rovides high inut imedance and voltage gain of. Outut emitter followers are not shown for simlicity. which sulies the bias voltage for the base of an emitter follower ull-u device (Qull-u). Using this method, the outut common-mode voltage becomes V cm V D + V D + V D3 V Qull u I Bias R L V QlA V QlA I Bias R L (3.76)

242 3.4 Interstage Track and Hold Design where the last line of equation 3.76 assumes all V BE dros are equal. Since this bias voltage is indeendent of V BE, it is also indeendent of the concomitant reliance on temerature. The gain of the second ostamlifier is A V G m Z L + g m g m + R ee R ee ( + + R g mqla g L ) mqla ( + R g L ) m (3.77) If R ee R L, then this exression reduces to A V + g m g m + R ee R L ( + R g L ) m ( + R g L ) m (3.78) Since the gain is indeendent of g m and hence transistor oerating oint, the amlifier should be distortion-free. Mismatches in comonents will degrade erformance from this ideal, but oeration with linearity aroriate for 7-bit quantization ( SFDR 9N dB ) is achievable. The interstage ostamlifier layout is symmetrical and occuies an area equal to 5 µm 300µm (Fig. 3.56). A relica of the interstage T/H circuit facilitates matching the A/D converter residue fullscale amlitude to the fine quantizer full-scale amlitude. This relica circuit is identical to the interstage T/H but scaled down to reduce ower dissiation. Also, the relica circuit is locked in track mode, so the bridge switch circuitry is eliminated. The entire interstage T/H along with its relica, the clock buffer, and the bias circuitry occuy an area equal to 750 µm 000 µm (Fig. 3.57).

243 Chater 3 Samle-and-Hold Design References [] B. Gilbert, Translinear circuits: A roosed classification, Electronics Letters, vol.,. 4 6, Jan [] B. Gilbert, A recise four-quadrant multilier with subnanosecond resonse, IEEE Journal of Solid State Circuits, vol. SC-3, , Dec [3] B. Gilbert, A new wide-band amlifier technique, IEEE Journal of Solid State Circuits, Figure Second T/H ostamlifier. shst Size: 4 x 85 microns

244 3.4 Interstage Track and Hold Design 3 vol. SC-3, , Dec [4] E. Seevinck, Synthesis of nonlinear circuits based on the translinear rincile, in International Symosium on Circuits and Systems, , IEEE, 983. [5] E. Seevinck, Analysis and Synthesis of Translinear Integrated Circuits. Elsevier, 988. [6] J. R. Gray and S. C. Kitsooulos, A recision samle and hold circuit with subnanosecond switching, IEEE Transactions on Circuit Theory, vol. CT-, , Set [7] I. Dostis, Evaluation of the nonlinear distortion caused by the finite turn-off time of a Samle-and-Hold-Circuit for high-seed PCM, IEEE Transactions on Circuit Theory, vol. CT-3, , Mar [8] G. Erdi and P. R. Henneuse, A recision FET-Less Samle-and-Hold with high Chargeto-Droo current ratio, IEEE Journal of Solid State Circuits, vol. SC-3, , Dec [9] B. Astegher, A. Lechner, and H. Jessner, A novel All-NPN samle and hold circuit, in 5th Euroean Solid-State Circuits Conference Digest of Technical Paers,. 88 9, IEEE, 989. [0] A. J. Metz, Samling bridge. U.S. Patent Number 4,659,945, Ar [] K. Tanaka, F. Ishikawa, K. Abe, and K. Koma, A 40MS/s monolithic S/H IC, in Interna- Figure Second T/H with relica. th Size: 74 x 98 microns

245 4 Chater 3 Samle-and-Hold Design tional Solid State Circuits Conference,. 90 9, IEEE, Feb [] M. J. Chambers and L. F. Linder, A recision monolithic Samle-And-Hold for video Analog-to-Digital converters, in International Solid State Circuits Conference, , IEEE, Feb. 99. [3] G. M. Gorman, J. B. Camou, A. K. Oki, B. K. Oyama, and M. E. Kim, High erformance samle-and-hold imlemented with GaAs/AlGaAs heterojunction biolar transistor technology, in International Electron Device Meeting, , IEEE, Dec [4] K. Poulton, J. S. Kang, J. J. Corcoran, K.-C. Wang, P. M. Asbeck, M.-C. F. Chang, and G. Sullivan, A Gs/s HBT samle and hold, in GaAs IC Symosium,. 99 0, IEEE, 988. [5] J. Corcoran, K. Poulton, and T. Hornak, A GHz 6b ADC system, in International Solid State Circuits Conference,. 0 03, IEEE, Feb [6] K. Poulton, J. J. Corcoran, and T. Hornak, A -GHz 6-bit ADC system, IEEE Journal of Solid State Circuits, vol. SC-, , Dec [7] B. Wong and K. Fawcett, A recision dual bridge GaAs samle and hold, in GaAs IC Symosium, , IEEE, 987. [8] F. Thomas, F. Debrie, M. Gloanec, M. L. Paih, P. Martin, T. Nguyen, S. Ruggeri, and J.- M. Uro, -GHz GaAs ADC building blocks, IEEE Journal of Solid State Circuits, vol. SC-4,. 3 8, Ar [9] K. R. Stafford, P. R. Gray, and R. A. Blanchard, A comlete monolithic Samle/Hold amlifier, IEEE Journal of Solid State Circuits, vol. SC-9, , Dec [0] P. J. Lim and B. A. Wooley, A high-seed samle-and-hold technique using a miller hold caacitance, IEEE Journal of Solid State Circuits, vol. SC-6, , Ar. 99. [] M. Nayebi, A 0-bit video BiCMOS track-and-hold amlifier, IEEE Journal of Solid State Circuits, vol. SC-4, , Dec [] P. Real and D. Mercer, A 4b linear, 50ns samle-and-hold subsystem with self- correction, in International Solid State Circuits Conference, , IEEE, Feb. 99. [3] P. Real, D. H. Robertson, C. W. Mangelsdorf, and T. L. Tewksbury, A wide-band 0-b 0-Ms/s ielined ADC using current-mode signals, IEEE Journal of Solid State Circuits, vol. SC-6, , Aug. 99. [4] F. Moraveji, A 4b, 50ns samle-and-hold amlifier with low hold ste, in International Solid State Circuits Conference, , IEEE, Feb. 99. [5] F. Moraveji, A high-seed current-multilexed samle-and-hold amlifier with low hold ste, IEEE Journal of Solid State Circuits, vol. SC-6, , Dec. 99. [6] R. J. van de Plassche and H. J. Schouwennars, A monolithic S/H amlifier for digital audio, in International Solid State Circuits Conference,. 80 8, IEEE, Feb [7] R. J. van de Plassche and H. J. Schouwennars, A monolithic high-seed samle-and-hold amlifier for digital audio, IEEE Journal of Solid State Circuits, vol. SC-8,. 76 7, Dec [8] R. Petschacher, B. Zojer, B. Astegher, H. Jessner, and A. Lechner, A 0-b 75-MSPS subranging A/D converter with integrated samle and hold, IEEE Journal of Solid State Cir-

246 3.4 Interstage Track and Hold Design 5 cuits, vol. SC-5, , Dec [9] P. H. Saul, A GaAs MESFET samle and hold switch, IEEE Journal of Solid State Circuits, vol. SC-5,. 8 85, June 980. [30] R. Bayruns, N. Scheinberg, and R. Goyal, An 8ns monolithic GaAs samle and hold amlifier, in International Solid State Circuits Conference,. 4 43, IEEE, Feb [3] D. R. Martin and D. J. Secor, High seed analog to digital converters in communication systems: Terminology, architecture, theory, and erformance, tech. re., TRW Electronic Systems Grou, Redondo Beach, CA, Nov. 98. [3] T. Wakimoto, Y. Akazawa, and S. Konaka, Si biolar -GHz 6 bit flash A/D conversion LSI, IEEE Journal of Solid State Circuits, vol. SC-3, , Dec [33] M. Shinagawa, Y. Akazawa, and T. Wakimoto, Jitter analysis of high-seed samling systems, IEEE Journal of Solid State Circuits, vol. SC-5,. 0 4, Feb [34] K.-C. Wang, P. M. Asbeck, M.-C. F. Chang, D. L. Miller, G. J. Sullivan, J. J. Corcoran, and T. Hornak, Heating effects on the accuracy of HBT voltage comarators, IEEE Transactions on Electron Devices, vol. ED-34, , Aug [35] K. Poulton, K. L. Knudsen, J. J. Corcoran, K.-C. Wang, R. L. Pierson, R. B. Nubling, and M.-C. F. Chang, Thermal design and simulation of biolar integrated circuits, IEEE Journal of Solid State Circuits, vol. SC-7, , Oct. 99. [36] R. C. Joy and E. S. Schlig, Thermal roerties of very fast transistors, IEEE Transactions on Electron Devices, vol. ED-7, , Aug [37] R. D. Lindsted and R. J. Surtry, Steady state junction temeratures of semiconductor chis, IEEE Transactions on Electron Devices, vol. ED-9,. 4 44, Jan. 97. [38] T. C. Hill, III, Differential amlifier with dynamic thermal balancing. U.S. Patent Number 4,58,56, July 985.

247 6 Chater 3 Samle-and-Hold Design

248 Chater 4 Coarse Quantizer 4. 4-Bit Flash Quantizer The toology of the coarse quantizer is based uon a flash converter (Fig. 4.) with several modifications to imrove erformance and reduce ower dissiation. The basic flash A/D converter architecture is well-suited for low resolution alications such as the 4-bit coarse quantizer envisioned here, but does exhibit some characteristics which hinder erformance of the 0-bit A/D converter including: high inut caacitance, threshold erturbations due to comarator inut current flowing through the resistive reference ladder, and high ower dissiation. These drawbacks are alleviated through two techniques, use of a differential reference ladder imlementation and interolation between comarator re-amlifiers. These methods are detailed in the next two subsections. 4.. Differential Reference Ladder In a tyical flash A/D converter such as that deicted in figure 4. inut bias current flows into each comarator of the array. This current flows through the resistive ladder thereby causing voltage fluctuations which erturb the nominally equally-saced reference voltages from their ideal ositions []. This well-known effect is called reference bowing because the reference voltages vary from their ideal ositions according to a arabolic or bowed attern. A reference generation

249 8 Chater 4 Coarse Quantizer +Vref Vin Encoding N-bit Digital Outut Logic -Vref N - Comarators Thermometer Code Figure 4.. Flash or arallel A/D converter toology. scheme which simultaneously eliminates the reference bowing roblem and rovides buffering to reduce the caacitive loading resented by the comarator array relies on a differential signal being alied to differential emitter followers with resistive loads (Fig. 4.) [3]. Here, the emitter followers rovide buffering, however, the nodes at the bottom of the resistive ladders must be charged through the full ladder resistance. The distributed nature of this loading laces a ractical uer limit on the number of comarators which can be driven in this manner; however for the low resolution coarse quantizer, this settling time is adequate. Temorarily ignoring comarator bias currents, the kth comarator threshold occurs when its differential inut is zero which imlies that V k V N k (4.)

250 4. 4-Bit Flash Quantizer 9 V in Q I Ladder V N + - C 0 V 0 R Ta V N + - C V R Ta V N + - C V V + - C N V N R Ta V + - C N V N I Ladder R Ta V N V 0 Q + - V in C N Figure 4.. Differential reference ladder with comarators. The node voltages V k and V N k can be defined in terms of the inut voltage and the voltage dros across the resistive ladder: V in V BE kv Ta V in V BE ( N k)v Ta (4.) where V Ta is defined by V Ta I Ladder R. If V BE V BE, then equation 4. simlifies to V in kv Ta ( N k)v Ta V in ( k N)V Ta V in ( k N )V Ta (4.3)

251 0 Chater 4 Coarse Quantizer The last line of equation 4.3 indicates that the value of V in at which the inut to the kth comarator equals zero is linearly roortional to k as desired. To take into account the effects of comarator inut currents, consider the case if the comarator inut is a differential air. Then bias current flows only into the comarator terminal with the higher alied otential excet when both terminals are at nearly the same voltage in which case the inut bias current divides equally between the two terminals. This situation is deicted in figure 4.3 where the kth comarator s inuts are assumed V in Q Q V in V 0 I b I b V 0 V I b I b V V I b I b V V k I b I b V k V k I b I b V k V k+ V k + V N V N R Ta R Ta V N V N R Ta R Ta V N V N I Ladder I Ladder Figure 4.3. currents. Differential reference ladder showing comarator inut bias to be balanced, and the base currents are labelled accordingly. The effective threshold voltage for

252 4. 4-Bit Flash Quantizer the kth comarator can be determined by again writing the equation which defines that threshold: V k V N k (4.4) which can be exanded in terms of the ladder variables and the comarator inut bias current to give k V in V BE kv Ta R Ta I b ( k + ) N k V V in BE ( N k)v Ta R Ta I b ( N k + ) (4.5) If V BE is again assumed to equal V BE, then equation 4.5 becomes k V in ( k N)V Ta + R Ta I b V in ( N k) N R Ta I b ( k )V Ta + ( k N + Nk k ) 4 N NR Ta I b N ( k ) V Ta + ( k ) N NR Ta I b ( k ) ( V Ta + ) (4.6) The last line of this equation imlies that the inut voltage which defines the kth threshold increases linearly with k. The only difference between this result and that found for the simlified case with no comarator currents (Eq. 4.3) is that the roortionality constant changed from V Ta to V Ta + NR Ta I b. This fact imlies that in the differential ladder scheme resented, comarator inut currents do not affect threshold linearity but merely increase the uniform sacing between thresholds by the quantity NR Ta I b. The symmetry of the differential scheme can be better areciated as deicted in figure 4.4 where the comarators ta diametrically oosed oints along the two ladders drawn along the erimeter of a circle. 4.. Interolation The conventional flash architecture was modified for use with the coarse quantizer by

253 Chater 4 Coarse Quantizer Figure 4.4. Three dimensional deiction of differential reference ladder with comarator connections. emloying interolation between adjacent comarator re-amlifiers to reduce ower dissiation and caacitive loading. The interolation utilized combines oututs from adjacent differential comarator re-amlifiers (Fig. 4.5) to create a virtual threshold for a comarator where no re- Preams V0 VA Vn VA Comarators C0 VA VA VB VB Vin V Vn- VB VB C C "0" Actual Thresholds C0 C C R ta I lad "" Interolated Threshold Figure 4.5. Interolation between reamlifiers reduces loading on differential reference ladder and reduces ower by halving the number of comarator re-amlifiers.

254 4. 4-Bit Flash Quantizer 3 amlifier differential inut voltage equals zero [3], [4], [5]. This oeration relies on the fact that the reamlifier outut transition from one olarity to the other occurs over some reasonable range of inut voltage. Otherwise, the interolation would be ineffective. By using this interolation technique, the number of re-amlifiers used in the coarse quantizer was reduced from 5 to 8. This reduction minimizes ower dissiation and reduces caacitive loading on the differential reference ladder significantly. The differential ladder with interolation can be visualized abstractly with the aid of figure 4.6 where re-amlifier connections to the reference ladder are drawn in black, and +Vin -Vin V0 V0 V V Vn- Vn- Vn Vn Figure 4.6. Differential reference ladder drawn to emhasize circular symmetry, and including reference to interolated thresholds in grey. virtual connections which are generated with interolation are drawn in grey.

255 4 Chater 4 Coarse Quantizer 4..3 Layout and DAC Interface The eight differential-air re-amlifiers are laid out in a linear array with the differential ladder to their left (as oriented in figure 4.7). This array is most easily connected to the comarator array by abutment, so the 5 comarators must itch-align with the 8 reamlifiers, imlying that a high asect-ratio is necessary for the comarator layout (Fig. 4.8). Each comarator cell also includes a differential air serving as a current switch of the segmented reconstruction DAC. Locating the DAC current switches within the comarator cells greatly reduces wiring caacitance, and the direct connection between the flash comarators and the current segment switches rovides for maximum switching seed by eliminating all intervening logic [6]. The comlete coarse quantizer with differential ladder, interolating re-amlifiers, and comarators with internal DAC switches is shown in figure 4.9. References [] A. G. F. Dingwall, Monolithic exandable 6 bit 0 MHz CMOS/SOS A/D converter, IEEE Journal of Solid State Circuits, vol. SC-4, , Dec [] R. Petschacher, B. Zojer, B. Astegher, H. Jessner, and A. Lechner, A 0-b 75-MSPS subranging A/D converter with integrated samle and hold, IEEE Journal of Solid State Circuits, vol. SC-5, , Dec [3] C. Lane, A 0-Bit 60 MSPS flash ADC, in Biolar Circuits and Technology Meeting, , IEEE, Set [4] C. W. Mangelsdorf, Parallel analog-to-digital converter. U.S. Patent Number 4,94,7, May 990. [5] D. A. Mercer, A -b 750-ns subranging A/D converter with self-correcting S/H, IEEE Journal of Solid State Circuits, vol. SC-6, , Dec. 99. [6] T. Kamoto, Y. Akazawa, and M. Shinagawa, An 8-Bit -ns monolithic DAC, IEEE Jour-

256 4. 4-Bit Flash Quantizer 5 nal of Solid State Circuits, vol. SC-3,. 4 46, Feb Figure 4.7. Coarse quantizer reamlifier array driven by differential reference ladder. xcqrear Size: 8 x 465 microns

257 6 Chater 4 Coarse Quantizer Figure 4.8. Coarse quantizer comarator with internal DAC current switch. cqltchvo Size: 64 x 458 microns

258 4. 4-Bit Flash Quantizer 7 Figure 4.9. Coarse quantizer latch array with current segment inuts and differential DAC outut. ltchar Size: 84 x 60 microns

259 8 Chater 4 Coarse Quantizer

260 Chater 5 Digital to Analog Converter and Residue Amlifier The digital-to-analog converter within the 0-bit ADC roduces an analog signal roortional to the digital outut from the coarse quantizer suitable for subtraction from the ADC inut signal. Because a coarse relica of the inut signal is reconstructed at the DAC outut, the internal D/A converter is frequently termed a reconstruction DAC. The subtraction of the reconstructed signal from the inut occurs within the residue amlifier generating a result which is then rocessed by the fine quantizer to comlete the digitization. To ensure adequate linearity of the ADC, both the D/A converter and the residue amlifier must erform their resective functions with linearity errors below one 0-bit LSB. Since errors in these two comonents form only a fraction of the total error affecting A/D oeration, actual DAC and residue amlifier errors must be well below this level. In addition to these accuracy requirements, both comonents must oerate very raidly while dissiating low ower. The architecture and circuit imlementations of the D/A converter and residue amlifier are discussed in detail next. 5. Segmented Aroach The most imortant requirement for the reconstruction DAC is that its linearity be commensurate with 0-bit oeration. Additionally, the DAC delay-time, as measured from a change

261 30 Chater 5 Digital to Analog Converter and Residue Amlifier in its digital inut until its analog outut has settled adequately, must be minimized; esecially since in the unconventional timing arrangement emloyed (Figs..5 and.6) the DAC must track dynamically changing digital inuts. Since the coarse quantizer comarator bank generates a thermometer code outut, a DAC architecture which directly interfaces with this format is desirable. Several architectures were investigated for suitability as reconstruction DACs given the aforementioned considerations. The R--R ladder DAC [], [], erhas the most commonly imlemented D/A converter architecture, rovides a very efficient solution since only one current source is required er bit. However, the R--R toology exhibits high sensitivity to resistor mismatch and is therefore unsuitable for the resent alication. D/A converters emloying dynamic element matching techniques offer excellent linearity and intolerance to device mismatches [3], [4], [5], [6], [7] but generally require high ower suly voltages and large off-chi decouling elements. Neither of these secial requirements can be suorted in the resent design so dynamic matching methods were abandoned. Current coier techniques offer high accuracy and otentially low ower dissiation [8], [9], but require CMOS devices which are unavailable in the semiconductor rocess used here. A fully-segmented DAC architecture rovides very low sensitivity to device mismatches [0], [] along with the simlest ossible interface to the thermometer code outut from the coarse quantizer and was therefore selected as the architecture for the reconstruction DAC. The segmented imlementation of the reconstruction D/A converter exhibits 4-bit resolution and so consists of 5 equally weighted current segments which are switched under control of the thermometer code outut from the coarse quantizer (Fig. 5.). Each 50 µa segment current is set by a reference voltage driving the base of a twice minimum-size transistor stabilized by a 400 mv degeneration voltage. The ballast resistance necessary to establish this degeneration is 600 Ω imlemented by an 800 µm 5 µm NiCr thin-film resistor with 50 Ω sheet resistance. These resistors were designed to be very large to minimize mismatches along the segment array []. The anticiated mismatch of such a resistor, σ R µ R, in Tektronix SHPi rocess is aroximately 0.%, tyical of many modern semiconductor rocesses [3], [], [0].

262 5. Effects of Mismatches 3 I Out I Out Wiring Matrix A Thin Film (NiCr) Resistors σr 800 µm.% 50 µ A R 5 µm 600 Ω V Ref + 400mV - Figure 5.. Fully-segmented current-outut reconstruction DAC. 5. Effects of Mismatches Current segment mismatches arise from both random and deterministic henomena. Deterministic errors are caused largely by asymmetrical layout of the current segments. For examle, if thermal gradients exist across the segment array the equivalence between the segment currents will be destroyed. Likewise, if the current segments see unequal wiring resistance to ground, individual currents will be erturbed. These tyes of errors must be addressed during layout but are not considered further here. Three sources of random error degrade segment matching: mismatches in transistor saturation current (which also manifest themselves as V BE mismatches when devices carry equal currents), mismatches in transistor current gain, β, and mismatches in current source degeneration resistance. Straightforward analysis [4] indicates that for degeneration voltages a few times larger than the thermal voltage, V T, or more, the mismatch in degeneration resistance dominates the other error sources. Since this condition holds in the DAC designed here, where the degeneration voltage is 400 mv, the relative current source mismatch is aroximated by

263 3 Chater 5 Digital to Analog Converter and Residue Amlifier the relative degeneration resistor mismatch. That is σ I µ I σ R µ R, where I reresents the segment current and R the degeneration resistance. The effect of current source mismatch errors on reconstruction DAC and A/D erformance can be assessed via Monte Carlo simulation wherein current segment values are selected from an assumed random distribution, and the resultant DAC outut levels or A/D thresholds are calculated. Simulation of DAC linearity using this technique led to figure 5. which lots DAC yield (assuming Yield (%) Resolution 4 bits Peak INL / 0-bit LSB Number of Samles Current Segment Mismatch (%) Figure bit yield for a fully-segmented DAC with 4 bit resolution versus current segment mismatch assuming maximum INL is / LSB. eak INL must be below / of a 0-bit LSB) versus the DAC current segment mismatch, σ I µ I. This figure indicates that yield is virtually 00% for σ I µ I < 0.%, and significant degradation occurs for σ I µ I 0.3%. A more ertinent measure of the imact of current segment mismatch is its effect on A/D converter SNR shown in figure 5.3 along with ADC yield (assuming minimally accetable SNR is 59 db). This figure indicates that SNR degradation is minimal when σ I µ I < 0.% and aroaches db when σ I µ I 0.%. Therefore, the above simulations

264 5. Effects of Mismatches ADC Yield at 59 db (%) n4 n7 n5 n n5 n6 Mean SNR (db) n4 n DAC Current Source Matching (%) Figure bit A/D converter yield (uer) and mean SNR (lower) versus segmented DAC current source mismatch for both 4-7 and 5-6 artitioning. indicate that DAC current source mismatches should not degrade A/D converter SNR significantly since the resistor matching exected from the Tektronix rocess is quite good, σ I µ I σ R µ R 0.%. However, the receding simulations assume erroneously that segment errors are uncorrelated with each other. In reality, a strong satial correlation exists among resistors, imlying that if one resistor deviates from the norm, neighboring resistors tend to do so in the same fashion []. Such satial correlation degrades DAC INL from redicted levels. To counteract this

265 34 Chater 5 Digital to Analog Converter and Residue Amlifier henomenon, a wiring matrix added between the DAC current sources and the current switches (Fig. 5.) randomizes the aarent location of current segments by ensuring that hysically roximate segments are not connected to current switches which are located near to each other. An otimum ordering for this scrambling rocedure was develoed by Conroy []. Others have devised scrambling sequences to cancel the effects of current source errors where the mismatches are assumed to follow a linear or quadratic function of distance from the array center [5], [6], [7], [8], [9], [0], but the technique roosed by Conroy gives suerior results and was used here. When the current segments are thus scrambled, the Monte Carlo analysis described earlier accurately redicts DAC and A/D converter erformance degradation due to current segment errors. Therefore, random errors afflicting current source values such that σ I µ I 0.% should not significantly degrade the SNR of the 0-bit A/D converter. 5.3 Layout Considerations To combat the otential deleterious effects of unforeseen deterministic errors such as thermal gradients, three versions of the DAC array were imlemented (and consequently three versions of the A/D converter). The first layout of the DAC current segments (Fig. 5.4) corresonds to the arrangement just described. The connections from the DAC switch array located in the coarse quantizer enter the layout at the to left in sequential order, and as can be seen are connected to the individual current segments in an aarent hahazard ordering. This ordering is actually the otimum arrangement for removing satial correlations alluded to earlier. The lines at the to left of the layout connect seamlessly to those in the layout of the coarse quantizer (Fig. 4.9 at to right). The second DAC current segment layout is intended to cancel linear thermal gradients across the array. Therefore, two identical current source arrays (each with one half the required current) are connected in arallel and hysically arranged so that the centroid of each air of sources connected in arallel is located at the center of the array. Therefore, if the current segments are numbered sequentially from to 5, and the two sub-arrays are designated A and B such that sources A and B are electrically connected in arallel, then moving from one end of the joint array to the other, the sources encountered are A,5B,A,4B,,4A,B,5A,B. In the layout of this current source array (Fig. 5.5), the wiring matrix also enters at the to left and scrambles the effective locations of the sources to minimize the effects of satial correlation. The third DAC current source array is identical electrically to the first, but the degeneration

266 5.3 Layout Considerations 35 resistors are larger and include secial tabs to facilitate laser trimming if necessary. The overall size of the array (Fig. 5.6) is significantly larger than the nominal array and indicates the area enalty aid to enable laser trimming of resistors [], [], [3]. Figure 5.4. Segmented DAC current source array with scrambled wiring matrix at to. dacarray Size: 668 x 9 microns

267 36 Chater 5 Digital to Analog Converter and Residue Amlifier 5.4 Residue Amlifier The urose of the residue amlifier is to subtract the analog outut of the reconstruction Figure 5.5. Segmented DAC current source array with common centroid layout. dacar3 Size: 96 x 5 microns

268 5.4 Residue Amlifier 37 DAC from the held signal out of the inut T/H. To ensure very fast settling, this oeration must be erformed with an oen-loo circuit which achieves the requisite linearity. Since the reconstruction DAC generates a current outut, and since current-mode subtraction is inherently fast, it is desirable to convert the T/H outut signal from a voltage to a current before subtraction. A tyical circuit for erforming the required transconductance and current-mode subtraction (Fig. 5.7a) relies uon a linear transconductance oeration followed by straightforward subtraction of the two current signals. In this method, the transconductance oeration must exhibit linearity commensurate with Figure 5.6. Segmented DAC current source array with trimmable layout. dactrim Size: 36 x 356 microns

269 38 Chater 5 Digital to Analog Converter and Residue Amlifier +Vout- +Vout- +Vin DAC -Vin +Vin -Vin Vout (a) Residue Waveform DAC (b) Vin Coarse quantizer Thresholds (c) Figure 5.7. Residue amlifier imlementations. (a) Tyical aroach using transconductance cell and subtracting currents at outut. (b) Imroved aroach subtracting currents at transconductor emitter. 0-bit oeration. An imroved technique (Fig. 5.7b) subtracts the signal currents at the emitters of the transconductance amlifier taking advantage of the reduced dynamic range of the signal at this location. Because the current subtraction takes lace in the degeneration resistor of the transconductance stage, the signal current modulating the V BE of the inut transistors is reduced by a factor of 6 comared to the revious case. This reduction occurs because the DAC outut current is a close aroximation to the transconductance current resulting in a current waveform similar to that shown in figure 5.7c. The reduction in dynamic range reduces distortion significantly since according to equations 3.5 and 3.53, HD is roortional to the signal amlitude, and HD 3 is roortional to the square of the signal amlitude. Therefore, the imroved residue amlifier reduces HD comared to the conventional case by 0log6 4dB, and the HD 3 by a dramatic 0log6 48dB. In addition to the imroved linearity offered by the new aroach,

270 5.4 Residue Amlifier 39 the ower dissiation is reduced comared to the conventional toology since the bias current of the DAC is also used by the transconductance stage. By selecting the load resistors of the residue amlifier to be twice the value of the degeneration resistor a gain of 4 is achieved along with the subtraction oeration. The hysical imlementation of the residue amlifier is shown in figure 5.8. References [] D. J. Dooley, A comlete monolithic 0-b D/A converter, IEEE Journal of Solid State Circuits, vol. SC-8, , Dec [] B. E. Amazeen, P. R. Holloway, and D. A. Mercer, A comlete single-suly microrocessor-comatible 8-bit DAC, IEEE Journal of Solid State Circuits, vol. SC-5,. 059 Figure 5.8. Residue amlifier and its relicas. resamar Size: 54 x 38 microns

271 40 Chater 5 Digital to Analog Converter and Residue Amlifier 070, Dec [3] R. J. van de Plassche, Dynamic element matching for high-accuracy monolithic D/A converters, IEEE Journal of Solid State Circuits, vol. SC-, , Dec [4] R. J. van de Plassche and D. Goedhart, A monolithic 4 bit D/A converter, IEEE Journal of Solid State Circuits, vol. SC-4, , June 979. [5] R. J. van de Plassche and H. J. Schouwennars, A monolithic 4 bit A/D converter, IEEE Journal of Solid State Circuits, vol. SC-7,. 7, Dec. 98. [6] E. C. Kwong, G. L. Baldwin, and T. Hornak, A frequency-ratio-based -bit MOS recision binary current source, IEEE Journal of Solid State Circuits, vol. SC-9, , Dec [7] H. J. Schouwenaars, E. C. Dijkmans, B. M. J. Ku, and E. J. M. van Tuijl, A monolithic dual 6-bit D/A converter, IEEE Journal of Solid State Circuits, vol. SC-, , June 986. [8] H. J. Schouwenaars, D. W. J. Groeneveld, and H. A. H. Termeer, A low-ower stereo 6- bit CMOS D/A converter for digital audio, IEEE Journal of Solid State Circuits, vol. SC- 3, , Dec [9] D. W. J. Groeneveld, H. J. Schouwenaars, H. A. H. Termeer, and C. A. A. Bastiaansen, A self-calibration technique for monolithic high-resolution D/A converters, IEEE Journal of Solid State Circuits, vol. SC-4,. 57 5, Dec [0] J. A. Schoeff, An inherently monotonic bit DAC, IEEE Journal of Solid State Circuits, vol. SC-4, , Dec [] C. S. G. Conroy, W. A. Lane, and M. A. Moran, Statistical design techniques for D/A converters, IEEE Journal of Solid State Circuits, vol. SC-4,. 8 8, Aug [] M. J. M. Pelgrom, A. C. J. Duinmaijer, and A. P. G. Welbers, Matching roerties of MOS transistors, IEEE Journal of Solid State Circuits, vol. SC-4, , Oct [3] G. Kelson, H. H. Stellrecht, and D. S. Perloff, A monolithic 0-b digital-to-analog converter using ion imlantation, IEEE Journal of Solid State Circuits, vol. SC-8, , Dec [4] P. R. Gray and R. G. Meyer, Analysis and Design of Analog Integrated Circuits. John Wiley and Sons, second ed., 984. [5] P. H. Saul and J. S. Urquhart, Techniques and technology for high-seed D-A conversion, IEEE Journal of Solid State Circuits, vol. SC-9,. 6 68, Feb [6] T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, An 80MHz 8b CMOS D/A converter, in International Solid State Circuits Conference,. 3 33, IEEE, Feb [7] T. Miki, Y. Nakamura, M. Nakaya, S. Asai, Y. Akasaka, and Y. Horiba, An 80-MHz 8- bit CMOS D/A converter, IEEE Journal of Solid State Circuits, vol. SC-, , Dec [8] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, A 0-b 70-MS/s CMOS D/A converter, in 990 Symosium on VLSI Circuits Digest of Technical Paers, , IEEE, 990.

272 5.4 Residue Amlifier 4 [9] Y. Nakamura, T. Miki, A. Maeda, H. Kondoh, and N. Yazawa, A 0-b 70-MS/s CMOS D/A converter, IEEE Journal of Solid State Circuits, vol. SC-6, , Ar. 99. [0] F. G. Weiss, A Gs/s GaAS DAC with on-chi current sources, in GaAs IC Symosium,. 7 0, IEEE, 986. [] J. J. Price, A assive laser-trimming technique to imrove linearity of a 0-bit D/A converter, IEEE Journal of Solid State Circuits, vol. SC-, , Dec [] K. Kato, T. Ono, and Y. Amemiya, A monolithic 4 bit D/A converter fabricated with a new trimming technique (DOT), IEEE Journal of Solid State Circuits, vol. SC-9, , Oct [3] J. Shier, A finite-mesh technique for laser trimming of thin-film resistors, IEEE Journal of Solid State Circuits, vol. SC-3, , Aug. 988.

273 4 Chater 5 Digital to Analog Converter and Residue Amlifier

274 Chater 6 Folding Fine Quantizer 6. Concet of Folding As described in chater, a feedforward multi-stage A/D converter gains efficiency by artitioning an N-bit quantization into a number of lower-resolution quantizations. In such a converter (Fig. 6.a) an n-bit coarse quantizer digitizes the inut signal with low resolution, and alies the resultant codeword to a reconstruction DAC. The analog outut of the DAC is then subtracted from the original inut to form a residue signal (Fig. 6.b) which is quantized by an n-bit fine quantizer. The advantage of this aroach arises because the combined comlexity of the n-bit coarse quantizer and the n-bit fine quantizer can be far less than the comlexity of a single N-bit quantizer. The object of a folding quantizer is to form the residue signal with simle analog circuits thereby obviating the need for the coarse quantizer, DAC, and subtracter comonents of figure 6.a. In such an imlementation (Fig. 6.), the low dynamic-range residue signal generated by the analog folding circuit directly drives the fine quantizer. Because of the eriodic nature of the residue signal; however, the digitized outut from the fine quantizer is ambiguous, and a coarse quantizer is still necessary to ascertain in which eriod of the folding circuit s transfer characteristic the quantizer inut signal lies. The inut-outut characteristic of the analog folding circuit can be arameterized by the number of iece-wise linear segments, or folds, which it contains. This arameter, abbreviated F, determines the resolution of both the coarse and

275 44 Chater 6 Folding Fine Quantizer Vin Residue ADC N Fine Bits ADC DAC (a) Residue N Coarse Bits N Coarse Quantizer Thresholds (b) Vin N Fine Thresholds Figure 6.. Architecture of feedforward quantizer. Vin Vout Analog Folding Circuit with F Folds Vin Vout Fine Quantizer ( /F Thresholds) N LSB s Coarse Quantizer (F Thresholds) MSB s Digital Encoder N-bit Outut Figure 6.. Folding A/D converter architecture. Analog folding with F folds reduces fine quantizer resolution to N F. fine quantizers required in a folding A/D converter (Fig. 6.3). Since the coarse quantizer requires F

276 6. Concet of Folding 45 V FS V FS Comarator Array Inut Signal N Thresholds Flash Converter N Thresholds Flash Converter Folding Converter Folding Converter V FS /F N /F Thresholds V FS /F N /F Thresholds 0 0 Fold Fold A/D Inut Signal (a) Fold F- Fold F V FS 0 0 Fold Fold A/D Inut Signal (b) Fold F- Fold F V FS Figure 6.3. Reduction in dynamic range seen be comarator array for (a) sawtooth and (b) triangle folding characteristics. thresholds, its resolution is n log F while the fine quantizer requires N F thresholds so its resolution is n log ( N F) N n. 6.. Linear Folding Circuits Folding A/D converters based on the architecture of figure 6. would be ossible if simle analog circuits could easily realize the iece-wise linear inut-outut characteristics indicated. However, because of the discontinuities in the folding transfer function, these tyes of characteristics are inherently difficult to realize. Several imlementations have been develoed which aroximate the triangle wave folding characteristic of figure 6.3, but each has significant drawbacks. For examle, the circuit of figure 6.4 [], [] based on the translinear rincile, offers a near ideal aroximation to a triangle wave folding characteristic. However, the differential inut voltage varies by diode dros for each fold within the transfer function. So if eight folds are desired, the differential inut voltage range is 6 V D V. This voltage swing is unaccetably large for the low-ower, high-frequency alication considered here. A second folding circuit which aroximates the ideal triangle wave deicted in figure 6.3 is shown in figure 6.5 [3]. This toology also aroximates the triangle waveform quite well, but also suffers from the

277 46 Chater 6 Folding Fine Quantizer I I I I I αi (4-α)I Iout Iout I Iout- Iout 3 4 α -I Figure 6.4. Translinear-based current-mode folding circuit. large inut swing requirement which lagued the first circuit. In addition, this imlementation exhibits a large common mode outut current uon which the differential outut current is suerimosed. In ractical alications with limited ower suly voltages, this common-mode comonent could rove roblematic. Generally, circuits with discontinuous inut-outut characteristics are difficult to realize and are not amenable to high-seed alications. Therefore, folding converters which do not rely uon iece-wise linear folding functions revail.

278 6. Sinusoidal Folding 47 I out I out 4I 4I α I I I I I I (4- α)ι I Iout- Iout 3 4 α -I Figure 6.5. Current-mode folding circuit using cascodes. 6. Sinusoidal Folding A folding A/D converter based uon a eriodic, but not iece-wise linear folding function can be develoed if the non-linear function is well behaved which in this context means that the characteristic is eriodic and does not saturate [4], [5]. A sinusoidal folding function (Fig. 6.6) serves as an at examle. In this case, the folding characteristic resembles the triangle-wave deicted in figure 6.3b; however, the outut signal from the folding circuit is not a linear function of the inut. Therefore, the fine quantizer must contain thresholds which are not uniformly saced, but which are located according to an inverse-sine law. This threshold lacement would be very difficult to achieve in ractice, but a simle alternative lies in generating many sinusoids, uniformly shifted in hase with resect to each other (Fig 6.7). In this arrangement, the fine quantizer consists of an array of comarators, each with its reference inut grounded so that the quantizer thresholds corresond to the zero-crossings of the sinusoids. Since the sinusoids are equally-saced in hase, their zero-crossings are equally-saced along the analog inut range, and the quantizer thresholds are located correctly. Generating the hase-shifted waveforms with an array of sinusoidal folding

279 48 Chater 6 Folding Fine Quantizer Vin Vout Sinusoidal Folding Circuit Vin Vout Inverse-Sine Fine Quantizer Coarse Quantizer Digital Encoder Figure 6.6. A folding function which is not iece-wise linear. The transfer function shown is sinusoidal for convenience but could be any non-saturating, eriodic function. In-Phase Θ 0 Vin Θ 90/Ν Digital Encoder QuadratureΘ 90 Figure 6.7. An array of hase-shifted, non-linear folding blocks with comarators detecting zero-crossings can circumvent the need for an inversesine quantizer. circuits would be very inefficient, but a simlification of the scheme deicted in figure 6.7 obviates the need for this tye of redundancy. Instead, only two quadrature sinusoids are generated, and the remaining signals are obtained by linear suerosition between the first two. A simle technique for

280 6. Sinusoidal Folding 49 achieving the suerosition utilizes resistive interolation (Fig. 6.8). By aroriately selecting the In-Phase Θ 0 Θ 0 Vin Q γ I Interolation 90/Ν Digital Encoder QuadratureΘ 90 Θ 90 Figure 6.8. Linear suerosition imlements non-uniform interolation to generate multile sinusoids equally-saced in hase from two quadrature sinusoids. interolation resistors, any desirable hase angle, γ, can be generated. The folding quantizer architecture resented in figure 6.8 is simle and otentially very efficient; however, ractical circuits must be available to generate the two quadrature sinusoids, and the interolation scheme must be easily imlemented and robust. These two issues are discussed in the following sections. 6.. Sinusoidal Folding Circuits Several circuits with sinusoidal transfer functions were investigated for suitability in folding quantizers. The first such circuit considered (Fig. 6.9) [], is based on the translinear rincile and offers the advantages of simlicity and low common-mode outut current for a given differential outut. However, as in the case with the revious translinear-based folding circuits, the voltage drive required to obtain an inut-outut characteristics with 8 folds (or equivalently 4 eriods) is on the order of 5 V. This voltage swing is not comatible with the quantizer being designed here. Therefore, the circuit of figure 6.9 was rejected. A modification of this folding circuit requires a differential current drive rather than a differential voltage drive (Fig. 6.0) [], but still demands a very large voltage swing at its inut to generate several folds. A different aroach which does not require large voltage drive (because it is not a translinear circuit) is deicted in figure 6.

281 50 Chater 6 Folding Fine Quantizer I I I I I Vin+ R R R R Vin- Iout I out IE I out - I out I E Increasing IR Vin+ - Vin- IR - I E Figure 6.9. Translinear sinusoidal folding circuit with voltage drive. [6], [7]. This circuit relies on the hyerbolic tangent transfer function of a voltage driven biolar differential air to aroximate a sinusoid. By selecting the voltage searation between the references V, V, V 3, and V 4 aroriately, a good aroximation to a sinusoid may be made VT over a few eriods. An aroriate voltage searation is a few times the thermal voltage,, so the total inut voltage swing is on the order of V for an 8-fold circuit, an accetable value. The circuit of figure 6. suffers some imortant drawbacks. The inut is single-ended so, as in the case of the flash coarse quantizer from chater 4, bias currents flowing into the folding circuit s differential airs will erturb the aarent reference voltages thereby distorting the desired shae of the sinusoid. Additionally, the outut current from the folding circuit consists of a large common-mode comonent with only a small differential comonent. Therefore, oeration under limited ower suly voltage ranges oses biasing roblems. Lastly, if many folds are desired, mandating many differential airs in the folding circuit, then the caacitive loading on the outut node becomes large adversely affecting settling time. Some of these drawbacks are overcome by the circuit of figure 6. [4], [9], [0], [], [], [3] which uses a wired-or configuration at the differential air

282 6. Sinusoidal Folding 5 R.4R 3.4R.4R R 0.7R R R 0.7R αi (- α)i I out I out I E I out - I out I E Increasing IR /4 / 3/4 α -I E Figure 6.0. Translinear sinusoidal folding circuit with current drive. oututs to reduce the common-mode outut signal and to rovide buffering. This circuit still suffers from the threshold erturbing effects of a single-ended reference scheme. To eliminate this error source, the sinusoidal folding circuit of figure 6.3 was develoed. This circuit incororates a differential reference ladder identical to that described in chater 4 [4], [3], [3], [6]. Therefore, errors due to inut bias current flowing through the resistive reference ladder and into the differential airs comrising the folding circuit are eliminated. Cascode devices are emloyed to reduce the imedance at the common collector node loaded by significant device caacitance, and de-bias resistors connected from the cascode emitters to the ositive suly absorb most of the bias current drawn by the differential airs in the folding circuit. Owing to the low inut imedance of the cascode devices, only a small amount of signal current flows into the de-bias resistors. Therefore, the outut signal has a large differential-mode comonent and a small common-mode comonent as desired. Two extra differential airs are added to the folding circuit at the extremes to ensure that each of the 9 remaining airs in the circuit exerience symmetric effects from nearestneighbor differential airs. This technique maintains the fidelity of the sinusoid at the extremes of

283 5 Chater 6 Folding Fine Quantizer Vin R L R L V V V V3 V V4 V + - Vout I I I I Vout IR L V V V3 V4 Vin -IR L Figure 6.. Folding circuit based uon hyerbolic tangent transfer function of voltage driven differential airs. the inut range. Notice that the hase of the resulting waveform can be controlled by shifting the ositions along the reference ladder to which the folding circuit connects. In this way, a second folding circuit whose outut is in quadrature with the first can easily be constructed. A significant drawback of this folding circuit is its deendence on temerature. Since the gain of the differential airs within the circuit vary with temerature, and since the outut waveform is not an exact sinusoid but an aroximation to one, the shae of the outut waveform will change slightly with temerature. This changing shae introduces errors into the resulting quantizer transfer function which will be discussed in detail in the next sub-section.

284 6.3 Non-uniform Interolation 53 R L R L R L R L R L + - Vout Vin V V V V3 V V4 V I I I I Vout IR L V V V3 V4 Vin -IR L Figure 6.. Folding circuit based on wired-or interconnection. Rl +Vout- Rl I I I I I I I I I I I Vin+ Rt Rt Rt Rt Rt Rt Rt Rt Rt Rt Im Im Rt Rt Rt Rt Rt Rt Rt Rt Rt Rt Vin- Vout IRl IRl Vin+ - Vin- Im Rt Figure 6.3. Fully-differential sinusoidal folding circuit with differential reference ladder, overflow comensation, and common-mode de-bias circuitry. 6.3 Non-uniform Interolation

285 54 Chater 6 Folding Fine Quantizer The interolation scheme deicted in figure 6.8 is concetually straightforward and can be imlemented with a simle resistive ladder as deicted in figure 6.4. Here differential emitter I V6 R R R V5 R V4 R R Q V3 R R V V R R I R R Q R R R Figure 6.4. Differential non-uniform interolation ladder generates sinusoids equally saced in hase from quadrature inuts. Distortion is minimized due to symmetry of circuit enabling use of simle, low-ower emitter follower buffers. followers buffer the quadrature signals outut by the two folding circuits discussed above. The quadrature waveforms are termed the In-hase signal and the Quadrature signal and are therefore labelled I and Q in the schematic. The interolation ladder is redrawn along with a hasor diagram and lots of interolated waveforms in figure 6.5 to emhasize the analogous reresentations. Note the similarity, both hysical and concetual, between the electrical reresentation and the hasor reresentation. Comarator differential inuts connect to oints diametrically oosed on the resistive ring. Also, the symmetry of this configuration reduces the effects of distortion in the emitter follower buffers. When I I, Q Q so that signal current flows from the Q node, through the interolation ring and into the Q node, but the voltages at I and I remain unerturbed so that no

286 6.3 Non-uniform Interolation 55 I V6 R R R R Q R V5 V4 R R R R R R Q V3 V R R R R V I I V6 V5 V4 θ θ θ Q θ θ V3 θ θ θ V V I (a) (b) V Out 0 V In -V FS (c) V FS Figure 6.5. (a) Differential non-uniform interolation ladder. (b) Phasor reresentation of quadrature and interolated signals. (c) Corresonding voltage waveforms. threshold variation results. Similarly, when I Q, then I Q so that signal current flowing from the I node equals that flowing from the Q node, and signal current flowing to the I node equals that flowing to the Q node. Therefore, resultant V BE modulation in the emitter follower buffers cancels and, again, no threshold erturbation results. The resistor values required to obtain interolated sinusoids equally-saced in hase from two quadrature waveforms can be found by simle trigonometric identities. The resistor sread necessary is about :, and sensitivity of ADC threshold lacement to resistor errors is quite low. When temerature is varied, the shae of the incoming quadrature signals changes leading to threshold error. Simulations of this effect shown in figure 6.6 indicate that threshold errors are nearly non-existent at room temerature as desired, but increase for both temerature extremes. Maximum threshold error occurs when temerature is -55 C reaching a magnitude of aroximately 6% of an 8-bit LSB.

287 56 Chater 6 Folding Fine Quantizer DNL (% of 8-Bit LSB) T5 T00 T75 T50 T5 T0 T-5 T Interolation Position Figure 6.6. Threshold error at interolated thresholds. 6.4 Folding and Interolating A/D Converter The comonents required to imlement the folding quantizer block diagram deicted in figure 6.8 have been demonstrated; however, several additional functions must be added to form a useful circuit. Figure 6.7 includes all necessary circuitry for a 7-bit folding quantizer. The inut signal (assumed differential) drives a differential reference ladder attached to two folding circuits which generate quadrature differential sinusoidal oututs called I and Q. These signals are alied via emitter follower buffers across a differential non-uniform interolation ladder to generate an array of equally hase-shifted sinusoids. The array of sinusoids must be digitized and encoded. Additionally, a coarse quantizer must determine within which fold of the sinusoidal transfer characteristic the inut signal lies. The coarse quantizer is sometimes called a cycle-ointer because it identifies which cycle of the folding characteristic the inut signal occuies. In the block diagram of figure 6.7, as in all folding A/D converters, the number of

288 6.4 Folding and Interolating A/D Converter 57 X 8 X Sinewave Generators Folds er Sinewave Times Interolation Vin Differential Reference Ladder (6 tas) I Q Nonuniform Differential 8X Interolation Ladder Analog Encoding and Comarators (5 Bits) Digital Encoding & Error Correction Digital Outut (7 Bits) Cycle-Pointing Coarse Quantizer (3 Bits) Figure 6.7. Folding, interolating, and analog encoding fine quantizer using quadrature folded waveforms. thresholds, N, is determined by N AFI (6.) where A is the number of folding circuits, F is the number of folds in each folded waveform, and I is the interolation factor. In the resent design, A since only the I and Q folding circuits are used, F 8 which is a ractical limit for low voltage-swing converters, and I 8 which is required so that AFI Encoding The novel encoding technique used for this converter greatly reduces the comlexity of the necessary encoding circuitry (Fig. 6.8). Rather than drive comarators directly, the oututs from the interolation ladder are encoded in the analog domain before digitization. This encoding most naturally mas to Gray code, wherein each decreasingly significant bit transitions at twice the rate of its redecessor (Fig. 6.8, right side). In the resent encoding scheme, this relationshi is roduced by multilying two quadrature signals which transition at the rate of the redecessor bit (recall that the roduct of quadrature sinusoids is a third sinusoid at twice the frequency). The result is a simle encoding tree comosed of multilier elements: analog multilier encoders and digital Exclusive-OR gates. In fact, the analog encoders are very simle multilier circuits identical to Exclusive-OR gates. The latching comarators define the transition boundary across which encoded analog signals become digital logic levels.

289 58 Chater 6 Folding Fine Quantizer I Q Q I BIT R R R R BIT R R R R BIT 3 R3 R3 R3 R3 BIT 4 R4 R4 R4 R4 BIT 5 Nonuniform Interolation Ladder Analog Multilier Encoders Comarators Digital Encoding Gray Coded Outut Waveforms Figure 6.8. Imroved encoding scheme significantly reduces hardware comlexity. All circuits are differential but are shown single-ended for simlicity Cycle Pointer (Coarse Quantizer) The coarse quantizer outut is in Gray code, for comatibility with the Gray-coded fine quantizer, and also to minimize encoding errors caused by comarator metastability. Analog encoders, simlified versions of folding amlifiers [7], [8], [9], [0], [], [], [3], roduce this Gray code (Fig. 6.9) by comaring the analog inut with aroriate reference voltages. Oututs from these analog rocessing blocks are digitized generating Gray code directly with no other intervening logic Layout The layout of the analog ortion of the folding 7-bit quantizer (Fig. 6.0) includes the differential reference ladder, the folding amlifiers, interolation ladder, and analog multiliers from the encoding block. This ortion of the chi is aroximately 00µm 00µm.

290 6.4 Folding and Interolating A/D Converter 59 V A V B V C out VD VE VF In MSB Vin + - Vout V A V B V C out VD VE VF In MSB- Inut + _ Vout 3 V A V B V C out VD VE VF In MSB- Vin V B V E 3 + _ Vout 4 V A V B V C out VD VE VF In MSB-3 Vin VA V C V D V F Gray Code Digital Outut Figure 6.9. Cycle ointer incororating analog encoding. Actual circuit is differential but is shown single-ended for simlicity. References [] B. Gilbert, Monolithic analog READ-ONLY memory for character generation, IEEE Journal of Solid State Circuits, vol. SC-6, , Feb. 97. [] B. Gilbert, A monolithic microsystem for analog synthesis of trigonometric functions and their inverses, IEEE Journal of Solid State Circuits, vol. SC-7,. 79 9, Dec. 98. [3] R. J. van de Plassche and R. E. J. van der Grift, A high-seed 7 bit A/D converter, IEEE Journal of Solid State Circuits, vol. SC-4, , Dec [4] W. Wolz, Videoumsetzer mit mehrfachfaltung, Elektronik, , July 983. [5] J. V. Woods and R. N. Zobel, Fast synthesized cyclic-arallel analogue-digital convertor, IEE Proceedings, vol. 7,. 45 5, Ar [6] A. Arbel and R. Kurz, Fast ADC, IEEE Transactions on Nuclear Science, vol. NS-, , Feb [7] R. E. J. van de Grift and R. J. van de Plassche, A monolithic 8-bit video A/D converter,

291 60 Chater 6 Folding Fine Quantizer IEEE Journal of Solid State Circuits, vol. SC-9, , June 984. [8] R. E. J. van de Grift, I. W. J. M. Rutten, and M. van der Veen, An 8 bit video ADC incororating folding and interolation techniques, IEEE Journal of Solid State Circuits, vol. SC-, , Dec [9] R. E. J. van de Grift and M. van der Veen, An 8b 50MHz video ADC with folding and interolation techniques, in International Solid State Circuits Conference, , IEEE, Feb [0] R. J. van de Plassche and P. Baltus, An 8b 00-MHz folding ADC, in International Solid State Circuits Conference,. 3, IEEE, Feb [] R. J. van de Plassche and P. Baltus, An 8-bit 00-MHz full Nyquist analog-to-digital con- Figure 6.0. Layout of fine quantizer analog circuitry including differential reference ladder, folding amlifiers, interolation ladder, and analog multiliers from the encoding block. xfqfend Size: 3 x 3 microns

292 6.4 Folding and Interolating A/D Converter 6 verter, IEEE Journal of Solid State Circuits, vol. SC-3, , Dec [] J. van Valburg and R. van de Plassche, An 8b 650MHz folding ADC, in International Solid State Circuits Conference,. 30 3, IEEE, Feb. 99. [3] P. Vorenkam and J. P. M. Verdaasdonk, A 0b 50Ms/s ielined ADC, in International Solid State Circuits Conference,. 3 33, IEEE, Feb. 99. [4] L. M. Devito, High-seed voltage-to-frequency converter. U.S. Patent Number 4,839,653, June 989. [5] R. Petschacher, B. Zojer, B. Astegher, H. Jessner, and A. Lechner, A 0-b 75-MSPS subranging A/D converter with integrated samle and hold, IEEE Journal of Solid State Circuits, vol. SC-5, , Dec [6] A. G. F. Dingwall, Monolithic exandable 6 bit 0 MHz CMOS/SOS A/D converter, IEEE Journal of Solid State Circuits, vol. SC-4, , Dec [7] J. J. Corcoran, K. L. Knudsen, D. R. Hiller, and P. W. Clark, A 400MHz 6b ADC, in International Solid State Circuits Conference, , IEEE, Feb [8] A. P. Brokaw, Parallel analog-to-digital converter. U.S. Patent Number 4,70,8, May 98. [9] T. W. Henry and M. P. Morgenthaler, Direct flash analog-to-digital converter and method. U.S. Patent Number 4,386,339, May 983. [0] C. W. Mangelsdorf, Parallel analog-to-digital converter. U.S. Patent Number 4,94,7, May 990. [] C. W. Mangelsdorf and A. P. Brokaw, Integrated circuit analog-to-digital converter. U.S. Patent Number 4,596,976, June 986. [] P. A. Reiling, Translating circuits. U.S. Patent Number,9,5, Jan [3] P. A. Reiling, Analog-to-digital converter. U.S. Patent Number 3,573,798, Ar. 97.

293 6 Chater 6 Folding Fine Quantizer

294 Chater 7 Gain Stabilization 7. Gain Matching Requirements Gain mismatch among the 0-bit ADC comonents leads to threshold errors in the A/D converter transfer function [], [], [3], [4], [5]. These errors are most easily quantified by their effect on SNR according to equation.09. However, comonent gain errors also give rise to distortion, since the threshold disturbances they cause are not random, but deterministic functions of analog inut voltage. As mentioned in section 0., a useful area of inquiry lies in determining analytic exressions for ADC distortion in terms of ertinent gain mismatch factors. Three comonent gain errors are considered: coarse quantizer gain error, DAC gain error, and fine quantizer gain error. All other gain errors can be exressed as equivalent values of these three. Variations in coarse quantizer gain from the ideal value cause equivalent variations in the ADC gain, but do not degrade linearity. DAC gain errors cause the residue waveform to exceed the inut range of the fine quantizer for extreme values of inut voltage (Fig. 7.a). Such errors in the residue waveform manifest themselves as SNR degradation. This effect, described in chater and reeated here for convenience (Fig. 7.), becomes excessive for DAC gain errors greater than about % in magnitude for the 4,7 artitioning used here. Fine quantizer gain errors cause eriodic disturbances of the A/D converter thresholds (Fig. 7.b) which degrade linearity. Therefore, fine quantizer gain error must also be limited to about % before SNR diminishes significantly (Fig.

295 64 Chater 7 Gain Stabilization Residue V DAC - V in DAC gain too low DAC gain too high Nominal Inut Range to nd Quantizer Correct DAC Gain 0 Vfs/4 Vfs/ 3Vfs/4 Vfs Vin V V Oam ensures VV Segment 0 (b) Segment 5 Vfs Reconstruced A/D Outut 3Vfs/4 Ideal Waveform Vfs/ Vfs/4 A/D Outut with Incorrect nd Quantizer Full-Scale Range 0 Vfs/4 Vfs/ 3Vfs/4 Vfs Vin (a) Figure 7.. Effects of comonent gain errors on A/D transfer function. (a) Effect of fine quantizer gain error. (b) Effect of DAC gain error. 7.3).

296 7. Gain Control n5 n6 SNR (db) n4 n7 0 n4 n7 ADC Gain Error (%) n5 n DAC Gain Error (%) Figure bit A/D converter SNR (uer) and gain error (lower) versus DAC gain error for both 4-7 and 5-6 artitioning. 7. Gain Control To avoid the errors described above, the full-scale range of the reconstruction DAC must match the full-scale range of the inut signal; and the residue, after amlification, must align with the full-scale range of the fine quantizer. These gains are matched to one another using on-chi relica circuits (Fig. 7.4) [0], [7], [3], [9]. An externally sulied reference voltage equal to the

297 66 Chater 7 Gain Stabilization n5 n6 SNR (db) n4 n ADC Gain Error (%) n4 n7 n5 n Fine Quantizer Gain Error (%) Figure bit A/D converter SNR (uer) and gain error (lower) versus fine quantizer gain error for both 4-7 and 5-6 artitioning. full-scale range of the inut drives a scaled relica of the coarse quantizer differential reference ladder, and an o-am forces the DC voltage across both the relica and the main ladders to match this reference. Similarly, the full-scale reference voltage and an attenuated version drive two scaled relicas of the residue amlifier biased by two scaled DAC relicas set the secific thermometer codes and 0. (The scaling factor used here is :5 so the relica DAC settings corresond to all 5 segments on and 0-of-5 segments on resectively.) A second o-am controls the segment currents in the relica and main DAC to align two eaks along the sawtooth residue characteristic

298 7. Gain Control 67 +Vfs -Vfs 4 Scaled S/H Relica First Quantizer Ladder Hardwired DAC Switch " " Hardwired DAC Switch "0 " DAC Segment Currents Second Quantizer Ladder Coarse Quantizer Gain Loo Reconstruction DAC Gain Loo Fine Quantizer Gain Loo Figure 7.4. Gain-matching relica circuits and feedback loos which adjust comonent gains. (voltages V and V in figure 7.a). Thus, the DAC full-scale range aligns with the first quantizer full-scale range. The outut of one relica residue amlifier also sulies the reference level to a relica of the second quantizer ladder. The second quantizer gain is controlled by a third o-am loo identical to that controlling the first quantizer gain. All three o-ams, which oerate at DC in the relica circuits, are off-chi. References [] S. H. Lewis and P. R. Gray, A ielined 5MHz 9b ADC, in International Solid State Circuits Conference,. 0, IEEE, Feb [] S. H. Lewis and P. R. Gray, A ielined 5-Msamle/s 9-bit analog-to-digital converter,

299 68 Chater 7 Gain Stabilization IEEE Journal of Solid State Circuits, vol. SC-, , Dec [3] S. Sutarja and P. R. Gray, A 50ks/s 3b ielined A/D converter, in International Solid State Circuits Conference,. 8 9, IEEE, Feb [4] S. Sutarja and P. R. Gray, A ielined 3-bit, 50-ks/s, 5-V analog-to-digital converter, IEEE Journal of Solid State Circuits, vol. SC-3, , Dec [5] M. Ishikawa and T. Tsukahara, An 8-bit 50-MHz CMOS subranging A/D converter with ielined wide-band S/H, IEEE Journal of Solid State Circuits, vol. SC-4, , Dec [6] T. Shimizu, M. Hotta, K. Maio, and S. Ueda, A 0-bit 0-MHz two-ste arallel A/D converter with internal S/H, IEEE Journal of Solid State Circuits, vol. SC-4,. 3 0, Feb [7] T. Shimizu, M. Hotta, K. Maio, and S. Ueda, A 0b 0MHz two-ste arallel ADC with internal S/H, in International Solid State Circuits Conference,. 4 5, IEEE, Feb [8] R. Petschacher, B. Zojer, B. Astegher, H. Jessner, and A. Lechner, A 0-b 75-MSPS subranging A/D converter with integrated samle and hold, IEEE Journal of Solid State Circuits, vol. SC-5, , Dec [9] P. Vorenkam and J. P. M. Verdaasdonk, A 0b 50Ms/s ielined ADC, in International Solid State Circuits Conference,. 3 33, IEEE, Feb. 99.

300 Chater 8 Performance Three versions of the 0-bit A/D converter differing exclusively in the layout of the reconstruction DAC were fabricated in the Tektronix SHPi rocess. Each chi occuies the same area and uses identical ad locations to facilitate testing. The erformance of these chis is discussed next. A searate 8-bit A/D converter based uon the 7-bit fine quantizer of chater 6 was also fabricated. Performance of the 8-bit device is discussed in chater Circuit Layout Because low comlexity quantizers comrise the A/D converter, each chi incororates less than 500 transistors and even fewer resistors so that the silicon area occuied is aroximately 4mm 4mm, or equivalently 60mil 60mil (Fig 8.). The 4-bit coarse quantizer, DAC current switches, and encoding logic (including the Coarse Ladder, Coarse Latches & DAC Switches, Delay Stage, Correction MUX, and Coarse ROM as labelled in figure 8.) occuy about the same area as the 7-bit fine quantizer and its encoding logic (Folding Ams, Cycle Pointer, Fine Encoding, and Error Correction in figure 8.), thus confirming the original remise by which conversion was artitioned between the two stages (see section.3. and figure.7). The inut and interstage T/H circuits are located at the to of the chi along with the residue amlifier. These are the most sensitive analog comonents in the A/D converter and are therefore intentionally located as far away as ossible from digital comonents and from the outut buffers. The coarse quantizer

301 70 Chater 8 Performance T/H Coarse Ladder Coarse Latches & DAC Switches Res Am DAC T/H Folding Ams 4064µm Delay Stage Cycle Pointer Fine Encoding Correction MUX Error Correction Coarse ROM Outut Buffers 488mm Figure bit A/D converter with constituent comonents highlighted. Die size is aroximately 4 mm X 4 mm (60 mil X 60 mil). Analog inut is at to, left of chi. Digital oututs are at bottom. is on the left side of the chi with the fine quantizer on the right. The reconstruction DAC occuies the center of the die in all 3 imlementations, and the outut buffers fill the bottom of the layout. The 0-bit outut word from the converter is Gray coded and includes one extra bit to indicate an overflow or underflow condition. Each outut latch switches a differential air which drives comlementary oen-emitter transistors. These outut devices can be terminated off-chi by differential ECL receivers. Thus, the on-chi outut drivers are comatible with standard ECL logic levels as are the samle-clock inuts. The analog inut circuitry rovides 50 Ω termination resistors from both comlementary inut nodes to ground and accets ground-centered signals.

302 8. Circuit Layout 7 The version of the A/D converter utilizing the nominal DAC layout (Fig. 8.) includes Figure 8.. Die hotograh of 0-bit A/D converter with nominal DAC layout. Unused area surrounding DAC degeneration resistors is reserved for use in other ADC versions. significant unused silicon surrounding the DAC degeneration resistors (as shown in figure 8., the DAC occuies the center ortion of the circuit). This area is reserved to accommodate the larger DAC layouts from other versions of the ADC chi. In the version of the converter using a commoncentroid reconstruction DAC (Fig. 8.3) this area is nearly filled, and in the version incororating a trimmable DAC (Fig. 8.4) the area is comletely utilized. In fact, the excessively large size of trimmable resistors is a significant imediment to their widesread use. Since the die-size and ad

303 7 Chater 8 Performance Figure 8.3. Die hotograh of 0-bit A/D converter with common centroid reconstruction DAC layout. locations are identical for all versions of the converter chi, ackaging and testing techniques were also consistent among the different versions. Each chi has 00 ads, but many are used solely to monitor internal bias voltages during testing with custom wafer robes. Therefore, the chis were bonded in standard ceramic 68-in leaded chi-carrier (LCC) ackages. The three versions of the 0-bit converter shared a common reticle along with the 8-bit converter so that only one mask set was required to fabricate all four circuits. No JFETs or PNP biolar devices are included on any of the four chis ensuring that the circuit design and layout are alicable to generally available silicon biolar rocesses.

304 8. Test Methodology 73 Figure 8.4. Die hotograh of 0-bit A/D converter with trimmable reconstruction DAC layout. 8. Test Methodology The A/D converter chis were tested by sulying sinusoidal inut signals and ECL comatible clocks to the device under test (DUT) and caturing the resultant digital outut data in high-seed memory for later evaluation by comuter. The test set-u used for this urose (Fig. 8.5) sulies low-noise, sinusoidal analog inut signals which are aroriately filtered to reduce harmonics and which are hase-locked to low-noise, fast rise-time samle clocks. Passive haseslitters generate differential analog inut signals in resonse to the single-ended versions emanating from the frequency synthesizers. Digital data is catured in high-seed memory and later downloaded to a laboratory comuter for analysis. Additionally, a high-seed, 0-bit DAC

305 74 Chater 8 Performance Power Sulies HP 866 Freq. Synth. Analog Inut 0 MHz Reference HP 866 Freq. Synth. HP 866 Freq. Synth. Σ Colby PG5000 Pulse Gen. BPF Clock DUT 0 0-Bit DAC Oscilloscoe Workstation GPIB Control Tek 9503 Fast Data Cache Sectrum Analyzer Figure 8.5. A/D converter test setu. All synthesizers are hase-locked to one master synthesizer. Pulse generator sulies ECL clock signal to DUT uon trigger from low hase-noise synthesized source. Four ulse generators are used to suly clocks to DUT, but only one is shown for simlicity. Off-chi reconstruction DAC is helful for real-time debugging of system. Digitized data is catured in fast, dee memory and analyzed on workstation off-line. reconstructs the digitized signal for analysis with an oscilloscoe and sectrum analyzer. The test set-u, a hotograh of which aears in figure 8.6, also includes comuter-controlled ower sulies and voltmeters to monitor bias voltages and ower dissiation. Both robed wafers and ackaged arts were tested using this set-u. To facilitate testing of many devices, a fixture with a low insertion-force socket was used when evaluating arts housed in the 68-in ceramic ackages described above. Several well-known analysis techniques enable characterization of A/D converter dynamic erformance from collections of digital outut data taken from the DUT in resonse to known inut signals. In articular, erforming the Fast Fourier Transform (FFT) on digitized waveforms generates the ADC s digital outut sectrum from which SNR, SFDR, and THD can be ascertained [], [], [3], [4]. Additionally, calculating histograms from large sets of outut data generated in resonse to inut signals with known robability density functions enables determination of the ADC s dynamic integral and differential linearity error (INL and DNL) [], []. Alternatively, INL

306 8. Test Methodology 75 Figure 8.6. A/D converter test setu. Synthesizers, ulse generators, sectrum analyzer, and filter bank are housed in rack on left. High-seed memory and workstation are on right. Power sulies, oscilloscoes, and test fixtures are on bench in rear. and DNL can be calculated from measurements of the actual ADC threshold levels. Such measurements are best erformed with the aid of a hardware tracking loo which encloses the A/D converter within a feedback loo to erform an integrated (and hence low-noise) measurement of the articular threshold level in question [], [5]. These analysis techniques allow calculation of ADC dynamic erformance without the intervention of a otentially error-rone reconstruction DAC and were utilized to characterize the ADCs described here. The reconstruction DAC in the test set-u above generates qualitative information for debugging and trouble-shooting, and does not affect the accuracy of the erformance data tabulated below.

307 76 Chater 8 Performance 8.3 Test Results Aroximately 70 die sites were robed and 5 ackaged arts tested for each of the three ADC versions. The robed die sites were all located on one wafer, and the ackaged arts were taken from a second wafer. No significant difference in erformance was noted between the three versions so distinctions among the three circuits will no longer be made. About 70% of the circuits tested exhibit the nominal erformance described here. The ADC dissiates 800 mw from +5 V and 5 V ower sulies, excluding off-chi ECL sulies which bias the outut devices. The +5 V ower suly is required only for the two T/H circuits. Although the converters erformed reasonably well at or beyond 00 Mss, reliable data could only be obtained at 75 Mss, and all of the data reorted below ertains to that samle-rate. Sectral analysis of digitized sinewaves using 89 oint FFTs and Hamming window filtering indicates dynamic erformance consistent with 0-bit oeration (Figs. 8.9 through 8.7). For 0 Relative Amlitude (dbc) fin 5.87 MHz fs 75 Mss FFT block size 89 S/(N+D) 59 db SFDR -77 dbc Frequency (MHz) Figure 8.7. Digital outut sectrum from A/D converter when samling a 5.87 MHz sinusoidal inut at 75 Mss.

308 8.3 Test Results Relative Amlitude (dbc) fin fin 5.87 MHz fs 75 Mss FFT block size 89 S/(N+D) 59 db SFDR -76 dbc 3fin Frequency (MHz) Figure 8.8. Digital outut sectrum from A/D converter when samling a 5.87 MHz sinusoidal inut at 75 Mss. a 5.87 MHz differential, full-scale inut sinusoid converted at 75 Mss, the ratio of signal ower to all other ower in the outut sectrum, the so-called signal-to-noise-lus-distortion or S/(N+D), is 59 db. Also, the surious-free dynamic range (SFDR), secified by the highest surious signal level relative to the fundamental, is nearly 80dBc. The sectra from figures 8.9 through 8.7 corresond to three different ADCs oerating at the frequencies secified above. All three devices give similar S/(N+D), aroximately 59 db, which closely aroaches the theoretical limit for a 0-bit ADC, 6 db. The SFDR is about 77dBc in all three cases. This figure falls short of the ideal for a 0- bit converter, 9N 90dB, but comares very favorably to the distortion erformance reorted for other 0-bit converters extant. When the analog inut frequency is increased toward the target Nyquist rate of 50 MHz, distortion increases as exected (Fig. 8.0). For a 49.6 MHz full-scale inut and a 75 Mss conversion rate, the S/(N+D) degrades only slightly to 56 db while the SFDR, dominated by the 3rd harmonic, degrades to 6dBc. The first several harmonics, although rearranged in osition

309 78 Chater 8 Performance 0-0 Relative Amlitude (dbc) fin fin 5.87 MHz fs 75 Mss FFT block size 89 S/(N+D) 59 db SFDR -75 dbc 3fin Frequency (MHz) Figure 8.9. Digital outut sectrum from A/D converter when samling a 5.87 MHz sinusoidal inut at 75 Mss. due to the effects of aliasing, are clearly visible above the noise floor in the sectrum lotted in figure 8.0. The 3rd harmonic is dominant as mentioned, followed by the nd harmonic located at 69dBc. Other low-order harmonics are discernible but are near 80dBc. The degraded S/(N+D), 56 db, is still greater than 9 effective bits and at 50 MHz surasses the erformance of any known monolithic 0-bit ADC regardless of ower dissiation. Likewise, the decreased SFDR at 50 MHz nonetheless reresents a significant imrovement in achievable erformance over any 0-bit A/D converter reorted to date. Integral linearity error (ILE) and differential linearity error (DLE), also known as integral non-linearity (INL) and differential non-linearity (DNL) resectively can be calculated from histograms of ADC outut data in resonse to signals with know robability density functions [], []. By using this histogram method on data collected from the ADC when digitizing a 5.87 MHz sinusoid at 75 Mss the DNL and INL lotted in figures 8. and 8. resectively result. Peak DNL is less than / LSB and is for most thresholds below 0. LSB. The root-mean-square (rms)

310 8.3 Test Results 79 0 Relative Amlitude (dbc) fin 49.6 MHz fs 75 Mss FFT block size 89 S/(N+D) 56 db SFDR -6 dbc 3f f 6f 9f 8f 5f 4f 7f Frequency (MHz) Figure 8.0. Digital outut sectrum from A/D converter when samling a 49.6 MHz sinusoidal inut at 75 Mss. DNL is aroximately 0. LSB. Both of these figures are consistent with 0-bit linearity and indicate that the nonuniform interolation scheme used to eliminate threshold errors in the fine quantizer works effectively as does the interstage gain-matching aroach. Peak INL is below 3/4 LSB and for most thresholds is less than / LSB. Again, this uniformity of threshold lacement confirms the validity of the design techniques invoked to attain 0-bit oeration with very low comlexity and ower dissiation. When the inut frequency is increased from 5.87 MHz to 49.6 MHz, the threshold uniformity degrades slightly. Plots of the DNL and INL calculated from the histogram technique at this frequency are shown in figures 8.3 and 8.4 resectively. Peak DNL is still well below / LSB, and rms DNL is virtually unchanged from the 5.87 MHz case. INL no longer remains below 3/4 LSB, extending to 0.8 LSB for a very few codes. This henomenon is robably caused by T/H distortion since the location of the ADC thresholds is indeendent of the analog inut frequency.

311 80 Chater 8 Performance Threshold Error (LSB's) Threshold Number (X000) Figure 8.. Differential linearity as measured by a histogram test with f in 6MHz and f s 75Mss. A stringent test on A/D converter oeration, called a beat-frequency test, entails driving the T/H with an analog inut frequency close to / the samle rate. Under these conditions, the inut signal traverses across the maximum number of thresholds between successive samles. Therefore, signal slew-rates within the circuit are maximized resulting in greater distortion than in other modes of oeration. By alying the digital outut from the A/D converter to a reconstruction DAC, the resultant signal can be dislayed on an oscilloscoe exosing any signs of faulty oeration such as missing codes. A beat frequency test erformed on this ADC oerating at 75 Mss and with the analog inut set to MHz results in the oscilloscoe waveform deicted in figure 8.5. To obtain this image, the outut data stream from the ADC was decimated by before being alied to the reconstruction DAC. This oeration is necessary because otherwise an enveloe signal will be dislayed. Such an enveloe results under near-nyquist conditions because the A/D converter will samle a sinusoid eak of one olarity, followed on the successive samle by a sinusoid eak of the oosite olarity. For this reason, a test like that described here is sometimes called an enveloe test. When decimating by, every other samle is removed from the data stream so that

312 8.3 Test Results 8 Threshold Error (LSB's) Threshold Number (X000) Figure 8.. Integral linearity as measured by a histogram test with f in 5.87MHz and f s 75Mss. successive samles roduce adjacent voltages. Note that the frequency difference from Nyquist, that is f in f S, gives the frequency of the resultant waveform. The waveform shown in figure 8.5 shows no signs of distortion or missing codes even under the stressful conditions selected. The fidelity of the beat frequency waveform imlies that the T/H circuit can adequately track highfrequency inuts without distortion due to slewing effects, and that the quantizer can adequately track a voltage transition equal to its full-scale-range in one samle eriod.

313 8 Chater 8 Performance Threshold Error (LSB's) Threshold Number (X000) Figure 8.3. Differential linearity as measured by a histogram test with f in 49.6 MHz and f s 75 Mss.

314 8.3 Test Results 83 Threshold Error (LSB's) Threshold Number (X000) Figure 8.4. Integral linearity as measured by a histogram test with f in 5.87 MHz and f s 75 Mss.

315 84 Chater 8 Performance Figure 8.5. Beat frequency test. f S 75 Mss, f in MHz. ADC outut is decimated by then alied to reconstruction DAC and dislayed on oscilloscoe. References [] Hewlett Packard, Dynamic Performance Testing of A to D Converters. Product Note 580A. [] J. Doernberg, H. Lee, and D. A. Hodges, Full-seed testing of A/D converters, IEEE Journal of Solid State Circuits, vol. SC-9, , Dec [3] G. Pretzl, Dynamic testing of high-seed A/D converters, IEEE Journal of Solid State Circuits, vol. SC-3, , June 978. [4] T. E. Linnenbrink, Effective bits: Is that all there is?, IEEE Transactions on Instrumentation and Measurement, vol. IM-33, , Mar [5] J. J. Corcoran, T. Hornak, and P. B. Skov, A high-resolution error lotter for analog-todigital converters, IEEE Transactions on Instrumentation and Measurement, vol. IM-4, , Dec. 975.

316 Chater 9 8 Bit A/D Converter The fine quantizer from the 0-bit ADC incororates folding, interolation, and analog encoding to achieve efficient, high-seed oeration. This building-block, suitably modified, forms the quantizer of the 8-bit A/D converter described here. The inut T/H from the 0-bit ADC recedes this quantizer to ensure accurate digitization of dynamic signals. A brief descrition detailing the architecture of this comosite A/D aears next, followed by discussion of the converter s measured erformance. 9. Architecture Since the 8-bit ADC (Fig. 9.) derives from its 7-bit redecessor (Fig. 6.7), the two architectures share most features, differing in only two asects. First, the 8-bit ADC features a T/H to cature dynamic signals, and second, its interolation factor is doubled (as is the comlexity of succeeding stages), thereby increasing the converter s resolution by one bit. The resolution, N, of the converter derives from N A F I (9.) where A is the number of folding amlifiers used, F is the number of folds er sinewave, and I is the interolation factor. For the 8-bit quantizer imlemented, A, F 8, and I 6;

317 86 Chater 9 8 Bit A/D Converter X 8 X Sinewave Generators Folds er Sinewave Times Interolation Vin T/H Differential Reference Ladder (6 tas) I Q Nonuniform Differential 6X Interolation Ladder Analog Encoding and Comarators (6 Bits) Digital Encoding & Error Correction Digital Outut (8 Bits) Cycle-Pointing Coarse Quantizer (3 Bits) Figure bit A/D converter architecture. T/H derives from inut T/H in 0-bit ADC. Quantizer is based uon 7-bit fine quantizer, also from 0-bit converter. therefore, A F I (9.) as exected. The increased interolation factor, I, comared to the 7-bit case roughly doubles the number of comarators necessary along with the comlexity of the succeeding logic. Whereas the differential reference ladder and folding amlifiers are identical among the two quantizers (owing to the fact that A and F are equal), the die hotograh (Fig. 9.) indicates that the analog and digital encoding banks are twice the size of those in the 7-bit quantizer (see figures 6.0 for comarison). Even with this increase in comlexity, the A/D chi still requires only comarators: 7 to digitize the interolated sinusoids and 4 to form the cycle ointer. These comonents are visible when the overlaid text is removed from the die hotograh (Fig. 9.3). The entire converter utilizes only aroximately 000 transistors and the fabricated die occuies about 3mm 3mm ( 0mils 0mils ).

318 9. Performance 87 T/H Coarse Quantizer Differential Ladder & Folding Amlifiers Interolation Ring Analog Encoding Digital Encoding 3056mm Error Correction Outut Buffers 35mm Figure bit A/D converter with overlays to indicate location of constituent comonents. 9. Performance The 8-bit converter chis were tested using the same set-u and algorithms as the 0-bit A/D. Different wafer robe cards and test fixtures were necessary to accommodate the smaller die size and number of ads required for the 8-bit chi. Again, aroximately 70 die sites were robed and 5 ackaged arts tested. The ADC dissiates 550 mw from +5 V and 5 V sulies, but only the inut T/H circuit requires the ositive suly voltage. As in the 0-bit converter, digital inuts and oututs are comatible with ECL logic levels, while the analog inut rovides 50 Ω terminations for a ground-centered differential signal.

319 88 Chater 9 8 Bit A/D Converter Figure 9.3. Die hotograh of 8-bit A/D converter. FFT analysis of digital outut data rovides the corresonding sectrum generated by the A/D converter. This outut sectrum can be evaluated to ascertain SNR and harmonic distortion. When erformed over an array of inut and samle frequencies, such analysis comletely characterizes ADC erformance. FFT analysis on digitized data from the 8-bit converter generated the lots of SNR and harmonic distortion shown in figures 9.4 through 9. below. This data covers samle rates from 5 Mss to 00 Mss along with inut frequencies from.5 MHz to the Nyquist rate. Each lot includes measurements for nominal ower suly voltages and for ower suly variations of +7% and 7%. The data contained in these curves should be comared to ideal erformance for an 8-bit quantizer which includes: