ROM-Based Finite State Machine Implementation in Low Cost FPGAs

Transcription

1 ROM-Based Fiite State Machie Imlemetatio i Low Cost FPGAs I. García-Vargas, R. Sehadji-Navarro, G. Jiméez-Moreo ad A. Civit-Balcells Deartameto de Arquitectura y Tecología de Comutadores Uiversidad de Sevilla Sevilla, Sai {igacio,raouf,gaji,civit}@atc.us.es P. Guerra-Gutiérrez Deartameto de Igeiería Electróica Uiversidad Politécica de Madrid Madrid, Sai guerra@die.um.es Abstract This work resets a techique for the resource otimizatio of iut multilexed ROM-based Fiite State Machies. This techique exloits the do t care value of the iuts to reduce the memory size as well as multilexer comlexity. This techique has bee alied to a ublicly available FSM bechmarks ad imlemeted i a low-cost FPGA. Results have bee comared with tools suorted ROM ad stadard logic cells imlemetatios. I a sigificat umber of test cases, the roosed techique is the best desig alterative, both i resource requiremets ad seed. I. INTRODUCTION The cocet of the Fiite State Machie (FSM) is at the very cetre of cotrol ad comutig theories ad rovides a excellet abstractio framework for the defiitio of comlex cotrol-domiated automata. Deedig o the alicatio ad system comlexity, FSMs are imlemeted with microcotrollers, sigal rocessors (DSP) or rogrammable logic. This work deals with the efficiet imlemetatio of FSMs o rogrammable logic makig use of the embedded memory. I the last decade Field Programmable Gate Array (FPGA) have evolved from a relacemet of glue-logic to a serious cometitor of comlex alicatio secific itegrated circuits (ASIC). This has bee ossible through the mass roductio of submicrometer techologies, which have eabled the itegratio of thousads of elemetary cells i a sigle device. Amog the elemets owadays itegrated i these devices, embedded sychroous memory blocks (RAM) have show to be a sigificat breakthrough i may digital sigal rocessig ad etworkig alicatios. However, RAM blocks may also be used for other tasks, such as the imlemetatio of sequetial circuits. This fact has motivated a growig iterest o the imlemetatio of ROM-based Fiite State Machies (FSM) [,,3,4,5]. I fact, the latest versios of Xilix ISE Foudatio iclude the otio of limited maig of sequetial logic ad FSMs ito o-chi memory [6]. Wheever a FPGA is cosidered for the imlemetatio of a comlex FSM, circuit otimizatio must be addressed i order to coe with the limited umber of available resources. The availability of ew o-chi modules such as memories rovides ew alteratives to cotroller sythesis. FSM imlemetatio with embedded ROM blocks rovides some beefits comared to sythesis o logic cells. The maximum clock frequecy of a FSM imlemeted i a ROM block is ideedet of its comlexity. Moreover memory blocks rovide cotrol sigals that allow for module deactivatio whe the FSM is iactive, rovidig a efficiet mechaism for ower savig. I ay case, it has bee roved that comlex FSMs cosume less ower whe imlemeted as memory blocks [4]. However, the ROM imlemetatio of FSMs oses a sigificat roblem: If o otimizatio is cosidered, memory size grows exoetially with the umber of iuts ad the umber of state ecodig bits. This is a critical asect, as memory requiremets may easily exceed the available o-chi RAM eve with a simle FSM. I order to coe with memory size, additioal resources are itroduced to trade ROM size with logic [,3,4,7]. Some of the reviously referred techiques reduce the ROM address bitwidth by multilexig FSM iuts. This aroach is useful with those FSMs where the curret state is oly fuctio of a subset of the iuts. Multilexers select for each state oly those iuts that are of relevace, thus reducig the umber of addresses i the ROM. With this scheme, memory size is exchaged for multilexers, modules that are efficietly imlemeted with moder FPGAs [8,9]. As a examle, a 3: multilexer takes oly two Cofigurable Logic Blocks (CLB) of a Xilix Sarta-3 []. Moreover, some FPGA families rovide tristate buffers, allowig the imlemetatio of wired multilexers that take o additioal logic [,]. This works resets a techique based o iut multilexig with the aim of reducig resource eeds, ot oly i memory size but i the umber of multilexers as well. Ulike revious state-of-the-art techiques, which oly reduce the umber of /7/$. '7 IEEE 34 Authorized licesed use limited to: Uiv Politecica de Madrid. Dowloaded o Setember 5, 9 at :7 from IEEE Xlore. Restrictios aly.

2 iuts, the roosed aroach exloits multilexig to reduce both the umber of iuts ad the umber of bits required to code the machie states. Additioally, i order to simlify multilexer comlexity, a otimizatio algorithm is alied to reduce the umber of iuts of each multilexer. As it is show i the results sectio, this ste will also have a imact o memory size, as multilexer cotrol bits of each state are also stored i the memory. This aer is structured as follows, the secod sectio details the roosed techique, whose results with MCNC bechmark [] are aalyzed i the third sectio. The work closes with coclusios ad future work. II. TECHNIQUE DESCRIPTION The FSM is abstracted as a 5-tule (X, Y, S, f, g) where X, Y ad S are fiite collectios of the iut, outut ad state variables; f:x S S is the trasitio fuctio that rovides the ext state s j for the give iuts ad the curret state s i ad g:x S Y is the outut fuctio that comutes the machie outut for the give iuts ad curret state. FSMs are usually rereseted as State Trasitio Diagrams (STD). These diagrams are treated as directed grahs, where each vertex is a machie state ad each arc (s i, s j ) reresets a trasitio betwee curret state s i ad ext state s j. Additioally, each arc is labelled as x/y with s j =f(x,s i ) ad y=g(x,s i ). These cocets are summarized i Fig. a, which shows a STD for a simle FSM. The STD reresetatio is a commoly used to summarize ay FSM behaviour; however for a roer descritio of the roosed techique it is more coveiet to rereset the FSM i the form of a State Trasitio Table (STT). The STT, as show i Fig. b, is table whose rows rereset trasitios which are exressed as the 4-tule (i, s, s, out), which corresod to the iuts, reset state, ext state ad outut variables. It is obvious that the STT highlights the ROM-ability of the FSM. Fig. shows the referece architecture for the hardware sythesis, which may be see as a direct imlemetatio of the STT. Each word of the memory will store the oututs ad the ext state, while address is determied by the iuts ad the curret state, uder this assumtio the size of the required memory is: m+ х ( + ) () where m is the umber of iuts, the bitwidth of the coded state ad is the umber of oututs. Equatio () shows that the memory eeds are exoetial with the umber of iuts ad state codeword size. For this reaso, if o additioal measure is take, eve a simle FSM may easily take u a uaccetable amout of memory. I those FSMs where the ext state ad outut are fuctio of a subset of the iuts, ROM size is reduced by the iut multilexig techique, whose referece architecture is show --/ --/ S --/ --/ (a) S S --/ -/ -/ i s a b c s out - - s s - - s s - s s - s s - - s s - - s s - - s s i i i i i i is i s is s out - a - s c b s - s - a s c b s - c s c b s c b s c b - s - a s - s - a s - s - c s (c) i i i i i i is i s is s out a s c b s a s a s c b s c s c b s c b s c b - s a s c s a s c s c s (d) Fig.. FSM examle: (a) STD, (b) STT, (c) ESTT, (d) ESTT reresetatio after state ecodig bit reductio. i Fig. 3. The multilexer bak selects for each state the subset of iuts that are of iterest, thus reducig the umber of sigals that cotribute to the memory address word. Two alterative strategies are ossible for the multilexer cotrol, either the state codeword is used (Fig. 3a) or additioal cotrol bits are stored i the memory (Fig. 3b). The first otio X ROM m+ ( + ) g Y m REGISTER f (b) Fig.. ROM-based FSM imlemetatio. 343 Authorized licesed use limited to: Uiv Politecica de Madrid. Dowloaded o Setember 5, 9 at :7 from IEEE Xlore. Restrictios aly.

3 X g Y m MULTIPLEXERS m ROM m + ( + ) REGISTER f (a) has the advatage of reservig memory size; however icludig ew cotrol bits i the memory may allow multilexer comlexity reductio ad rovide a overall FSM simlificatio. Therefore the roosed techique selects the secod alterative. I this case, ROM size is give by the followig exressio: m + х ( + + r) () where m is maximum umber of selected iuts, is the umber of oututs, the state codeword bitwidth ad r the umber of bits devoted to multilexer cotrol. I the articular case where the multilexer is cotrolled by the state code, r is equal to zero. The ability of the techique to reduce memory size is based o the fact that m is equal or smaller tha m. However, the actual value is determied by the state that is sesitive to the highest umber of iuts. Therefore, such techique will yield bad results i FSMs where oly a reduced fractio of states are sesitive to a high umber of iuts. I the worst case, a sigle state which is sesitive to all iuts will revet ay ROM simlificatio. The techique herei described solves this roblem with a twofold aroach: o oe had iut multilexig is used i order to reduce both the umber of iuts (m) ad the state bitwidth (), o the other a otimizatio algorithm is alied i order to reduce the umber of bits used i the multilexer cotrol (r). This way overall comlexity of the FSM is miimized. We will defie those iuts which ifluece o a articular state as state effective iuts (SEI). The SEI umber is differet for each state, but the umber of iuts selected by a multilexer is fixed, therefore i each state the cotrol multilexer selects ot oly the SEI but also some iuts that r (b) X m MULTIPLEXERS h r m ROM m + ( r + + ) g REGISTER Fig. 3. FSM imlemetatio with iut multilexig: (a) multilexers cotroled by the state codeword, (b) cotrol bits stored i ROM. Y f have o ifluece o the curret state, these iuts will be deomiated as do t care selected iuts (DCSI). I order to reduce state codeword bitwidth, the roosed techique will artially use the DCSI for the state codificatio. I order to roerly rereset the iut multilexed FSM (FSMIM), it is madatory to exted the iformatio stored i the STT. Each row of the Exteded State Trasitio Table (ESTT) will store a 6-tule (i, is, s, is, s, out), where the ew items are the reset (is) ad ext (is) iut selectio. For each state, is stores iformatio about the selected iuts ad i cotais the actual value of these iuts. The iformatio about which subset of iuts will be selected for the ext state s is stored i is. Ulike FSMs, whose states are oly idetified by the s word, FSMIMs are idetified by the -tule (s, is). Fig. c shows the ESTT of the FSM corresodig to the STD i Fig. a. It is observed that the first two rows of the ESTT the iut selectio for state s is -a. That meas that the first iut is a DCSI ad the secod iut is the a iut of the origial FSM. It is said that two states share a DCSI if it selected by both states ad with the same multilexer. With this covetio, two states sharig a DCSI may be coded settig the DCSI value to i oe state ad i the other. I formal otatio, let A ad B to be two states sharig at least oe DCSI, with (PS j, PIS j ) as the -tule that uivocally idetifies state A ad (PS k, PIS k ) idetifies the state B. Both states may be coded with the same PS if they differ i the PIS havig a differet code at the shared DCSI. Fig. d shows the states (s, -a) ad (s, -c), which have bee coded usig the same code s for the state ad cosiderig a differet value for the shared DCSI ( is chose for s ad for s ). The fial states are (s, a) ad (s, c). Multilexer comlexity, ad also the umber of the required cotrol bits, deeds o the way iuts are assiged to each multilexer. As a examle, Fig. 4 shows two ossible assigmets related to the examle FSM of Fig.. I order to fid a otimum artitioig, it has bee decided to assig each iut to a sigle multilexer. For examle, i the Fig. 4a, where the iut c is liked to two multilexers, the resultig logic turs out to be more comlex tha Fig 4b. This is accomlished by guarateeig that two iuts actig uo a give state do ot share the same multilexer (deedet iuts). I the Fig. 4b, iuts b ad c are deedet iuts ad are assiged to differet multilexer. I this case, the otimizatio roblem cosists o maximizig the umber of ideedet iuts for each multilexer. This roblem may be modelled as a Maximum Ideedet Set Problem (MISP) [3]. I case a solutio is ot foud, costraits will be relaxed by allowig the assigmet of deedet iuts to the same multilexer. 344 Authorized licesed use limited to: Uiv Politecica de Madrid. Dowloaded o Setember 5, 9 at :7 from IEEE Xlore. Restrictios aly.

4 a b e c s s c i i b c b c b c e i i c b c b c b (a) (b) Fig. 4. Examle of multilexer bak: (a) without simlificatio, (b) with simlificatio III. EXPERIMENTAL RESULTS The roosed techique has bee alied to the MCNC bechmark []. O oe had, the techique ability to otimize ROM size ad multilexer bak comlexity is show. O the other, i order to assess the quality of the otimized imlemetatio i terms of actual resource use ad maximum clock frequecy, several imlemetatios with a commercially available FPGA have bee carried out. FSMs have bee sythesized o a Xilix Sarta-3 xc3s5 with the device vedor s referece tool ISE Foudatio 7.i (Xilix Ic. Sa Jose, CA, USA). Imlemetatio results obtaied with the FSMIM have bee comared agaist alterative FSM imlemetatios where either (a) ROM sythesis without otimizatio, (b) a stadard imlemetatio o logic cells or (c) tool suorted ROM sythesis are cosidered. The four alterative imlemetatios will be referred as FSMIM, ROM, ISE-LUT ad ISE-RAM resectively. The otimizatio rocess cosists of two stes. The first ste is the Multilexer Bak Comlexity Simlificatio (MBCS) ad the secod is the State Ecodig Bit Reductio (SEBR). Table I shows the results after both stes, where ROM size is comared to the case where otimizatio is erformed ad fially the overall reductio factor is summarized. These results show that the use of a o-comlex multilexer bak rovides a sigificat theoretical memory reductio (87% o average). The highest memory reductios are achieved for the s5, s8, s83 y scf FSM. For the cosidered bechmark, oly 9% of the FSMs require multilexers with more tha 4 iuts. I order to evaluate the usefuless of the SEBR ste, results are also comared agaist iut multilexig aloe. Fig. 5 shows the ROM size reductio after the MBCS ad the SEBR stes. Dark gray bars show memory reductio after the MBCS ste, while light gray bars reflect the additioaly size imrovemet rovided by the SEBR ste. It is observed that, although multilexig rovides a sigificat imrovemet, the SEBR yields a additioal 67% average reductio that i half the cases is as high as 7%. a c s b I four cases (keyb, ous, s ad s7) the SEBR ste has a dramatic imact o memory reductio. It is imortat to highlight that i the articular case of the keyb, ous, s ad s7 test FSMs, the MBCS by itself yielded o memory reductio ad it is oly due to the SEBR. Table II shows the average resource requiremets of differet imlemetatios. The FSMIM techique requires a average of.76 BRAMs, the ISE_BRAM 6.3 ad the ROM techique 3.6. Thaks to the reductios rovided by the roosed techique, the umber of bechmark FSMs that ca be sythesized ito the smallest member of the Xilix Sartae e TABLE I OPTIMIZATION RESULTS FSM FSMIM Name ROM ROM MUX Bak Size Size Reductio (Kbits) (Kbits) (%) (Iut Number) bbsse , cse ,, ex ,4,4,,, ex , keyb , mark ,, ous ,,, laet ,,,4,4 ma ,,,, s ,,,, s ,4,, s ,4,, s s , s ,7 s ,6,4,4,,, s ,6,4,4 sad ,4,4,4,,4, scf ,3,4,4,,,, sse , styr ,4,, Fig. 5: Imact of each otimizatio ste o the fial desig 345 Authorized licesed use limited to: Uiv Politecica de Madrid. Dowloaded o Setember 5, 9 at :7 from IEEE Xlore. Restrictios aly.

5 TABLE II RESOURCE USE SUMMARY FSM ISE-LUT ISE-BRAM ROM FSMIM LUT LUT BRAM BRAM LUT BRAM bbsse cse ex ex keyb mark ous 9 laet ma s s s s7 s s s s sad scf sse styr family (with 4 BRAMs) is doubled (86% i FSMIM vs. 43% i the best case of other ROM-based imlemetatios). This sigificat imrovemet is at the cost of small umber of looku tables (LUT). The average umber of LUTs of the FSMIM imlemetatio is as low as 5, while u to LUTs are required i a stadard logic sythesis of the FSM (ISE-LUT). I tests sl488 ad sl494, BRAM reductio is higher tha 97% with the extra cost of oly 5 LUT. Some of the FSMs i the testbech (s5, s8, s83 ad scf) could ot be imlemeted ito the FPGA with ISE-BRAM ad ROM imlemetatio, due to the high memory requiremets, desite the fact that the selected model is the biggest of the family with 4 RAM blocks. I four cases (ex4, mark, ous ad s7) the traditioal aroach oly requires a sigle RAM block ad therefore there is o aaret beefit i usig the roosed techique ad this situatio may be commo due to the relatively high size of the idividual RAM block (8Kb). However, as the o-chi RAMs are double-ort memories, it is feasible to imlemet two FSMs i the same block, makig use of the secod address/data orts to access the available sace [5] ad i this case there is still motivatio to reduce memory size. Fig. 6 shows the FSM maximum oeratig clock frequecy after lacemet ad routig with the differet techiques uder cosideratio. I 8% of the test cases, the FSMIM frequecy is higher that the LUT-based imlemetatio, beig the imrovemet higher tha 57% i a fourth of the test cases. These results show that the FSMIM is a valid alterative to stadard cell based FSM imlemetatio. Comared to the BRAM aroaches, the FSMIM allows for higher oeratig frequecy i 59% of the cosidered scearios i the ROM case ad 8% i the ISE-BRAM case. This is Fig. 6. Maximum Oeratio Frequecy mostly due to the distributio of the RAM blocks withi the device. Overall, the FSMIM aroach rovides better results both i area ad frequecy i 9% of the test cases. IV. CONCLUSION AND FUTURE WORK This work has reseted a techique that achieves a sigificat reductio i the umber of required o-chi memory blocks for the imlemetatio of a FSM i a FPGA, makig use of a reduced umber of extra logic resources, such as look-u tables. This block reductio has a ositive imact o the maximum clock frequecy of the FSM. The roosed techique has bee comared agaist other alteratives, makig used of a stadard FSM bechmark. Results show that i a sigificat umber of test cases the roosed techique is the best desig alterative, both i resource requiremets ad seed, eve whe comarig agaist traditioal cell based FSM imlemetatios. The roosed imlemetatio is ot limited to low cost FPGAs, but ca be used by ay FPGA device that icludes RAM blocks. As future work, it seems iterestig to study the erformace of the techique with the latest Xilix architecture based o 6-iut LUTs (Virtex-5) that allows for a more efficiet multilexor imlemetatio. REFERENCES [] R. Sehadji-Navarro, I. García-Vargas, G. Jimeez-Moreo ad A. Civit- Ballcels ROM-based FSM imlemetatio usig iut multilexig, Electroics Letters, Vol. 4, N., Setember 4 [] Rawski M., Selvaraj H., ad Łuba, T.: A Alicatio of Fuctioal Decomositio i ROM-Based FSM Imlemetatio i FPGA Devices, Proc. Euromicro Symosium o Digital System Desig, 3, Belek-Atalya (Turkey), Authorized licesed use limited to: Uiv Politecica de Madrid. Dowloaded o Setember 5, 9 at :7 from IEEE Xlore. Restrictios aly.

6 [3] Valery Sklyarov, Sythesis ad Imlemetatio of RAM-Based Fiite State Machies i FPGAs, Proc. Field Programmable Logic ad its alicatios (FPL),, [4] Aurag Tiwari ad Kare a. Tomko, Savig Power by Maig Fiite- State Machies ito Embedded Memory Blocks i FPGAs, Desig, Automatio ad Test i Euroe Coferece ad Exhibitio Volume II (DATE'4), Feb. 4 [5] Garcia, E.: Xilix: Creatig Fiite State Machies, Xcell Joural,, 38 [6] Xilix, Ic: ISE Foudatio ( [7] Katz, R. H.: Cotemorary Logic Desig (The Bejami/Cummigs Publishig Comay, Ic., Califoria, 994) [8] Altera, Cor.: Stratix II Device Hadbook, 4, Ver.., Chater [9] Krueger, R.: Xilix Virtex Devices: Variable Iut LUT Architecture, The Sydicated, 4, Vol. 4, Issue I [] Xilix, Ic.: Usig Dedicated Multilexers i Sarta-3 Geeratio FPGAs, XAPP466 (v.) May, 5 [] Xilix, Ic.: XST User Guide, 5 [] McElvai, K.: IWLS'93 Bechmark Set: Versio 4., 993 [3] Garey, M. R. ad Johso, D. S. Comuters ad Itractability: A Guide to the Theory of NP-Comleteess. New York: W. H. Freema, Authorized licesed use limited to: Uiv Politecica de Madrid. Dowloaded o Setember 5, 9 at :7 from IEEE Xlore. Restrictios aly.