A new Power MOSFET Generation designed for Synchronous Rectification

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1 A New Power MOSFET Geeratio desiged for Sychroous Rectificatio A ew Power MOSFET Geeratio desiged for Sychroous Rectificatio Keywords R. Siemieiec, C. Mößlacher, O. Blak, M. Rösch, M. Frak, M. Hutzler INFINEON TECHNOLOGIES AUSTRIA AG Siemesstrasse 2 A-9500 Villach, Austria Tel.: Fax: ralf.siemieiec@ifieo.com URL: htt:// MOSFET, New switchig devices, Switched-mode ower suly, Simulatio, Measuremet Abstract Low-voltage MOSFETs are widely used i the sychroous rectifyig stages of ower sulies. To allow a high efficiecy i light-load coditios, the ower MOSFET ot oly eeds to meet geeral requiremets like low o-resistace, low gate charge ad good avalache caability, but must also have a low outut caacitace ad low reverse-recovery charge. The aer shows how those requiremets were met i our ewest geeratio of ower MOSFET startig with the 60 V class. Itroductio Several years ago the ucomig 80PLUS requiremets for SMPS (switched-mode ower suly) forced the desigers of ower sulies to rethik the cocet of the secodary side rectificatio. At that time covetioal diodes with a forward voltage dro of roughly 0.5 V were used. I combiatio with large outut currets these diodes geerate high coductio losses, leadig to a oor efficiecy level of the SMPS at high outut ower. The chage to sychroous rectificatio by usig stadard MOSFETs with low R DS(ON) was the solutio to icrease the efficiecy level above 80 % at 20 %, 50 % ad 100 % of the outut ower. Further desig stes like imroved PCB layout, ehaced subber etworks for better sikig behavior of the MOSFET or goig for lower R DS(ON) icreased the efficiecy level to a eak of aroud 90 %. However, the curret 80PLUS latium certificatio requires much more. The efficiecy for sigle outut PSUs (ower suly uits) with a AC iut voltage of 230 V (e.g. server PSU) has to be above 90 %, 94 % ad 91 % at resectively 20 %, 50 % ad 100 % of the outut ower. A otimizatio at full load could be eabled by usig the smallest available R DS(ON) for the SR (sychroous rectificatio) MOSFET, but this aroach does ot allow the highest erformace to be reached at low outut ower. To reach or exceed the 80PLUS latium certificatio i the comig years, it is essetial to have MOSFETs for sychroous rectificatio which have a well balaced ratio betwee switchig losses ad coductio losses. At the same time the absolute loss values eed to be extremely low. Alicatio requiremets Basics of Sychroous Rectificatio To desig a MOSFET which is erfectly suited to sychroous rectificatio, this alicatio eeds to be aalyzed i-deth to get a uderstadig of which arameters are imortat. I the followig a short overview is give, a detailed aalysis is reseted i a searate aer [1]. Power losses i the SR MOSFET must be searated ito load deedet coductio losses ad costat switchig losses. Coductio losses are determied by the R DS(ON) of the switch. They icrease with icreasig outut load of the ower suly. O the other had the switchig losses are costat over the whole outut load, ad are maily determied by the gate charge Q G ad the outut EPE Birmigham ISBN: P.1

2 A New Power MOSFET Geeratio desiged for Sychroous Rectificatio V RRM V DS I F ID V IN di/dt = cost. Q OSS time Q RR I RRM t IRRM t VRRM t RR Fig. 1: Simlified model of the tur-off rocess of a Sychroous Rectificatio MOSFET charge Q OSS. The gate-source-caacitace C GS eeds to be charged u to the gate drivig voltage at each tur-o ad will be discharged to groud at each tur-off. Cosiderig the tur-off rocess, the stored charge Q RR of the body diode must be removed ad the outut caacitace C OSS has to be charged u to the secodary side trasformer voltage, the iut voltage of the SR stage as exlaied i Fig. 1. This rocess results i a reverse curret eak I RRM which is liked to the overall iductace of the commutatio loo. The eergy stored i this iductace is trasferred to the outut caacitace as soo as the drai-source-voltage of the MOSFET V DS exceeds the iut voltage V IN with the voltage sike carryig this eergy. The amout of eergy is defied by the reverse-recovery charge stored i the body diode Q RR ad the charge stored i the outut caacitace Q OSS u to the trasformer voltage V IN ad is lost every switchig cycle. A high outut caacitace C OSS does ot oly geerate ower losses but also causes a large reverse curret eak as show schematically i Fig. 1. The higher the reverse curret eak I RRM, the higher the rate of voltage rise dv/dt, ad thus the tur-off voltage sike, will be. This high dv/dt ca also trigger a dyamic re-tur-o of the MOSFET by raisig the gate voltage above the threshold voltage due to the caacitive voltage divider C GD /C GS. To revet this a small outut caacitace C OSS, a o-critical ratio C GD /C GS ad a arrow tolerace of all MOSFET caacitaces are essetial. Otimizatio towards highest efficiecy To otimize the SR MOSFET for the highest efficiecy, a well balaced ratio betwee switchig losses ad coductio losses must be foud. At low outut loads the coductio losses oly lay a mior role while switchig losses are domiat. For higher loads the weightig of the losses is the other way aroud. To calculate the losses ad to get a idicatio how the techology will erform i the system, differet figures-of-merit (FOM) eed to be cosidered [2,3]. The FOM G is the roduct of the R DS(ON) ad the Q G, while the FOM OSS is the roduct of R DS(ON) ad Q OSS. As the caacitaces of a MOSFET are iverse roortioal to the R DS(ON), this roduct is fixed over the whole R DS(ON) rage of a give techology. As illustrated i Fig. 2 the coductio losses icrease liearly with higher R DS(ON). O the other had switchig losses icrease substatially at low R DS(ON) values. Cosiderig the total ower losses, a local miimum is foud. At recisely this oit, marked with a black dot i Fig. 2, the MOSFET geerates the lowest losses i a give system ad therefore the highest efficiecy is foud. Further otimizatio of a SR system caot be doe with this give MOSFET techology. Cosequetly, the mai goal of the ew SR MOSFET geeratio develomet was to move this oit of miimum losses to the bottom left corer i Fig. 2. This ca be achieved by a further massive decrease of the FOM G, which meas a reductio of switchig losses ad a reductio of coductio losses at the same time. This measure ca raise the whole system efficiecy both at low outut ower ad at high outut ower, makig it easier to meet the ew eergy efficiecy requiremets. EPE Birmigham ISBN: P.2

3 A New Power MOSFET Geeratio desiged for Sychroous Rectificatio coductio losses switchig losses total losses switchig loss domiated balaced oeratio Power Losses [W] coductio loss domiated O-Resistace [mohm] Fig. 2: Power losses er device vs. o-resistace i sychroous rectificatio for a give MOSFET techology (V IN = 30 V, V GS = 10 V, I = 15 A f = 125 khz) Device desig otimizatio Device Cocet Several years ago, the first geeratio of ower MOSFET emloyig the comesatio ricile based o a field-late cocet was itroduced [4]. The basic ricile to realize a area-secific oresistace well below the 1D silico limit is similar to the charge-comesatio i suer-juctio devices like the CoolMOS, as schematically show i Fig. 3a. Here the comesatio of -drift regio doors is realized by accetors located i -colums. I field-late tye devices, a isolated field-late rovides the mobile charges required to comesate the drift regio doors uder blockig coditios as idicated i Fig. 3b. Comared to a device usig a simle laar -juctio, the electric field ow also has a comoet i the lateral directio. Fig. 4 idicates the basic differeces i the electric field for a simle -juctio ad for the case where a field-late comesates the doors i the drift regio. As ca be see the field-late ricile leads to a almost costat field distributio i vertical directio, thereby reducig the ecessary drift regio legth for a give breakdow voltage. I additio, the drift regio doig ca be icreased. Both measures, the formatio of a suer-juctio as well as a field-late structure, ca sigificatly reduce the o-state resistace. -colum -colum thick oxide layer field late Fig. 3: a) Comesatio by -ad -colums b) Comesatio usig a field-late EPE Birmigham ISBN: P.3

4 A New Power MOSFET Geeratio desiged for Sychroous Rectificatio E y E y y y E x E x x x Fig: 4 a) Electric field for a -juctio Furthermore, the field-late electrode is coected to the source electrode of the MOSFET ad the gate is formed by a searate electrode. Therefore such a device structure ot oly offers a outstadig area-secific o-resistace, but also a low gate-charge. Fig. 5 idicates the reductio of the o-resistace which ca be achieved. It comares the resistace of the drift regio, curretly the major art cotributig to the total coductio losses of the device, for the case of a ideal -juctio ad for a comesatio device usig field-lates. The values for the comesatio device are either estimated usig a simlified 1D model or calculated usig 2D device simulatio [5]. Imrovemet of outut charge ad o-resistace b) Electric field for a field-late structure Desite all the advatages the itroductio of charge-comesatio is ievitably liked to a icrease of the outut caacitace C OSS ad the outut charge Q OSS due to the icreased doig desity comared to a stadard MOSFET. Here it is useful to cosider the reviously defied Figure-of-Merit FOM OSS = Q OSS x R DS(ON) sice from a alicatio oit of view the outut charge for a give oresistace is of iterest. A simle otimizatio towards the lowest ossible area-secific o-resistace by usig a smaller cell itch will lead to a degradatio of the FOM OSS. Alteratively, a reductio of the Q OSS is obviously ossible by a further reductio of the drift regio legth ad a lower drift regio doig, ad/or a decrease i the cell desity (i.e. icreasig the trech width etc.). Ufortuately, most Drift resistace R Drift x A [mω mm 2 ] D Si-Limit comesatio: 1D Model comesatio: 2D Simulatio Breakdow Voltage V BD [V] Fig. 5: Drift regio resistace vs. breakdow voltage EPE Birmigham ISBN: P.4

5 A New Power MOSFET Geeratio desiged for Sychroous Rectificatio Breakdow Voltage VBD Breakdow voltage becomes more ad more sesitive to trech deth Drift regio legth / trech deth Fig. 6: Breakdow voltage deedece o trech deth / drift regio legth for costat doig level of these measures will lead to a degradatio of the area-secific o-resistace ad will also affect the breakdow voltage of the device withi a give techology. Fig. 6 shows the fudametal deedecy betwee the breakdow voltage ad the trech deth ad the liked drift regio legth at a costat drift regio doig. As ca be see the realized breakdow voltage remais almost costat util the trech deth falls below a certai limit. Further reductio of trech deth ad drift regio legth results i a icreasig degradatio of the breakdow voltage. It is clear that rocess-related deviatios of the trech deth must be aroriately cosidered ad that for the highest yield i maufacturig withi a give techology it looks best to chose a target desig which always stays o the costat brach of the show deedecy. However, the key for further imrovemet of the MOSFET towards the reviously idicated requiremets is to realize a desig left of the costat brach of the breakdow voltage deedecy deicted i Fig. 6. Due to the icreased sesitivity of the breakdow voltage o trech deth ad drift regio legth, the mai measure for beig able to ot oly reduce the FOM OSS but also the areasecific o-resistace ad the gate-charge for faster switchig is the use of more advaced maufacturig rocesses. New maufacturig tools ad better lithograhy allow for smaller structures ad, essetially, lower toleraces through a imroved rocess cotrol. As a examle, the reductio of rocess-related deviatios i the trech deth from ±15% to oly ±5% Fieldlate Trech 2d geeratio, FOMoss otimized Fieldlate Trech 2d geeratio, RDS(o) otimized Fieldlate Trech 1st geeratio Stadard Trech FOMoss RDS(o) x A Fig. 7: Comariso of device erformace of 1st ad 2d geeratio of field-late trech MOSFET ad stadard trech MOSFET devices i the 60 V class EPE Birmigham ISBN: P.5

6 A New Power MOSFET Geeratio desiged for Sychroous Rectificatio allows a reductio of the target trech deth of 10%. Cosequetly the outut charge is reduced by 10% while the FOM OSS becomes eve smaller sice the o-resistace is also lower due to the shorter drift legth. Of course, the alicable measures are ot limited to the cotrol of the trech deth. The use of the imroved maufacturig setu also allows the reductio of the chael legth, which further cotributes to a imroved o-resistace. O the other had, better cotrol of the trech width results i smaller variatio of the mesa width, ad therefore the doig-related charge shows fewer fluctuatios. Sice this charge must be comesated by the field-late, this leads to a better cotrol of the breakdow voltage, givig more room to move to the left of the deedecy show i Fig. 6. I summary, imrovemets i the maufacturig tools ad a cosequet otimizatio of the imortat maufacturig rocesses allows for a clear reductio of the FOM OSS. The area-secific o-resistace ad the gate charge ca also be further reduced at the same time. Fig. 7 gives a comariso of the FOM OSS vs. R DS(ON) x A of the ucomig ew device geeratio with the redecessor geeratio ad devices emloyig a stadard trech cocet. Desite the clear imrovemet towards both, FOM OSS ad R DS(ON) x A, comared to the redecessor geeratio there are two articularly iterestig facts to ote. Firstly, the strog reductio of the outut-charge results i oly a mior icrease i the area-secific o-resistace comared to what would be achieved by a straightforward reductio of the o-resistace. Secodly, the FOM OSS of a otimized field-late comesatio device is as good as that of devices emloyig a stadard trech. Switchig erformace ad avoidace of dyamic tur-o As the roosed device techology is iteded for use i fast switchig alicatios, the absolute value of the gate-drai-charge Q GD ad its variatio is also imortat. The gate-drai charge Q GD (also kow as the Miller charge) ad the overall gate resistace R G are the mai factors cotrollig the switchig seed of the device. A small gate-drai-charge Q GD is therefore advatageous, but the variatio of this arameter over the whole maufacturig rocess should also be small. This is esecially imortat where devices are coected i arallel with each other, but a small rage of the Q GD value also allows the miimizatio of safety margis. Here the erformace of the ew techology also beefits from the reviously discussed imrovemets to the maufacturig rocess ad equimet. The better rocess cotrol ad the otimized device geometry results i a much smaller rage of the Q GD comared to the redecessor techology as idicated i Fig. 8. However, the use of ower MOSFETs for fast switchig alicatios comes with additioal risks. The most tyical oe is the dyamic tur-o. Observed maily, but ot exclusively, i hard-switchig toologies, very large dv/dt-values from drai to source may occur whe the device starts to block. This dv/dt coules to the gate via the caacitive voltage divider C GD /C GS ad could result i a dyamic tur-o of the device as exlaied i Fig. 9. I this case, a short circuit forms. Cosequetly, this leads to largely icreased losses i the MOSFET ad also i other affected devices, such as the trasformer Probability, F=(I-0.5)/N st geeratio 2d geeratio Normalized Q GD Fig. 8: Comariso of the rage of the gate-drai charge Q GD for 1 st ad 2 d device geeratio EPE Birmigham ISBN: P.6

7 A New Power MOSFET Geeratio desiged for Sychroous Rectificatio C GD I dv/dt C DS C GS Fig. 9 : Dyamic tur-o of a MOSFET by large dv/dt i a sychroous rectifier. The vulerability of a give MOSFET techology to dyamic tur-o ca be estimated usig the followig coditio: with V V Q GD,crit TH,mi DS,max C V C GS TH,mi < 1 dv = Q GD GD GD,crit (2) 0 Here, V TH,mi is the smallest secified threshold voltage, V DS,max is the maximum drai-source-voltage durig switchig (e.g. the voltage eak) ad Q GD,crit refers to the critical gate-drai-charge. Cosequetly, the gate-drai-charge of the MOSFET should be lower to avoid this effect. As i the case of the redecessor techology, the ecessary care was take that the coditio give by Eq. 1 is safely fulfilled ad that o dyamic tur-o is foud eve for the very high dv/dt which might occur i otimized, low-iductace circuits. Device erformace i target alicatios Simulatio ad measuremet setu To verify if the theory discussed above is alicable i a real alicatio, a test measuremet was doe i a laboratory setu. To obtai meaigful results, a 750W / 12V server ower suly uit with secodary side sychroous rectificatio, commercially available o the market, was take for verificatio. The toology is a hase-shift, full-bridge rectifier o the rimary side [6] with hardswitched, ceter-taed sychroous rectificatio stage o the secodary side as schematically show i Fig. 10. To get comarable results it is essetial always to have the same exteral laboratory coditios, such as costat temerature ad use of the same measuremet istrumets for miimized toleraces. For the measuremet of the AC iut of the ower suly, a Siemes ower aalyzer tye B6040 was used. The outut voltage was measured with a recisio data acquisitio uit tye Agilet 34970A, the curret was logged usig a high-curret shut resistor. To correctly aalyze the voltage overshoot of the SR MOSFET, it is imortat to measure the sigal as ear to the ackage as ossible, but ot o the PCB. This avoids ay ifluece of the arasitic stray iductaces which ca heavily affect the voltage sigal due to the high di/dt eviromet. Sice it is essetial i the develomet of a ew techology to kow as early as ossible how the ew device behaves i the target alicatio, a simlified sychroous rectificatio stage was imlemeted i a mixed-mode simulatio circuit usig Medici [7]. Both SR MOSFETs i this circuit as show i Fig. 10 are modeled by their full 2D structures. The iut voltage V IN reflects the voltage of the secodary side of the trasformer. A safe dead-time of 250s was chose for the gate voltages V GS1 (1) EPE Birmigham ISBN: P.7

8 A New Power MOSFET Geeratio desiged for Sychroous Rectificatio L STRAY,IN1 L OUT1 V GS1 R G1 Subber 1 R LOAD Primary side V IN V GS2 L STRAY,SOURCE1 L STRAY,SOURCE2 Subber 2 R G2 L OUT2 L STRAY,IN2 Fig. 10: Basic circuit for a hard-switched, ceter-taed sychroous rectificatio stage ad V GS2. The simulatios carried out reroduced the situatio for a give oeratig oit. The followig arameter values were used i the simulatios: R G1/2 = 2 Ω, L OUT1,2 = 10 µh, L STRAY,IN1,2 = 20 H, L STRAY,SOURCE1,2 = 2 H, R Subber1,2 = 2.7 Ω, C Subber1,2 = 10 F. Simulatio of voltage overshoot Fig. 11 comares the voltage overshoot (absolute values) i a sychroous rectifyig stage for the ew 60 V MOSFET ad the redecessor device as a result of simulatios ad measuremets i a real test circuit. Due to the lower outut charge of the ew device geeratio the voltage overshoot was clearly reduced over the full outut curret rage. These results cofirm the reviously discussed measures to imrove the device erformace. While the reductio i the overvoltage is equal i the measuremet ad the simulatio, the absolute values show a marked differece. The reasos are most likely caused by the simlificatios doe for the simulatio circuit, i.e. the icomlete cosideratio of all arasitic elemets i the real circuit fieldlate trech 1st geeratio, measured fieldlate trech 2d geeratio, measured fieldlate trech 1st geeratio, simulated fieldlate trech 2d geeratio, simulated VOVERSHOOT [V] Outut curret er device [A] Fig. 11: Comariso of the simulated ad measured voltage overshoot of the MOSFET i a SR stage EPE Birmigham ISBN: P.8

9 A New Power MOSFET Geeratio desiged for Sychroous Rectificatio Measured device erformace I the measuremet show i Fig. 12 the efficiecy is comared to the redecessor device ad a clear erformace imrovemet was gaied over the whole ower rage. The high-load efficiecy is imroved by 0.3 %, while at the same time the low-load efficiecy is 0.2 % better. This result was achieved by the reviously discussed imrovemet of the FOM G. Not oly the R DS(ON) but also the switchig charges like Q G ad Q OSS are much lower tha i the first geeratio device. Cosiderig a efficiecy level betwee 98 % ad 99 % of the sychroous rectificatio stage, a imrovemet of 0.3 % clearly hels the desigers of SMPS to reach their erformace targets fieldlate trech 1st geeratio fieldlate trech 2d geeratio ΔEfficiecy [%] Outut Power [W] Fig. 12: Measured device efficiecy i sychroous rectificatio As idicated before, voltage overshoots at tur-off of the SR MOSFET are a big challege, esecially for hard switched toologies. Desigers eed to esure that the level of this eak does ot exceed the maximum ratig of the device. This ofte requires the use of a subber etwork which is costly ad furthermore tyically decreases the erformace of the SMPS [8]. The subber i its easiest versio ΔVOVERSHOOT [V] fieldlate trech 1st geeratio -6 fieldlate trech 2d geeratio Outut Power [W] Fig. 13: Measured voltage overshoot i sychroous rectifier EPE Birmigham ISBN: P.9

10 A New Power MOSFET Geeratio desiged for Sychroous Rectificatio cosists of a series-coected resistor ad caacitor, coected i arallel to the drai ad source of the MOSFET as show i Fig. 10, ad is a sigificat source of ower losses. Ay reductio of the caacitace value imroves the efficiecy of the circuit. The measuremets of the sikig behavior i the PSU showed the clear imrovemet of the ew MOSFET geeratio comared to its redecessor techology over the full outut ower rage. This comariso is show i Fig. 13. A eak voltage reductio of u to 7 V at high outut ower is achieved. This o the oe had reduces the stress for the MOSFET itself leadig to imroved reliability, ad o the other had reduces the efforts ivolved i desigig the subber etwork. Coclusio This aer resets a ew geeratio of MOSFETs desiged to be used for sychroous rectificatio. To imrove the overall efficiecy it is clearly ot eough to go for roducts with low R DS(ON). As the ew efficiecy targets also require high levels of low load erformace, the switchig losses eed to be miimized at the same time. To fulfill these eeds, the FOM has to be dramatically decreased. By usig imroved maufacturig set-us this ste is ow ossible, as rove by the first alicatio measuremets. The efficiecy level ca be raised by u to 0.3 % while at the same time the tur-off voltage overshoot is reduced by u to 7 V. These imrovemets allow a easy desig-i rocess with less effort for the desigers of SMPS. Refereces [1] Mößlacher C. et al: Imrovig Efficiecy of Sychroous Rectificatio by Aalysis of the Mosfet Power Loss Mechaism, Proc. PCIM 2009, Nürberg, Germay [2] Nakagawa A. et al: Silico Limit Electrical Characteristics of Power Devices ad ICs, Proc. ISPS 2008, Prague, Czech Reublic [3] Mößlacher C. et al: Simle desig techiques for otimizig efficiecy ad overvoltage sike of sychroous rectificatio i DC to DC coverters, Proc. PCIM 2010, Nürberg, Germay [4] Schlögl A. et al: A ew robust ower MOSFET family i the voltage rage 80V - 150V with suerior low RDSo, excellet switchig roerties ad imroved body diode, Proc. EPE 2005, Dresde, Germay [5] Pawel I. et al: Theoretical Evaluatio of Maximum Doig Cocetratio, Breakdow Voltage ad O-state Resistace of Field-Plate Comesated Devices, Proc. ISPS 2008, Prague, Czech Reublic [6] Adreycak, B.: Active ower factor correctio usig zero curret ad zero voltage switchig techiques, Proc. HFPC 1991, Toroto, Caada [7] Syosys Ic.: Taurus Medici User Guide, Versio Z , March 2007 [8] Severs R.: Desig of Subbers for Power Circuits, htt:// July 2009 EPE Birmigham ISBN: P.10