ECE 2201 PRELAB 4A MOSFET SWITCHING APPLICATIONS. Digital CMOS Logic Inverter

Transcription

1 ECE 2201 PRELAB 4A MOSFET SWITCHING APPLICATIONS Digital CMOS Logic Iverter Had Aalysis P1. I the circuit of Fig. P41, estimate the roagatio delays t PLH ad t PHL usig the resistive switch model for each MOSFET. Assume that V t = 1.75V for both devices, ad that the rocess arameters are as show. K' W ma 1.0 W ma K' L V L V 5V 5V 0V VIN CL 100F VOUT Figure P41. Simulatio P2. Usig a simulatio tool, determie the roagatio delays t PLH ad t PHL for this circuit ad comare to your had aalysis. Use the followig MOSFET arameters for simulatio: L =L =100µm, W =W =100um, K = 1mA/V 2, ad K = 0.5mA/V 2. Set V IN to be a 0 to 5V 1MHz clock sigal ad lot the outut as a fuctio of time for at least two clock cycles. Use time cursors o the grah to determie the roagatio delays. Modificatios by Prof. Bitar. 1

2 PURPOSE: ECE 2201 LAB 4A MOSFET SWITCHING APPLICATIONS Digital CMOS Logic Iverter The urose of this laboratory assigmet is to ivestigate the oeratio of a itegrated CMOS logic iverter utilizig both NChael ad Pchael ehacemet mode MOSFET devices. Uo comletio of this lab you should be able to: Recogize the cutoff ad triode regios of oeratio for both Nchael ad Pchael MOSFETs. Determie the turo resistace r DS for several values of gatetosource voltage V GS for both N ad P chael devices. Extract MOSFET arameters k (W /L ), k (W /L ) ad threshold voltages V t,v t from triode regio measuremets. Aly the Pad Nchael MOSFET i the digital alicatio of a CMOS logic iverter ad measure the roagatio delays, t PHL ad t PLH for hightolow ad lowtohigh trasitios, resectfully. Use the effect of suly voltage o roagatio delay to develo a voltage cotrolled oscillator (VCO). MATERIALS: ECE Lab Kit DC Power Suly DVM Fuctio Geerator Oscilloscoe NOTES: (1) Be sure to record ALL results i your laboratory otebook. (2) THIS LAB UTILIZES THE MC14007 (or CD4007) MOSFET ARRAY SHOWN: Modificatios by Prof. Bitar. 2

3 NCHANNEL ENHANCEMENT MODE MOSFET PARAMETERS L1. Build the circuit show i Fig. 41, below. This circuit will be used to determie the rocess arameters k (W /L ) ad threshold voltage V t for oe of the NChael MOSFETS withi the MC14007 MOSFET array. Note that is, 7 ad 8 are used to access oe of the NMOS devices withi the itegrated circuit (IC). V GS RP 1kΩ 8 7 idmm idmm (RED) DMM (BLK) Figure 41. L2. Set V GS to a FIXED 2V ad measure the turo resistace r DS usig the digital multimeter (DMM) set to the 20kΩ rage. NOTE: If your meter has a autoscale feature, disable it ad use MANUAL mode. It is imortat that the meter remais i the 20kΩ rage for these measuremets, sice the iteral meter voltage will affect the readigs. L3. Reeat the r DS measuremets for V GS = 3V ad 5V. L4. Usig two of your data oits ad the followig exressio for r DS (derived i class), determie values for the rocess arameter k (W/L) ad the threshold voltage V t. r DS 1 k' ( W / L )( v V ) (1) GS t NOTE: V t should be betwee 1 & 2V ad k (W /L ) should be betwee 0.5 & 1.5 ma/v 2. Modificatios by Prof. Bitar. 3

4 PCHANNEL ENHANCEMENT MODE MOSFET PARAMETERS L5. Build the circuit show i Fig. 42, below. This circuit will be used to determie the rocess arameters k (W /L ) ad threshold voltage V t for oe of the PChael MOSFETS withi the MC14007 MOSFET array. Note that is, 13 ad 14 are used to access oe of the PMOS devices withi the IC. V S RP 1kΩ Figure 42. DMM L. Set V SG to a FIXED 2V ad measure the turo resistace r DS usig the digital multimeter (DMM) set to the 20kΩ rage. NOTE: Agai, if your meter has a autoscale feature, disable it ad use MANUAL mode. It is imortat that the meter remais i the 20kΩ rage for these measuremets, sice the iteral meter voltage will affect the readigs. L7. Reeat the r DS measuremets for V SG = 3V ad 5V. L8. Usig two of your data oits ad the followig exressio for r DS (derived i class), determie values for the rocess arameter k (W/L) ad the threshold voltage V t. r DS 1 (2) k' ( W / L )( v V ) SG t NOTE: V t should be betwee 1 & 2V ad k (W /L ) should be betwee 0.5 & 1.5 ma/v 2. Modificatios by Prof. Bitar. 4

5 DIGITAL SWITCH APPLICATIONS: CMOS LOGIC INVERTER L9. The goal of this circuit is the same as the assive load iverter from Lab 3: to take a iut voltage of either 0V (logic low) or 5V (logic high) ad rovide at the outut a voltage corresodig to the oosite logic level. DC Characteristics L10. Build the CMOS logic iverter show i Fig. 43. Adjust the fuctio geerator (usig the offset kob) so that v IN is a 100kHz, 0 to 5V square wave. NOTE: BE SURE TO CHECK V IN ON THE SCOPE BEFORE CONNECTING IT TO THE MOSFET ARRAY. L11. Set u the oscilloscoe to view the gate iut v IN o chael 1 at 2V/div, ad v OUT o chael 2 at 2V/div. Set both iuts to zero (GND) ad adjust the vertical ositio of each trace so that the iut is o the uer half of the dislay, ad the outut o the lower half. Oce the vertical ositio is adjusted correctly, whe viewig the voltage waveforms, be sure both chaels are o DC coulig. Set u the time base of the scoe to show at least oe full cycle of the square wave. L12. Sketch the iut ad outut waveforms as show o the oscilloscoe. Measure the high ad low voltage levels at the logic outut. I articular, ote how well the outut high ad low logic levels reroduce the iut levels. How well does this circuit meet the fuctioal goal exressed i art L9? 5V RP 1kΩ V 0 V IN M2 7 Fig. 43 Modificatios by Prof. Bitar. 5

6 AC Characteristics L13. As stated i the revious sectio, the goal of this circuit is rovide at the outut a logic level corresodig to the oosite of the iut. Ideally, if the iut chages state, the outut would chage istataeously; i ractice, there will be a delay which is referred to as the roagatio delay. L14. Add a 100F load caacitace the logic iverter, as show i Fig. 44. This caacitace corresods to the caacitive load that the outut might see due to the caacitace of a PC board trace, bus wirig, or other logic gate iuts. L15. Sketch the iut ad outut waveforms. Comare to the waveforms from art L10, with o caacitive load. L1. Measure the hightolow (t PHL ) ad lowtohigh (t PLH ) roagatio delays. Measuremet hit: for the hightolow measuremet, trigger the scoe off the risig edge of the iut, exad the horizotal scale to get a good look at the delay, ad use the time cursors to measure the delay time. For the lowtohigh measuremet, trigger off the fallig edge of the iut. L17. How well does this circuit meet the istataeous fuctioal goal exressed i sectio L13? 14 5V RP 1kΩ 13 5V 0 VIN 8 M2 7 CL 100F VOUT Figure 44. Modificatios by Prof. Bitar.

7 VOLTAGE CONTROLLED OSCILLATOR (VCO) L18. A imortat fuctioal block i commuicatio circuits is the voltage cotrolled oscillator, or VCO. This block is a oscillator for which the outut frequecy is cotrolled by a voltage. Oe simle tye of VCO is the rig oscillator, show i Fig The rig oscillator is simly a strig of iverters coected i a rig. With a odd umber of iversios, there is o stable state for v OUT, ad the result (after ay oweru trasiets die out) is a sigle trasitio chasig itself aroud the rig. Assumig the risig ad fallig roagatio delay times are equal to t PD, the resultig frequecy (for a N stage rig) is simly 1/Nt PD. As we have see, the roagatio delay of the CMOS iverter deeds o the suly voltage VDD: a higher VDD icreases the gate drive to the MOSFET, reducig r DS, thus reducig the roagatio delay. Sice the frequecy of the rig oscillator is determied by the roagatio delay, chagig VDD should allow us to chage the frequecy of the waveform at v OUT. L19. Build the circuit show i Fig 4.5. L20. Measure the frequecy of the outut waveform at v OUT for VDD=10V. Measure the frequecy at differet values of VDD, decreasig i icremets of 1V dow to 3V. VDD 14 M2 11 M VOU VDD M4 7 M5 9 M 4 Figure 45. Modificatios by Prof. Bitar. 7

8 LAB WRITEUP NCHANNEL AND PCHANNEL ENHANCEMENT MODE MOSFET PARAMETERS W1. Comare the turo resistaces r DS & r DS, as well as the threshold voltages V t & V t for the Nchael ad Pchael MOSFETS withi the MC14007 IC. How do they comare? Which is greater? How balaced are these two devices? DIGITAL SWITCH APPLICATIONS: CMOS LOGIC INVERTER W2. Plot the iut ad outut waveforms (without C L ) as show o the oscilloscoe. Idicate the measured high ad low voltage levels of the logic outut waveform. I articular, ote how well the outut high ad low logic levels reroduce the iut levels. How well does this circuit meet the iverter fuctioal goal? W3. Plot the iut ad outut waveforms with C L. Comare to the waveforms from art W8, with o caacitive load. W4. Aalysis: Derive equatios (i terms of C L ad r DS ) redictig the hightolow (t PHL ) ad lowtohigh (t PLH ) roagatio delays for this logic gate. W5. Comare the measured hightolow (t PHL ) ad lowtohigh (t PLH ) roagatio delays to the umerical redictios of your aalysis i art W4. W. Discussio: How well does this circuit meet the istataeous switchig fuctioal goal? Ca you suggest ay chages i the circuit that would imrove delay erformace? W7. Usig the rocess arameters ad threshold voltages that you determied i stes L4 ad L8 of this lab for the N ad P Chael MOSFETS, reeat your relab simulatio usig these values ad comare your measured roagatio delays to that of your simulatio. Commet o how well the simulatio matches your actual results. VOLTAGE CONTROLLED OSCILLATOR (VCO) W8. Plot your frequecy measuremets of the outut waveform at v OUT as a fuctio of the suly voltage VDD. How well does this circuit erform as a VCO i terms of the fuctioal goal exressed i art L18? Modificatios by Prof. Bitar. 8