32-Channel, 16-/14-Bit, Serial Input, Voltage Output DAC AD5372/AD5373

Transcription

1 32-Chael, 6-/4-Bit, Serial Iput, Voltage Output DAC AD5372/AD5373 FEATURES 32-chael DAC i a 64-lead LQFP AD5372/AD5373 guarateed mootoic to 6/4 bits Maximum output voltage spa of 4 VREF (20 V) Nomial output voltage rage of 4 V to +8 V Multiple, idepedet output voltage spas available System calibratio fuctio allowig user-programmable offset ad gai Chael groupig ad addressig features Thermal shutdow fuctio DSP/microcotroller-compatible serial iterface SPI serial iterface 2.5 V to 5.5 V JEDEC-compliat digital levels Digital reset (RESET) Clear fuctio to user-defied SIGGNDx Simultaeous update of DAC outputs APPLICATIONS Level settig i automatic test equipmet (ATE) Variable optical atteuators (VOA) Optical switches Idustrial cotrol systems Istrumetatio DV CC V DD V SS AGND DGND FUNCTIONAL BLOCK DIAGRAM LDAC CONTROL = 6 FOR AD5372 = 4 FOR AD A/B SELECT 8 X M C X2A X2B TO MUX 2s A/B MUX MUX 2 4 OFS0 DAC 0 OFFSET DAC 0 DAC 0 BUFFER BUFFER GROUP 0 OUTPUT BUFFER AND POWER- DOWN CONTROL VREF0 VOUT0 VOUT VOUT2 VOUT3 VOUT4 VOUT5 SYNC SDI SCLK SDO BUSY RESET CLR SERIAL INTERFACE STATE MACHINE X2A DAC 7 X X2B M C 8 A/B SELECT 8 X M C TO MUX 2s A/B MUX MUX 2 X2A X2B A/B MUX MUX 2 4 OFS DAC 0 DAC 7 OFFSET DAC DAC 0 BUFFER BUFFER OUTPUT BUFFER AND POWER- DOWN CONTROL GROUP OUTPUT BUFFER AND POWER- DOWN CONTROL VOUT6 VOUT7 SIGGND0 VREF VOUT8 VOUT9 VOUT0 VOUT VOUT2 VOUT3 X2A DAC 7 X X2B M C A/B MUX MUX 2 DAC 7 OUTPUT BUFFER AND POWER- DOWN CONTROL VOUT4 VOUT5 SIGGND AD5372/ AD5373 GROUP 2 TO GROUP 3 ARE IDENTICAL TO GROUP VREF SUPPLIES GROUP TO GROUP 3 VOUT6 TO VOUT3 SIGGND2 SIGGND Figure. Protected by U.S. Patet No. 5,969,657; other patets pedig. Rev. B Iformatio furished by Aalog Devices is believed to be accurate ad reliable. However, o resposibility is assumed by Aalog Devices for its use, or for ay ifrigemets of patets or other rights of third parties that may result from its use. Specificatios subject to chage without otice. No licese is grated by implicatio or otherwise uder ay patet or patet rights of Aalog Devices. Trademarks ad registered trademarks are the property of their respective owers. Oe Techology Way, P.O. Box 906, Norwood, MA , U.S.A. Tel: Fax: Aalog Devices, Ic. All rights reserved.

2 TABLE OF CONTENTS Features... Applicatios... Fuctioal Block Diagram... Revisio History... 2 Geeral Descriptio... 3 Specificatios... 4 AC Characteristics... 5 Timig Characteristics... 6 Absolute Maximum Ratigs... 9 ESD Cautio... 9 Pi Cofiguratio ad Fuctio Descriptios... 0 Typical Performace Characteristics... Termiology... 3 Theory of Operatio... 4 DAC Architecture... 4 Chael Groups... 4 A/B Registers ad Gai/Offset Adjustmet... 5 Load DAC... 5 Offset DACs... 5 Output Amplifier... 6 Trasfer Fuctio... 6 Referece Selectio... 6 Calibratio... 7 Additioal Calibratio... 8 Reset Fuctio... 8 Clear Fuctio... 8 BUSY ad LDAC Fuctios... 8 Power-Dow Mode... 9 Thermal Shutdow Fuctio... 9 Toggle Mode... 9 Serial Iterface SPI Write Mode SPI Readback Mode Register Update Rates Chael Addressig ad Special Modes... 2 Special Fuctio Mode Applicatios Iformatio Power Supply Decouplig Power Supply Sequecig Iterfacig Examples Outlie Dimesios Orderig Guide REVISION HISTORY 2/08 Rev. A to Rev. B Added Table... 3 Chages to t0 Parameter... 6 Added t23 Parameter... 6 Chages to Figure Chages to Absolute Maximum Ratigs Sectio... 9 Chages to Pi Cofiguratio ad Fuctio Descriptios Sectio... 0 Chages to Reset Fuctio Sectio /07 Rev. 0 to Rev. A Chages to Table Chages to AD5373 Trasfer Fuctio Sectio... 6 Chages to Calibratio Sectio... 7 Chages to Table Chages to Register Update Rates Sectio Chages to Orderig Guide /07 Revisio 0: Iitial Versio Rev. B Page 2 of 24

3 GENERAL DESCRIPTION The AD5372/AD5373 cotai 32 6-/4-bit DACs i a sigle 64-lead LQFP. The devices provide buffered voltage outputs with a omial spa of 4 the referece voltage. The gai ad offset of each DAC ca be idepedetly trimmed to remove errors. For eve greater flexibility, the device is divided ito four groups of eight DACs. Two offset DACs allow the output rage of the groups to be altered. Group 0 ca be adjusted by Offset DAC 0, ad Group to Group 3 ca be adjusted by Offset DAC. The AD5372/AD5373 offer guarateed operatio over a wide supply rage: VSS from 6.5 V to 4.5 V ad VDD from 9 V to 6.5 V. The output amplifier headroom requiremet is.4 V operatig with a load curret of ma. The AD5372/AD5373 have a high speed serial iterface that is compatible with SPI, QSPI, MICROWIRE, ad DSP iterface stadards ad ca hadle clock speeds of up to 50 MHz. The DAC registers are updated o receptio of ew data. All the outputs ca be updated simultaeously by takig the LDAC iput low. Each chael has a programmable gai ad a offset adjust register. Each DAC output is gaied ad buffered o chip with respect to a exteral SIGGNDx iput. The DAC outputs ca also be switched to SIGGNDx via the CLR pi. Table. High Chael Cout Bipolar DACs Model Resolutio (Bits) Nomial Output Spa Output Chaels Liearity Error (LSB) AD VREF (20 V) 6 ±4 AD VREF (20 V) 6 ± AD VREF (20 V) 8 ±4 AD VREF (20 V) 8 ± AD VREF (2 V) 40 ±4 AD VREF (2 V) 40 ± AD VREF (2 V) 32 ±4 AD VREF (2 V) 32 ± AD ±8.75 V 32 ±3 AD ±8.75 V 40 ±3 Rev. B Page 3 of 24

4 SPECIFICATIONS DVCC = 2.5 V to 5.5 V; VDD = 9 V to 6.5 V; VSS = 6.5 V to 8 V; VREF0 = VREF = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = ope circuit; RL = ope circuit; gai (M), offset (C), ad DAC offset registers at default values; all specificatios TMIN to TMAX, uless otherwise oted. Table 2. Parameter AD5372 B Versio AD5373 B Versio Uit Test Coditios/Commets 2 ACCURACY Resolutio 6 4 Bits Itegral Noliearity (INL) ±4 ± LSB max Differetial Noliearity (DNL) ± ± LSB max Guarateed mootoic by desig over temperature Zero-Scale Error ±0 ±0 mv max Before calibratio Full-Scale Error ±0 ±0 mv max Before calibratio Gai Error % FSR Before calibratio Zero-Scale Error 2 LSB typ After calibratio Full-Scale Error 2 LSB typ After calibratio Spa Error of Offset DAC ±35 ±35 mv max See the Offset DACS sectio for details VOUTx Temperature Coefficiet 5 5 ppm FSR/ C typ Icludes liearity, offset, ad gai drift DC Crosstalk μv max Typically 20 μv; measured chael at midscale, full-scale chage o ay other chael REFERENCE INPUTS (VREF0, VREF) 2 VREFx Iput Curret ±0 ±0 μa max Per iput; typically ±30 A VREFx Rage 2/5 2/5 V mi/v max ±2% for specified operatio SIGGND INPUTS (SIGGND0 TO SIGGND3) 2 DC Iput Impedace kω mi Typically 55 kω Iput Rage ±0.5 ±0.5 V mi/v max SIGGNDx Gai 0.995/ /.005 mi/max OUTPUT CHARACTERISTICS 2 Output Voltage Rage VSS +.4 VSS +.4 V mi ILOAD = ma VDD.4 VDD.4 V max ILOAD = ma Nomial Output Voltage Rage 4 to +8 4 to +8 V mi/v max Short-Circuit Curret 5 5 ma max VOUTx to DVCC, VDD, or VSS Load Curret ± ± ma max Capacitive Load pf max DC Output Impedace Ω max DIGITAL INPUTS JEDEC compliat Iput High Voltage.7.7 V mi DVCC = 2.5 V to 3.6 V V mi DVCC = 3.6 V to 5.5 V Iput Low Voltage V max DVCC = 2.5 V to 5.5 V Iput Curret ± ± μa max Excludig CLR pi CLR High Impedace Leakage Curret ±20 ±20 μa max Iput Capacitace pf max DIGITAL OUTPUTS (SDO, BUSY) Output Low Voltage V max Sikig 200 μa Output High Voltage (SDO) DVCC 0.5 DVCC 0.5 V mi Sourcig 200 μa SDO High Impedace Leakage Curret ±5 ±5 μa max High Impedace Output Capacitace pf typ Rev. B Page 4 of 24

5 Parameter POWER REQUIREMENTS AD5372 B Versio DVCC 2.5/ /5.5 V mi/v max VDD 9/6.5 9/6.5 V mi/v max VSS 6.5/ / 4.5 V mi/v max Power Supply Sesitivity 2 Full Scale/ VDD db typ Full Scale/ VSS db typ Full Scale/ DVCC db typ AD5373 B Versio Uit Test Coditios/Commets 2 DICC 2 2 ma max DVCC = 5.5 V, VIH = DVCC, VIL = GND IDD 6 6 ma max Outputs uloaded, DAC outputs = 0 V 8 8 ma max Outputs uloaded, DAC outputs = full scale ISS 6 6 ma max Outputs uloaded, DAC outputs = 0 V 8 8 ma max Outputs uloaded, DAC outputs = full scale Power-Dow Mode Bit 0 i the cotrol register is DICC 5 5 μa typ IDD μa typ ISS μa typ Power Dissipatio (Uloaded) mw typ VSS = 8 V, VDD = 9.5 V, DVCC = 2.5 V Juctio Temperature C max TJ = TA + PTOTAL θja Temperature rage for B versio: 40 C to +85 C. Typical specificatios are at 25 C. 2 Guarateed by desig ad characterizatio; ot productio tested. 3 θja represets the package thermal impedace. AC CHARACTERISTICS DVCC = 2.5 V; VDD = 5 V; VSS = 5 V; VREF0 = VREF = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pf; RL = 0 kω; gai (M), offset (C), ad DAC offset registers at default values; all specificatios TMIN to TMAX, uless otherwise oted. Table 3. Parameter B Versio Uit Test Coditios/Commets DYNAMIC PERFORMANCE Output Voltage Settlig Time 20 μs typ Full-scale chage 30 μs max DAC latch cotets alterately loaded with all 0s ad all s Slew Rate V/μs typ Digital-to-Aalog Glitch Eergy 5 V-s typ Glitch Impulse Peak Amplitude 0 mv max Chael-to-Chael Isolatio 00 db typ VREF0, VREF = 2 V p-p, khz DAC-to-DAC Crosstalk 0 V-s typ Digital Crosstalk 0.2 V-s typ Digital Feedthrough 0.02 V-s typ Effect of iput bus activity o DAC output uder test Output Noise Spectral 0 khz 250 V/ Hz typ VREF0 = VREF = 0 V Guarateed by desig ad characterizatio; ot productio tested. Rev. B Page 5 of 24

6 TIMING CHARACTERISTICS DVCC = 2.5 V to 5.5 V; VDD = 9 V to 6.5 V; VSS = 6.5 V to 8 V; VREFx = 3 V; AGND = DGND = SIGGNDx = 0 V; CL = 200 pf to GND; RL = ope circuit; gai (M), offset (C), ad DAC offset registers at default values; all specificatios TMIN to TMAX, uless otherwise oted. Table 4. SPI Iterface Parameter, 2, 3 Limit at TMIN, TMAX Uit Descriptio t 20 s mi SCLK cycle time t2 8 s mi SCLK high time t3 8 s mi SCLK low time t4 s mi SYNC fallig edge to SCLK fallig edge setup time t5 20 s mi Miimum SYNC high time t6 0 s mi 24 th SCLK fallig edge to SYNC risig edge t7 5 s mi Data setup time t8 5 s mi Data hold time t s max SYNC risig edge to BUSY fallig edge t0 /.5 μs typ/μs max BUSY pulse width low (sigle-chael update); see Table 9 t 600 s max Sigle-chael update cycle time t2 20 s mi SYNC risig edge to LDAC fallig edge t3 0 s mi LDAC pulse width low t4 3 μs max BUSY risig edge to DAC output respose time t5 0 s mi BUSY risig edge to LDAC fallig edge t6 3 μs max LDAC fallig edge to DAC output respose time t7 20/30 μs typ/μs max DAC output settlig time t8 40 s max CLR/RESET pulse activatio time t9 30 s mi RESET pulse width low t μs max RESET time idicated by BUSY low t2 270 s mi Miimum SYNC high time i readback mode t s max SCLK risig edge to SDO valid t23 80 s max RESET risig edge to BUSY fallig edge Guarateed by desig ad characterizatio; ot productio tested. 2 All iput sigals are specified with tr = tf = 2 s (0% to 90% of DVCC) ad timed from a voltage level of.2 V. 3 See Figure 4 ad Figure 5. 4 t9 is measured with the load circuit show i Figure 2. 5 t22 is measured with the load circuit show i Figure 3. DV CC 200µA I OL TO OUTPUT PIN R L 2.2kΩ C L 50pF V OL Figure 2. Load Circuit for BUSY Timig Diagram TO OUTPUT PIN C L 50pF 200µA I OH V OH (MIN) V OL (MAX) Figure 3. Load Circuit for SDO Timig Diagram Rev. B Page 6 of 24

7 t SCLK t 3 t t 4 t 2 t 6 SYNC t 5 t 7 t 8 SDI DB23 DB0 t 9 BUSY t 0 t 2 t 3 LDAC t 7 VOUTx t 4 t 5 t 3 LDAC 2 t 7 VOUTx 2 t 6 CLR t 8 VOUTx t 9 RESET VOUTx BUSY t 8 t 20 t 23 LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY Figure 4. SPI Write Timig Rev. B Page 7 of 24

8 t 22 SCLK 48 t 2 SYNC SDI DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES TO BE READ NOP CONDITION SDO DB0 DB23 DB5 DB0 LSB FROM PREVIOUS WRITE Figure 5. SPI Read Timig SELECTED DATA CLOCKED OUT OUTPUT VOLTAGE 8V ACTUAL TRANSFER FUNCTION FULL-SCALE ERROR + ZERO-SCALE ERROR IDEAL TRANSFER FUNCTION 0 DAC CODE V ZERO-SCALE ERROR Figure 6. DAC Trasfer Fuctio Rev. B Page 8 of 24

9 ABSOLUTE MAXIMUM RATINGS TA = 25 C, uless otherwise oted. Trasiet currets of up to 60 ma do ot cause SCR latch-up. Table 5. Parameter Ratig VDD to AGND 0.3 V to +7 V VSS to AGND 7 V to +0.3 V DVCC to DGND 0.3 V to +7 V Digital Iputs to DGND 0.3 V to DVCC V Digital Outputs to DGND 0.3 V to DVCC V VREF0, VREF to AGND 0.3 V to +5.5 V VOUT0 through VOUT3 to AGND VSS 0.3 V to VDD V SIGGNDx to AGND V to + V AGND to DGND 0.3 V to +0.3 V Operatig Temperature Rage (TA) Idustrial (B Versio) 40 C to +85 C Storage Temperature Rage 65 C to +50 C Juctio Temperature (TJ max) 30 C θja Thermal Impedace 64-Lead LQFP 45.5 C/W Reflow Solderig Peak Temperature 230 C Time at Peak Temperature 0 sec to 40 sec Stresses above those listed uder Absolute Maximum Ratigs may cause permaet damage to the device. This is a stress ratig oly; fuctioal operatio of the device at these or ay other coditios above those idicated i the operatioal sectio of this specificatio is ot implied. Exposure to absolute maximum ratig coditios for exteded periods may affect device reliability. ESD CAUTION Rev. B Page 9 of 24

10 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS RESET BUSY 2 VOUT27 3 SIGGND3 4 VOUT28 5 VOUT29 6 VOUT30 7 VOUT3 8 NC 9 NC 0 NC NC 2 NC 3 NC 4 NC 5 V DD 6 NC = NO CONNECT V SS CLR VREF LDAC NC VOUT26 NC VOUT25 VOUT8 VOUT24 VOUT9 AGND VOUT0 DGND VOUT DV CC SIGGND SDO VOUT2 SDI VOUT3 SCLK VOUT4 SYNC DV CC VOUT5 DGND VOUT7 VOUT PIN INDICATOR AD5372/AD5373 TOP VIEW (Not to Scale) Figure 7. Pi Cofiguratio VOUT6 VOUT7 VOUT8 48 VOUT5 47 VOUT4 46 SIGGND0 45 VOUT3 44 VOUT2 43 VOUT 42 VOUT0 4 VREF0 40 VOUT23 39 VOUT22 38 VOUT VOUT20 V SS V DD 34 SIGGND2 33 VOUT9 Table 6. Pi Fuctio Descriptios Pi No. Memoic Descriptio RESET Digital Reset Iput. 2 BUSY Digital Iput/Ope-Drai Output. BUSY is ope drai whe a output. See the BUSY ad LDAC Fuctios sectio for more iformatio. 42 to 45, 47 to 50, 2 to 24, 26 to 33, 37 to 40, 60 to 62, 3, 5 to 8 VOUT0 to VOUT3 DAC Outputs. Buffered aalog outputs for each of the 32 DAC chaels. Each aalog output is capable of drivig a output load of 0 kω to groud. Typical output impedace of these amplifiers is 0.5 Ω. 4 SIGGND3 Referece Groud for DAC 24 to DAC 3. VOUT24 to VOUT3 are refereced to this voltage. 9 to 5, 9, 20 NC No Coect. 6, 35 VDD Positive Aalog Power Supply; 9 V to 6.5 V for specified performace. These pis should be decoupled with 0. μf ceramic capacitors ad 0 μf capacitors. 7, 36 VSS Negative Aalog Power Supply; 6.5 V to 8 V for specified performace. These pis should be decoupled with 0. μf ceramic capacitors ad 0 μf capacitors. 8 VREF Referece Iput for DAC 8 to DAC 3. This referece voltage is referred to AGND. 25 SIGGND Referece Groud for DAC 8 to DAC 5. VOUT8 to VOUT5 are refereced to this voltage. 34 SIGGND2 Referece Groud for DAC 6 to DAC 23. VOUT6 to VOUT23 are refereced to this voltage. 4 VREF0 Referece Iput for DAC 0 to DAC 7. This referece voltage is referred to AGND. 46 SIGGND0 Referece Groud for DAC 0 to DAC 7. VOUT0 to VOUT7 are refereced to this voltage. 5, 58 DGND Groud for All Digital Circuitry. The DGND pis should be coected to the DGND plae. 52, 57 DVCC Logic Power Supply; 2.5 V to 5.5 V. These pis should be decoupled with 0. μf ceramic capacitors ad 0 μf capacitors. 53 SYNC Active Low Iput. This is the frame sychroizatio sigal for the serial iterface. 54 SCLK Serial Clock Iput. Data is clocked ito the shift register o the fallig edge of SCLK. This pi operates at clock speeds up to 50 MHz. 55 SDI Serial Data Iput. Data must be valid o the fallig edge of SCLK. 56 SDO Serial Data Output. CMOS output. SDO ca be used for readback. Data is clocked out o SDO o the risig edge of SCLK ad is valid o the fallig edge of SCLK. 59 AGND Groud for All Aalog Circuitry. The AGND pi should be coected to the AGND plae. 63 LDAC Load DAC Logic Iput (Active Low). See the BUSY ad LDAC Fuctios sectio for more iformatio. 64 CLR Asychroous Clear Iput (Level Sesitive, Active Low). See the Clear Fuctio sectio for more iformatio Rev. B Page 0 of 24

11 TYPICAL PERFORMANCE CHARACTERISTICS AD5372/AD5373 T A = 25 C V SS = 5V V DD = +5V VREFx = V INL (LSB) 0 AMPLITUDE (V) DAC CODE TIME (µs) Figure 8. Typical AD5372 INL Plot Figure. Digital Crosstalk V DD = +5V V SS = 5V DV CC = +5V VREFx = +3V INL ERROR (LSB) 0 DNL (LSB) TEMPERATURE ( C) Figure 9. Typical INL Error vs. Temperature DAC CODE Figure 2. Typical AD5372 DNL Plot T A = 25 C V SS = 5V V DD = +5V VREFx = V AMPLITUDE (V) 0.0 OUTPUT NOISE (V/ Hz) TIME (µs) Figure 0. Aalog Crosstalk Due to LDAC FREQUENCY (Hz) Figure 3. Output Noise Spectral Desity Rev. B Page of 24

12 V SS = 2V V DD = +2V VREFx = +3V 4 2 V SS = 5V V DD = +5V T A = 25 C DI CC (ma) DV CC = +5.5V DV CC = +2.5V DV CC = +3.6V NUMBER OF UNITS TEMPERATURE ( C) I DD (ma) Figure 4. DICC vs. Temperature Figure 6. Typical IDD Distributio 3.5 I DD 4 2 DV CC = 5V T A = 25 C I DD /I SS (ma) I SS NUMBER OF UNITS V SS = 2V V DD = +2V VREFx = +3V TEMPERATURE ( C) DI CC (ma) Figure 5. IDD/ISS vs. Temperature Figure 7. Typical DICC Distributio Rev. B Page 2 of 24

13 TERMINOLOGY Itegral Noliearity (INL) Itegral oliearity, or edpoit liearity, is a measure of the maximum deviatio from a straight lie passig through the edpoits of the DAC trasfer fuctio. It is measured after adjustig for zero-scale error ad full-scale error ad is expressed i least sigificat bits (LSB). Differetial Noliearity (DNL) Differetial oliearity is the differece betwee the measured chage ad the ideal LSB chage betwee ay two adjacet codes. A specified differetial oliearity of LSB maximum esures mootoicity. Zero-Scale Error Zero-scale error is the error i the DAC output voltage whe all 0s are loaded ito the DAC register. Zero-scale error is a measure of the differece betwee VOUT (actual) ad VOUT (ideal), expressed i millivolts, whe the chael is at its miimum value. Zero-scale error is maily due to offsets i the output amplifier. Full-Scale Error Full-scale error is the error i the DAC output voltage whe all s are loaded ito the DAC register. Full-scale error is a measure of the differece betwee VOUT (actual) ad VOUT (ideal), expressed i millivolts, whe the chael is at its maximum value. Full-scale error does ot iclude zero-scale error. Gai Error Gai error is the differece betwee full-scale error ad zero-scale error. It is expressed as a percetage of the fullscale rage (FSR). Gai Error = Full-Scale Error Zero-Scale Error VOUT Temperature Coefficiet The VOUT temperature coefficiet icludes output error cotributios from liearity, offset, ad gai drift. DC Output Impedace DC output impedace is the effective output source resistace. It is domiated by package lead resistace. DC Crosstalk The DAC outputs are buffered by op amps that share commo VDD ad VSS power supplies. If the dc load curret chages i oe chael (due to a update), this chage ca result i a further dc chage i oe or more chael outputs. This effect is more sigificat at high load currets ad is reduced as the load currets are reduced. With high impedace loads, the effect is virtually immeasurable. Multiple VDD ad VSS termials are provided to miimize dc crosstalk. Output Voltage Settlig Time Output voltage settlig time is the amout of time it takes for the output of a DAC to settle to a specified level for a full-scale iput chage. Digital-to-Aalog Glitch Eergy Digital-to-aalog glitch eergy is the amout of eergy that is ijected ito the aalog output at the major code trasitio. It is specified as the area of the glitch i V-s. It is measured by togglig the DAC register data betwee 0x7FFF ad 0x8000 (AD5372) or 0xFFF ad 0x2000 (AD5373). Chael-to-Chael Isolatio Chael-to-chael isolatio refers to the proportio of iput sigal from the referece iput of oe DAC that appears at the output of aother DAC operatig from aother referece. It is expressed i decibels ad measured at midscale. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse that appears at the output of oe coverter due to both the digital chage ad subsequet aalog output chage at aother coverter. It is specified i V-s. Digital Crosstalk Digital crosstalk is defied as the glitch impulse trasferred to the output of oe coverter due to a chage i the DAC register code of aother coverter. It is specified i V-s. Digital Feedthrough Whe the device is ot selected, high frequecy logic activity o the digital iputs of the device ca be capacitively coupled both across ad through the device to appear as oise o the VOUT pis. It ca also be coupled alog the supply ad groud lies. This oise is digital feedthrough. Output Noise Spectral Desity Output oise spectral desity is a measure of iterally geerated radom oise. Radom oise is characterized as a spectral desity (voltage per Hz). It is measured by loadig all DACs to midscale ad measurig oise at the output. It is measured i V/ Hz. Rev. B Page 3 of 24

14 THEORY OF OPERATION DAC ARCHITECTURE The AD5372/AD5373 cotai 32 DAC chaels ad 32 output amplifiers i a sigle package. The architecture of a sigle DAC chael cosists of a 6-bit (AD5372) or 4-bit (AD5373) resistor-strig DAC followed by a output buffer amplifier. The resistor-strig sectio is simply a strig of resistors (of equal value) from VREF0 or VREF to AGND. This type of architecture guaratees DAC mootoicity. The 6-bit (AD5372) or 4-bit (AD5373) biary digital code loaded to the DAC register determies at which ode o the strig the voltage is tapped off before beig fed ito the output amplifier. Table 7. AD5372/AD5373 Registers Word Legth Register Name i Bits Descriptio The output amplifier multiplies the DAC output voltage by 4. The omial output spa is 2 V with a 3 V referece ad 20 V with a 5 V referece. CHANNEL GROUPS The 32 DAC chaels of the AD5372/AD5373 are arraged ito four groups of eight chaels. The eight DACs of Group 0 derive their referece voltage from VREF0. Group to Group 3 derive their referece voltage from VREF. Each group has its ow sigal groud pi. XA (Group) (Chael) 6 (4) Iput Data Register A, oe for each DAC chael. XB (Group) (Chael) 6 (4) Iput Data Register B, oe for each DAC chael. M (Group) (Chael) 6 (4) Gai trim registers, oe for each DAC chael. C (Group) (Chael) 6 (4) Offset trim registers, oe for each DAC chael. X2A (Group) (Chael) 6 (4) Output Data Register A, oe for each DAC chael. These registers store the fial, calibrated DAC data after gai ad offset trimmig. They are ot readable or directly writable. X2B (Group) (Chael) 6 (4) Output Data Register B, oe for each DAC chael. These registers store the fial, calibrated DAC data after gai ad offset trimmig. They are ot readable or directly writable. DAC (Group) (Chael) Data registers from which the DACs take their fial iput data. The DAC registers are updated from the X2A or X2B registers. They are ot readable or directly writable. OFS0 4 Offset DAC 0 data register: sets offset for Group 0. OFS 4 Offset DAC data register: sets offset for Group to Group 3. Cotrol 3 Bit 2 = A/B. 0 = global selectio of XA iput data registers. = global selectio of XB iput data registers. Bit = eable thermal shutdow. 0 = disable thermal shutdow. = eable thermal shutdow. Bit 0 = software power-dow. 0 = software power-up. = software power-dow. A/B Select 0 8 Each bit i this register determies whether a DAC i Group 0 takes its data from Register X2A or Register X2B (0 = X2A, = X2B). A/B Select 8 Each bit i this register determies whether a DAC i Group takes its data from Register X2A or Register X2B (0 = X2A, = X2B). A/B Select 2 8 Each bit i this register determies whether a DAC i Group 2 takes its data from Register X2A or Register X2B (0 = X2A, = X2B). A/B Select 3 8 Each bit i this register determies whether a DAC i Group 3 takes its data from Register X2A or Register X2B (0 = X2A, = X2B). Table 8. AD5372/AD5373 Iput Register Default Values Register Name AD5372 Default Value AD5373 Default Value XA, XB 0x5554 0x555 M 0xFFFF 0x3FFF C 0x8000 0x2000 OFS0, OFS 0x555 0x555 Cotrol 0x00 0x00 A/B Select 0 to A/B Select 3 0x00 0x00 Rev. B Page 4 of 24

15 A/B S AND GAIN/OFFSET ADJUSTMENT Each DAC chael has seve data registers. The actual DAC data-word ca be writte to either the XA or the XB iput register, depedig o the settig of the A/B bit i the cotrol register. If the A/B bit is 0, data is writte to the XA register. If the A/B bit is, data is writte to the XB register. Note that this sigle bit is a global cotrol ad affects every DAC chael i the device. It is ot possible to set up the device o a perchael basis so that some writes are to XA registers ad some writes are to XB registers. XA XB M C MUX X2A X2B MUX DAC Figure 8. Data Registers Associated with Each DAC Chael DAC Each DAC chael also has a gai (M) register ad a offset (C) register, which allow trimmig out of the gai ad offset errors of the etire sigal chai. Data from the XA register is operated o by a digital multiplier ad adder cotrolled by the cotets of the M ad C registers. The calibrated DAC data is the stored i the X2A register. Similarly, data from the XB register is operated o by the multiplier ad adder ad stored i the X2B register. Although a multiplier ad adder symbol are show i Figure 8 for each chael, there is oly oe multiplier ad oe adder i the device, which are shared amog all chaels. This has implicatios for the update speed whe several chaels are updated at oce, as described i the Register Update Rates sectio. Each time data is writte to the XA register, or to the M or C register with the A/B cotrol bit set to 0, the X2A data is recalculated ad the X2A register is automatically updated. Similarly, X2B is updated each time data is writte to XB, or to M or C with A/B set to. The X2A ad X2B registers are ot readable or directly writable by the user. Data output from the X2A ad X2B registers is routed to the fial DAC register by a multiplexer. Whether each idividual DAC takes its data from the X2A or from the X2B register is cotrolled by a 8-bit A/B select register associated with each group of eight DACs. If a bit i this register is 0, the DAC takes its data from the X2A register; if, the DAC takes its data from the X2B register (Bit 0 through Bit 7 cotrol DAC 0 to DAC 7). Note that because there are 32 bits i four registers, it is possible to set up, o a per-chael basis, whether each DAC takes its data from the X2A or X2B register. A global commad is also provided that sets all bits i the A/B select registers to 0 or to LOAD DAC All DACs i the AD5372/AD5373 ca be updated simultaeously by takig LDAC low whe each DAC register is updated from either its X2A or X2B register, depedig o the settig of the A/B select registers. The DAC register is ot readable or directly writable by the user. LDAC ca be permaetly tied low, ad the DAC output is updated wheever ew data appears i the appropriate DAC register. OFFSET DACs I additio to the gai ad offset trim for each DAC, there are two 4-bit offset DACs, oe for Group 0 ad oe for Group to Group 3. These allow the output rage of all DACs coected to them to be offset withi a defied rage. Thus, subject to the limitatios of headroom, it is possible to set the output rage of Group 0 or Group to Group 3 to be uipolar positive, uipolar egative, or bipolar, either symmetrical or asymmetrical about 0 V. The DACs i the AD5372/AD5373 are factory trimmed with the offset DACs set at their default values. This gives the best offset ad gai performace for the default output rage ad spa. Whe the output rage is adjusted by chagig the value of the offset DAC, a extra offset is itroduced due to the gai error of the offset DAC. The amout of offset is depedet o the magitude of the referece ad how much the offset DAC moves from its default value. See the Specificatios sectio for this offset. The worst-case offset occurs whe the offset DAC is at positive or egative full scale. This value ca be added to the offset preset i the mai DAC chael to give a idicatio of the overall offset for that chael. I most cases, the offset ca be removed by programmig the C register of the chael with a appropriate value. The extra offset caused by the offset DAC eeds to be take ito accout oly whe the offset DAC is chaged from its default value. Figure 9 shows the allowable code rage that ca be loaded to the offset DAC, depedig o the referece value used. Thus, for a 5 V referece, the offset DAC should ot be programmed with a value greater tha 892 (0x2000). VREF (V) OFFSET DAC CODE Figure 9. Offset DAC Code Rage RESERVED Rev. B Page 5 of 24

16 OUTPUT AMPLIFIER Because the output amplifiers ca swig to.4 V below the positive supply ad.4 V above the egative supply, this limits how much the output ca be offset for a give referece voltage. For example, it is ot possible to have a uipolar output rage of 20 V, because the maximum supply voltage is ±6.5 V. SIGGNDx R4 60kΩ OFFSET DAC DAC CHANNEL R3 20kΩ R5 60kΩ R 20kΩ R2 20kΩ S2 CLR S CLR R6 0kΩ S3 SIGGNDx Figure 20. Output Amplifier ad Offset DAC OUTPUT Figure 20 shows details of a DAC output amplifier ad its coectios to the offset DAC. O power-up, S is ope, discoectig the amplifier from the output. S3 is closed, so the output is pulled to SIGGNDx (R ad R2 are greater tha R6). S2 is also closed to prevet the output amplifier from beig ope-loop. If CLR is low at power-up, the output remais i this coditio util CLR is take high. The DAC registers ca be programmed, ad the outputs assume the programmed values whe CLR is take high. Eve if CLR is high at power-up, the output remais i the previous coditio util VDD > 6 V ad VSS < 4 V ad the iitializatio sequece has fiished. The outputs the go to their power-o default value. TRANSFER FUNCTION The output voltage of a DAC i the AD5372/AD5373 is depedet o the value i the iput register, the value of the M ad C registers, ad the value i the offset DAC. AD5372 Trasfer Fuctio The iput code is the value i the XA or XB register that is applied to the DAC (XA, XB default code = 2,844). DAC_CODE = INPUT_CODE (M + )/2 6 + C 2 5 where: M = code i gai register default code = 2 6. C = code i offset register default code = 2 5. The DAC output voltage is calculated as follows: VOUT = 4 VREFx (DAC_CODE (OFFSET_CODE 4))/2 6 + VSIGGND CLR where: DAC_CODE should be withi the rage of 0 to 65,535. For 2 V spa, VREFx = 3.0 V. For 20 V spa, VREFx = 5.0 V. OFFSET_CODE is the code loaded to the offset DAC. It is multiplied by 4 i the trasfer fuctio because this DAC is a 4-bit device. O power-up, the default code loaded to the offset DAC is 546 (0x555). With a 3 V referece, this gives a spa of 4 V to +8 V. AD5373 Trasfer Fuctio The iput code is the value i the XA or XB register that is applied to the DAC (XA, XB default code = 546). DAC_CODE = INPUT_CODE (M + )/2 4 + C 2 3 where: M = code i gai register default code = 2 4. C = code i offset register default code = 2 3. The DAC output voltage is calculated as follows: VOUT = 4 VREFx (DAC_CODE OFFSET_CODE)/2 4 + VSIGGND where: DAC_CODE should be withi the rage of 0 to 6,383. For 2 V spa, VREFx = 3.0 V. For 20 V spa, VREFx = 5.0 V. OFFSET_CODE is the code loaded to the offset DAC. O power-up, the default code loaded to the offset DAC is 546 (0x555). With a 3 V referece, this gives a spa of 4 V to +8 V. REFERENCE SELECTION The AD5372/AD5373 have two referece iput pis. The voltage applied to the referece pis determies the output voltage spa o VOUT0 to VOUT3. VREF0 determies the voltage spa for VOUT0 to VOUT7 (Group 0), ad VREF determies the voltage spa for VOUT8 to VOUT3 (Group to Group 3). The referece voltage applied to each VREF pi ca be differet, if required, allowig the groups to have differet voltage spas. The output voltage rage ad spa ca be adjusted further by programmig the offset ad gai registers for each chael as well as programmig the offset DACs. If the offset ad gai features are ot used (that is, the M ad C registers are left at their default values), the required referece levels ca be calculated as follows: VREF = (VOUTMAX VOUTMIN)/4 If the offset ad gai features of the AD5372/AD5373 are used, the required output rage is slightly differet. The selected output rage should take ito accout the system offset ad gai errors that eed to be trimmed out. Therefore, the selected output rage should be larger tha the actual required rage. Rev. B Page 6 of 24

17 The required referece levels ca be calculated as follows:. Idetify the omial output rage o VOUT. 2. Idetify the maximum offset spa ad the maximum gai required o the full output sigal rage. 3. Calculate the ew maximum output rage o VOUT, icludig the expected maximum offset ad gai errors. 4. Choose the ew required VOUTMAX ad VOUTMIN, keepig the VOUT limits cetered o the omial values. Note that VDD ad VSS must provide sufficiet headroom. 5. Calculate the value of VREF as follows: VREF = (VOUTMAX VOUTMIN)/4 Referece Selectio Example If Nomial output rage = 2 V ( 4 V to +8 V) Zero-scale error = ±70 mv Gai error = ±3%, ad SIGGNDx = AGND = 0 V The Gai error = ±3% => Maximum positive gai error = 3% => Output rage icludig gai error = (2) = 2.36 V Zero-scale error = ±70 mv => Maximum offset error spa = 2(70 mv) = 0.4 V => Output rage icludig gai error ad zero-scale error = 2.36 V V = 2.5 V VREF calculatio Actual output rage = 2.5 V, that is, 4.25 V to V; VREF = (8.25 V V)/4 = 3.25 V If the solutio yields a icoveiet referece level, the user ca adopt oe of the followig approaches: Use a resistor divider to divide dow a coveiet, higher referece level to the required level. Select a coveiet referece level above VREF ad modify the gai ad offset registers to digitally dowsize the referece. I this way, the user ca use almost ay coveiet referece level but ca reduce the performace by overcompactio of the trasfer fuctio. Use a combiatio of these two approaches. CALIBRATION The user ca perform a system calibratio o the AD5372/ AD5373 to reduce gai ad offset errors to below LSB. This reductio is achieved by calculatig ew values for the M ad C registers ad reprogrammig them. The M ad C registers should ot be programmed util both the zero-scale ad full-scale errors are calculated. Reducig Zero-Scale Error Zero-scale error ca be reduced as follows:. Set the output to the lowest possible value. 2. Measure the actual output voltage ad compare it to the required value. This gives the zero-scale error. 3. Calculate the umber of LSBs equivalet to the error ad add this umber to the default value of the C register. Note that oly egative zero-scale error ca be reduced. Reducig Full-Scale Error Full-scale error ca be reduced as follows:. Measure the zero-scale error. 2. Set the output to the highest possible value. 3. Measure the actual output voltage ad compare it to the required value. Add this error to the zero-scale error. This is the spa error, which icludes the full-scale error. 4. Calculate the umber of LSBs equivalet to the spa error ad subtract this umber from the default value of the M register. Note that oly positive full-scale error ca be reduced. AD5372 Calibratio Example This example assumes that a 4 V to +8 V output is required. The DAC output is set to 4 V but is measured at 4.03 V. This gives a zero-scale error of 30 mv. LSB = 2 V/65,536 = μv 30 mv = 64 LSBs The full-scale error ca ow be calculated. The output is set to 8 V ad a value of 8.02 V is measured. This gives a full-scale error of +20 mv ad a spa error of +20 mv ( 30 mv) = +50 mv. 50 mv = 273 LSBs The errors ca ow be removed as follows:. Add 64 LSBs to the default C register value: (32, ) = 32, Subtract 273 LSBs from the default M register value: (65, ) = 65, Program the M register to 65,262; program the C register to 32,932. Rev. B Page 7 of 24

18 ADDITIONAL CALIBRATION The techiques described i the previous sectio are usually eough to reduce the zero-scale ad full-scale errors i most applicatios. However, there are limitatios whereby the errors may ot be sufficietly reduced. For example, the offset (C) register ca oly be used to reduce the offset caused by the egative zero-scale error. A positive offset caot be reduced. Likewise, if the maximum voltage is below the ideal value, that is, a egative full-scale error, the gai (M) register caot be used to icrease the gai to compesate for the error. These limitatios ca be overcome by icreasig the referece value. With a 3 V referece, a 2 V spa is achieved. The ideal voltage rage, for the AD5372 or the AD5373, is 4 V to +8 V. Usig a +3. V referece icreases the rage to 4.33 V to V. Clearly, i this case, the offset ad gai errors are isigificat, ad the M ad C registers ca be used to raise the egative voltage to 4 V ad the reduce the maximum voltage to +8 V to give the most accurate values possible. RESET FUNCTION The reset fuctio is iitiated by the RESET pi. O the risig edge of RESET, the AD5372/AD5373 state machie iitiates a reset sequece to reset the X, M, ad C registers to their default values. This sequece typically takes 300 μs, ad the user should ot write to the part durig this time. O power-up, it is recommeded that the user brig RESET high as soo as possible to properly iitialize the registers. Whe the reset sequece is complete (ad provided that CLR is high), the DAC output is at a potetial specified by the default register settigs, which is equivalet to SIGGNDx. The DAC outputs remai at SIGGNDx util the X, M, or C register is updated ad LDAC is take low. The AD5372/AD5373 ca be retured to the default state by pulsig RESET low for at least 30 s. Note that, because the reset fuctio is triggered by the risig edge, brigig RESET low has o effect o the operatio of the AD5372/AD5373. CLEAR FUNCTION CLR is a active low iput that should be high for ormal operatio. The CLR pi has a iteral 500 kω pull-dow resistor. Whe CLR is low, the iput to each of the DAC output buffer stages (VOUT0 to VOUT3) is switched to the exterally set potetial o the relevat SIGGNDx pi. While CLR is low, all LDAC pulses are igored. Whe CLR is take high agai, the DAC outputs retur to their previous values. The cotets of the iput registers ad DAC Register 0 to DAC Register 3 are ot affected by takig CLR low. To prevet glitches from appearig o the outputs, CLR should be brought low wheever the output spa is adjusted by writig to the offset DAC. BUSY AND LDAC FUNCTIONS The value of a X2 (A or B) register is calculated each time the user writes ew data to the correspodig X, C, or M register. Durig the calculatio of X2, the BUSY output goes low. While BUSY is low, the user ca cotiue writig ew data to the X, M, or C register (see the Register Update Rates sectio for more details), but o DAC output updates ca take place. The BUSY pi is bidirectioal ad has a 50 kω iteral pull-up resistor. Whe multiple AD5372 or AD5373 devices are used i oe system, the BUSY pis ca be tied together. This is useful whe it is required that o DAC i ay device be updated util all other DACs are ready. Whe each device has fiished updatig the X2 (A or B) registers, it releases the BUSY pi. If aother device has ot fiished updatig its X2 registers, it holds BUSY low, thus delayig the effect of LDAC goig low. The DAC outputs are updated by takig the LDAC iput low. If LDAC goes low while BUSY is active, the LDAC evet is stored ad the DAC outputs are updated immediately after BUSY goes high. A user ca also hold the LDAC iput permaetly low. I this case, the DAC outputs are updated immediately after BUSY goes high. Wheever the A/B select registers are writte to, BUSY also goes low, for approximately 500 s. The AD5372/AD5373 have flexible addressig that allows writig of data to a sigle chael, all chaels i a group, the same chael i Group 0 to Group 3, the same chael i Group to Group 3, or all chaels i the device. This meas that, 4, 8, or 32 DAC register values may eed to be calculated ad updated. Because there is oly oe multiplier shared amog 32 chaels, this task must be doe sequetially so that the legth of the BUSY pulse varies accordig to the umber of chaels beig updated. Table 9. BUSY Pulse Widths Actio BUSY Pulse Width Loadig iput, C, or M to chael 2.5 μs maximum Loadig iput, C, or M to 4 chaels 3.3 μs maximum Loadig iput, C, or M to 8 chaels 5.7 μs maximum Loadig iput, C, or M to 32 chaels 20. μs maximum BUSY pulse width = ((umber of chaels + ) 600 s) s. 2 A sigle chael update is typically μs. The AD5372/AD5373 cotai a extra feature whereby a DAC register is ot updated uless its X2A or X2B register has bee writte to sice the last time LDAC was brought low. Normally, whe LDAC is brought low, the DAC registers are filled with the cotets of the X2A or X2B register, depedig o the settig of the A/B select registers. However, the AD5372/AD5373 update the DAC register oly if the X2A or X2B data has chaged, thereby removig uecessary digital crosstalk. Rev. B Page 8 of 24

19 POWER-DOWN MODE The AD5372/AD5373 ca be powered dow by settig Bit 0 i the cotrol register to. This turs off the DACs, thus reducig the curret cosumptio. The DAC outputs are coected to their respective SIGGNDx potetials. The power-dow mode does ot chage the cotets of the registers, ad the DACs retur to their previous voltage whe the power-dow bit is cleared to 0. THERMAL SHUTDOWN FUNCTION The AD5372/AD5373 ca be programmed to shut dow the DACs if the temperature o the die exceeds 30 C. Settig Bit i the cotrol register to eables this fuctio (see Table 6). If the die temperature exceeds 30 C, the AD5372/AD5373 eter a thermal shutdow mode, which is equivalet to settig the power-dow bit i the cotrol register to. To idicate that the AD5372/AD5373 have etered thermal shutdow mode, Bit 4 of the cotrol register is set to. The AD5372/AD5373 remai i thermal shutdow mode, eve if the die temperature falls, util Bit i the cotrol register is cleared to 0. TOGGLE MODE The AD5372/AD5373 have two X2 registers per chael, X2A ad X2B, which ca be used to switch the DAC output betwee two levels with ease. This approach greatly reduces the overhead required by a microprocessor, which would otherwise eed to write to each chael idividually. Whe the user writes to the XA, XB, M, or C register, the calculatio egie takes a certai amout of time to calculate the appropriate X2A or X2B value. If a applicatio, such as a data geerator, requires that the DAC output switch betwee two levels oly, ay method that reduces the amout of calculatio time ecessary is advatageous. For the data geerator example, the user eeds oly to set the high ad low levels for each chael oce by writig to the XA ad XB registers. The values of X2A ad X2B are calculated ad stored i their respective registers. The calculatio delay, therefore, happes oly durig the setup phase, that is, whe programmig the iitial values. To toggle a DAC output betwee the two levels, it is oly required to write to the relevat A/B select register to set the MUX2 register bit. Furthermore, because there are eight MUX2 cotrol bits per register, it is possible to update eight chaels with a sigle write. Table 0 shows the bits that correspod to each DAC output. Table 0. DACs Selected by A/B Select Registers A/B Select Bits Register F7 F6 F5 F4 F3 F2 F F0 0 VOUT7 VOUT6 VOUT5 VOUT4 VOUT3 VOUT2 VOUT VOUT0 VOUT5 VOUT4 VOUT3 VOUT2 VOUT VOUT0 VOUT9 VOUT8 2 VOUT23 VOUT22 VOUT2 VOUT20 VOUT9 VOUT8 VOUT7 VOUT6 3 VOUT3 VOUT30 VOUT29 VOUT28 VOUT27 VOUT26 VOUT25 VOUT24 If the bit is set to 0, Register X2A is selected. If the bit is set to, Register X2B is selected. Rev. B Page 9 of 24

20 SERIAL INTERFACE The AD5372/AD5373 cotai a high speed SPI operatig at clock frequecies up to 50 MHz (20 MHz for read operatios). To miimize both the power cosumptio of the device ad o-chip digital oise, the iterface powers up fully oly whe the device is beig writte to, that is, o the fallig edge of SYNC. The serial iterface is 2.5 V LVTTL-compatible whe operatig from a 2.5 V to 3.6 V DVCC supply. It is cotrolled by four pis: SYNC (frame sychroizatio iput), SDI (serial data iput pi), SCLK (clocks data i ad out of the device), ad SDO (serial data output pi for data readback). SPI WRITE MODE The AD5372/AD5373 allow writig of data via the serial iterface to every register directly accessible to the serial iterface, that is, all registers except the X2A, X2B, ad DAC registers. The X2A ad X2B registers are updated whe writig to the XA, XB, M, ad C registers, ad the DAC data registers are updated by LDAC. The serial word (see Table or Table 2) is 24 bits log: 6 (AD5372) or 4 (AD5373) of these bits are data bits; six bits are address bits; ad two bits are mode bits that determie what is doe with the data. Two bits are reserved o the AD5373. The serial iterface works with both a cotiuous ad a burst (gated) serial clock. Serial data applied to SDI is clocked ito the AD5372/AD5373 by clock pulses applied to SCLK. The first fallig edge of SYNC starts the write cycle. At least 24 fallig clock edges must be applied to SCLK to clock i 24 bits of data before SYNC is take high agai. If SYNC is take high before the 24 th fallig clock edge, the write operatio is aborted. If a cotiuous clock is used, SYNC must be take high before the 25 th fallig clock edge. This ihibits the clock withi the AD5372/ AD5373. If more tha 24 fallig clock edges are applied before SYNC is take high agai, the iput data becomes corrupted. If a exterally gated clock of exactly 24 pulses is used, SYNC ca be take high ay time after the 24 th fallig clock edge. The iput register addressed is updated o the risig edge of SYNC. For aother serial trasfer to take place, SYNC must be take low agai. SPI READBACK MODE The AD5372/AD5373 allow data readback via the serial iterface from every register directly accessible to the serial iterface, that is, all registers except the X2A, X2B, ad DAC data registers. To read back a register, it is first ecessary to tell the AD5372/AD5373 which register is to be read. This is achieved by writig a word whose first two bits are the Special Fuctio Code 00 to the device. The remaiig bits the determie which register is to be read back. If a readback commad is writte to a special fuctio register, data from the selected register is clocked out of the SDO pi durig the ext SPI operatio. The SDO pi is ormally threestated but becomes drive as soo as a read commad is issued. The pi remais drive util the register data is clocked out. See Figure 5 for the read timig diagram. Note that due to the timig requiremets of t22 (25 s), the maximum speed of the SPI iterface durig a read operatio should ot exceed 20 MHz. UPDATE RATES The value of the X2A register or the X2B register is calculated each time the user writes ew data to the correspodig X, C, or M register. The calculatio is performed by a three-stage process. The first two stages take approximately 600 s each, ad the third stage takes approximately 300 s. Whe the write to a X, C, or M register is complete, the calculatio process begis. If the write operatio ivolves the update of a sigle DAC chael, the user is free to write to aother register, provided that the write operatio does ot fiish util the first-stage calculatio is complete (that is, 600 s after the completio of the first write operatio). If a group of chaels is beig updated by a sigle write operatio, the first-stage calculatio is repeated for each chael, takig 600 s per chael. I this case, the user should ot complete the ext write operatio util this time has elapsed. Table. AD5372 Serial Word Bit Assigmet I23 I22 I2 I20 I9 I8 I7 I6 I5 I4 I3 I2 I I0 I9 I8 I7 I6 I5 I4 I3 I2 I I0 M M0 A5 A4 A3 A2 A A0 D5 D4 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 Table 2. AD5373 Serial Word Bit Assigmet I23 I22 I2 I20 I9 I8 I7 I6 I5 I4 I3 I2 I I0 I9 I8 I7 I6 I5 I4 I3 I2 I I0 M M0 A5 A4 A3 A2 A A0 D3 D2 D D0 D9 D8 D7 D6 D5 D4 D3 D2 D D0 0 0 Bit I ad Bit I0 are reserved for future use ad should be 0 whe writig the serial word. These bits read back as 0. Rev. B Page 20 of 24

21 CHANNEL ADDRESSING AND SPECIAL MODES If the mode bits are ot 00, the data-word D5 to D0 (AD5372) or D3 to D0 (AD5373) is writte to the device. Address Bit A5 to Address Bit A0 determie which chaels are writte to, ad the mode bits determie to which register (XA, XB, C, or M) the data is writte, as show i Table 3 ad Table 4. Data is to be writte to the XA register whe the A/B bit i the cotrol register is 0, or to the XB register whe the A/B bit is. The AD5372/AD5373 have very flexible addressig that allows the writig of data to a sigle chael, all chaels i a group, the same chael i Group 0 to Group 3, the same chael i Group to Group 3, or all chaels i the device. Table 4 shows which groups ad which chaels are addressed for every combiatio of Address Bit A5 to Address Bit A0. Table 3. Mode Bits M M0 Actio Write to DAC data (X) register 0 Write to DAC offset (C) register 0 Write to DAC gai (M) register 0 0 Special fuctio, used i combiatio with other bits of the data-word Table 4. Group ad Chael Addressig Address Bit A2 Address Bit A5 to Address Bit A3 to Address Bit A All groups, all chaels 00 Group 0, all chaels 00 all chaels 0 all chaels 00 Group 3, all chaels Group 0, Chael 0 Group 0, Chael Group 0, Chael 2 Group 0, Chael 3 Group 0, Chael 4 0 Reserved Group 0, Chael 5 0 Reserved Group 0, Chael 6 Reserved Group 0, Chael 7 Chael 0 Chael Chael 2 Chael 3 Chael 4 Chael 5 Chael 6 Chael 7 Chael 0 Chael Chael 2 Chael 3 Chael 4 Chael 5 Chael 6 Chael 7 Group 3, Chael 0 Group 3, Chael Group 3, Chael 2 Group 3, Chael 3 Group 3, Chael 4 Group 3, Chael 5 Group 3, Chael 6 Group 3, Chael 7 Reserved Group 0, Chael 0 Reserved Group 0, Chael Reserved Group 0, Chael 2 Reserved Group 0, Chael 3 Reserved Group 0, Chael 4 Reserved Group 0, Chael 5 Reserved Group 0, Chael 6 Reserved Group 0, Chael 7 Chael 0 Chael Chael 2 Chael 3 Chael 4 Chael 5 Chael 6 Chael 7 Rev. B Page 2 of 24