FUNCTIONAL BLOCK DIAGRAM DV CC V DD V SS AGND DGND LDAC 14 REGISTER X2A REGISTER A/B MUX MUX X2B REGISTER X2A REGISTER A/B MUX MUX X2B REGISTER

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1 8-Chael, 16-/14-Bit, Serial Iput, Voltage Output DAC AD5362/AD5363 FEATURES 8-chael DAC i 52-lead LQFP ad 56-lead LFCSP packages Guarateed mootoic to 16/14 bits Nomial output voltage rage of 10 V to +10 V Multiple output voltage spas available Thermal shutdow fuctio Chael moitorig multiplexer GPIO fuctio System calibratio fuctio allowig user-programmable offset ad gai Chael groupig ad addressig features Data error checkig feature SPI-compatible serial iterface 2.5 V to 5.5 V digital iterface Digital reset (RESET) Clear fuctio to user-defied SIGGNDx Simultaeous update of DAC outputs APPLICATIONS Istrumetatio Idustrial cotrol systems Level settig i automatic test equipmet (ATE) Variable optical atteuators (VOA) Optical lie cards FUTIONAL BLOCK DIAGRAM DV CC V DD V SS AGND DGND LDAC TEMP_OUT PEC MON_IN0 MON_IN1 MON_OUT GPIO BIN/2SCOMP SY SDI SCLK SDO BUSY RESET CLR TEMP SENSOR CONTROL REGISTER MUX GPIO REGISTER SERIAL INTERFACE STATE MACHINE AD5362/ AD VOUT0 TO VOUT7 6 2 = 16 FOR AD5362 = 14 FOR AD A/B SELECT 8 REGISTER 8 A/B SELECT 8 REGISTER X1 REGISTER M REGISTER C REGISTER X1 REGISTER M REGISTER C REGISTER X1 REGISTER M REGISTER C REGISTER X1 REGISTER M REGISTER C REGISTER TO MUX 2s TO MUX 2s A/B MUX A/B MUX A/B MUX A/B MUX X2A REGISTER X2B REGISTER X2A REGISTER X2B REGISTER X2A REGISTER X2B REGISTER X2A REGISTER X2B REGISTER MUX 2 MUX 2 MUX 2 MUX 2 14 OFS0 14 REGISTER 14 OFS1 REGISTER DAC 4 REGISTER OFFSET DAC 0 DAC 0 REGISTER DAC 0 DAC 3 REGISTER DAC 3 OFFSET DAC 1 DAC 4 DAC 7 REGISTER DAC 7 BUFFER BUFFER BUFFER BUFFER GROUP 0 OUTPUT BUFFER AND POWER- DOWN CONTROL OUTPUT BUFFER AND POWER- DOWN CONTROL GROUP 1 OUTPUT BUFFER AND POWER- DOWN CONTROL OUTPUT BUFFER AND POWER- DOWN CONTROL VREF0 VOUT0 VOUT1 VOUT2 VOUT3 SIGGND0 VREF1 VOUT4 VOUT5 VOUT6 VOUT7 SIGGND Figure 1. Rev. A Iformatio furished by Aalog Devices is believed to be accurate ad reliable. However, o resposibility is assumed by Aalog Devices for its use, or for ay ifrigemets of patets or other rights of third parties that may result from its use. Specificatios subject to chage without otice. No licese is grated by implicatio or otherwise uder ay patet or patet rights of Aalog Devices. Trademarks ad registered trademarks are the property of their respective owers. Oe Techology Way, P.O. Box 9106, Norwood, MA , U.S.A. Tel: Fax: Aalog Devices, Ic. All rights reserved.

2 TABLE OF CONTENTS Features... 1 Applicatios... 1 Fuctioal Block Diagram... 1 Revisio History... 2 Geeral Descriptio... 3 Specificatios... 4 AC Characteristics... 6 Timig Characteristics... 7 Absolute Maximum Ratigs ESD Cautio Pi Cofiguratio ad Fuctio Descriptios Typical Performace Characteristics Termiology Theory of Operatio DAC Architecture Chael Groups A/B Registers ad Gai/Offset Adjustmet Offset DACs Output Amplifier Trasfer Fuctio Referece Selectio Calibratio Additioal Calibratio REVISION HISTORY 3/08 Rev. 0 to Rev. A Added 56-Lead LFCSP_VQ... Uiversal Chages to Table Added t23 Parameter... 7 Chages to Figure Chages to Table Chages to A/B Registers ad Gai/Offset Adjustmet Sectio Reset Fuctio Clear Fuctio BUSY ad LDAC Fuctios BIN/2SCOMP Pi Temperature Sesor Moitor Fuctio GPIO Pi Power-Dow Mode Thermal Shutdow Fuctio Toggle Mode Serial Iterface SPI Write Mode SPI Readback Mode Register Update Rates Packet Error Checkig Chael Addressig ad Special Modes Special Fuctio Mode Applicatios Iformatio Power Supply Decouplig Power Supply Sequecig Iterfacig Examples Outlie Dimesios Orderig Guide Chages to Calibratio Sectio Chages to Reset Fuctio Sectio ad BUSY ad LDAC Fuctios Sectio Chages to Chael Addressig ad Special Modes Sectio.. 23 Updated Outlie Dimesios Chages to Orderig Guide /08 Revisio 0: Iitial Versio Rev. A Page 2 of 28

3 GENERAL DESCRIPTION The AD5362/AD5363 cotai eight 16-/14-bit DACs i a sigle 52-lead LQFP package or 56-lead LFCSP package. The devices provide buffered voltage outputs with a spa of 4 the referece voltage. The gai ad offset of each DAC ca be idepedetly trimmed to remove errors. For eve greater flexibility, the device is divided ito two groups of four DACs, ad the output rage of each group ca be idepedetly adjusted by a offset DAC. The AD5362/AD5363 offer guarateed operatio over a wide supply rage with VSS from 16.5 V to 4.5 V ad VDD from 8 V to 16.5 V. The output amplifier headroom requiremet is 1.4 V, operatig with a load curret of 1 ma. The AD5362/AD5363 have a high speed 4-wire serial iterface that is compatible with SPI, QSPI, MICROWIRE, ad DSP iterface stadards ad ca hadle clock speeds of up to 50 MHz. All the outputs ca be updated simultaeously by takig the LDAC iput low. Each chael has a programmable gai ad a offset adjust register. Each DAC output is gaied ad buffered o chip with respect to a exteral SIGGNDx iput. The DAC outputs ca also be switched to SIGGNDx via the CLR pi. Table 1. High Chael Cout Bipolar DACs Model Resolutio (Bits) Nomial Output Spa Output Chaels Liearity Error (LSB) AD VREF (20 V) 16 ±4 AD VREF (20 V) 16 ±1 AD VREF (20 V) 8 ±4 AD VREF (20 V) 8 ±1 AD VREF (12 V) 40 ±4 AD VREF (12 V) 40 ±1 AD VREF (12 V) 32 ±4 AD VREF (12 V) 32 ±1 AD ±8.75 V 32 ±3 AD ±8.75 V 40 ±3 Rev. A Page 3 of 28

4 SPECIFICATIONS DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = 16.5 V to 4.5 V; VREF = 5 V; AGND = DGND = SIGGND0 = SIGGND1 = 0 V; RL = ope circuit; gai (M), offset (C), ad DAC offset registers at default values; all specificatios TMIN to TMAX, uless otherwise oted. Table 2. Parameter B Versio 1 Uit Test Coditios/Commets ACCURACY Resolutio 16 Bits AD Bits AD5363 Itegral Noliearity (INL) ±4 LSB max AD5362 ±1 LSB max AD5363 Differetial Noliearity (DNL) ±1 LSB max Guarateed mootoic by desig over temperature Zero-Scale Error ±15 mv max Before calibratio Full-Scale Error ±20 mv max Before calibratio Gai Error 0.1 % FSR Before calibratio Zero-Scale Error 2 1 LSB typ After calibratio Full-Scale Error 2 1 LSB typ After calibratio Spa Error of Offset DAC ±75 mv max See the Offset DACs sectio for details VOUTx 3 Temperature Coefficiet 5 ppm FSR/ C typ Icludes liearity, offset, ad gai drift DC Crosstalk μv max Typically 20 μv; measured chael at midscale, full-scale chage o ay other chael REFEREE INPUTS (VREF0, VREF1) 2 VREFx Iput Curret ±10 μa max Per iput; typically ±30 A VREFx Rage 2 2/5 V mi/v max ±2% for specified operatio SIGGND0 AND SIGGND1 INPUTS 2 DC Iput Impedace 50 kω mi Typically 55 kω Iput Rage ±0.5 V mi/v max SIGGNDx Gai 0.995/1.005 mi/max OUTPUT CHARACTERISTICS 2 Output Voltage Rage VSS V mi ILOAD = 1 ma VDD 1.4 V max ILOAD = 1 ma Nomial Output Voltage Rage 10 to +10 V Short-Circuit Curret 15 ma max VOUTx 3 to DVCC, VDD, or VSS Load Curret ±1 ma max Capacitive Load 2200 pf max DC Output Impedace 0.5 Ω max MONITOR PIN (MON_OUT) 2 Output Impedace DAC Output at Positive Full Scale 1000 Ω typ DAC Output at Negative Full Scale 500 Ω typ Three-State Leakage Curret 100 A typ Cotiuous Curret Limit 2 ma max DIGITAL INPUTS Iput High Voltage 1.7 V mi DVCC = 2.5 V to 3.6 V 2.0 V mi DVCC = 3.6 V to 5.5 V Iput Low Voltage 0.8 V max DVCC = 2.5 V to 5.5 V Iput Curret ±1 μa max RESET, SY, SDI, ad SCLK pis ±20 μa max CLR, BIN/2SCOMP, ad GPIO pis Iput Capacitace 2 10 pf max Rev. A Page 4 of 28

5 Parameter B Versio 1 Uit Test Coditios/Commets DIGITAL OUTPUTS (SDO, BUSY, GPIO, PEC) Output Low Voltage 0.5 V max Sikig 200 μa Output High Voltage (SDO) DVCC 0.5 V mi Sourcig 200 μa High Impedace Leakage Curret ±5 μa max SDO oly High Impedace Output Capacitace 2 10 pf typ TEMPERATURE SENSOR (TEMP_OUT) 2 Accuracy ±1 C 25 C ±5 C typ 40 C < T < +85 C Output Voltage at 25 C 1.46 V typ Output Voltage Scale Factor 4.4 mv/ C typ Output Load Curret 200 μa max Curret source oly Power-O Time 10 ms typ To withi ±5 C POWER REQUIREMENTS DVCC 2.5/5.5 V mi/v max VDD 8/16.5 V mi/v max VSS 16.5/ 4.5 V mi/v max Power Supply Sesitivity 2 Full Scale/ VDD 75 db typ Full Scale/ VSS 75 db typ Full Scale/ DVCC 90 db typ DICC 2 ma max DVCC = 5.5 V, VIH = DVCC, VIL = GND IDD 8.5 ma max Outputs = 0 V ad uloaded ISS 8.5 ma max Outputs = 0 V ad uloaded Power-Dow Mode Bit 0 i the cotrol register is 1 DICC 5 μa typ IDD 35 μa typ ISS 35 μa typ Power Dissipatio Power Dissipatio Uloaded (P) 209 mw max VSS = 12 V, VDD = 12 V, DVCC = 2.5 V Juctio Temperature C max TJ = TA + PTOTAL θja 1 Temperature rage for B versio: 40 C to +85 C. Typical specificatios are at 25 C. 2 Guarateed by desig ad characterizatio; ot productio tested. 3 VOUTx refers to ay of VOUT0 to VOUT7. 4 θja represets the package thermal impedace. Rev. A Page 5 of 28

6 AC CHARACTERISTICS DVCC = 2.5 V; VDD = 15 V; VSS = 15 V; VREF = 5 V; AGND = DGND = SIGGND0 = SIGGND1 = 0 V; CL = 200 pf; RL = 10 kω; gai (M), offset (C), ad DAC offset registers at default values; all specificatios TMIN to TMAX, uless otherwise oted. Table 3. Parameter B Versio 1 Uit Test Coditios/Commets DYNAMIC PERFORMAE 1 Output Voltage Settlig Time 20 μs typ Full-scale chage 30 μs max DAC latch cotets alterately loaded with all 0s ad all 1s Slew Rate 1 V/μs typ Digital-to-Aalog Glitch Eergy 5 V-s typ Glitch Impulse Peak Amplitude 10 mv max Chael-to-Chael Isolatio 100 db typ VREF0, VREF1 = 2 V p-p, 1 khz DAC-to-DAC Crosstalk 10 V-s typ Digital Crosstalk 0.2 V-s typ Digital Feedthrough 0.02 V-s typ Effect of iput bus activity o DAC output uder test Output Noise Spectral 10 khz 250 V/ Hz typ VREF0 = VREF1 = 0 V 1 Guarateed by desig ad characterizatio; ot productio tested. Rev. A Page 6 of 28

7 TIMING CHARACTERISTICS AD5362/AD5363 DVCC = 2.5 V to 5.5 V; VDD = 9 V to 16.5 V; VSS = 16.5 V to 8 V; VREF = 5 V; AGND = DGND = SIGGND = 0 V; CL = 200 pf to GND; RL = ope circuit; gai (M), offset (C), ad DAC offset registers at default values; all specificatios TMIN to TMAX, uless otherwise oted. Table 4. SPI Iterface Parameter 1, 2, 3 Limit at TMIN, TMAX Uit Descriptio t1 20 s mi SCLK cycle time t2 8 s mi SCLK high time t3 8 s mi SCLK low time t4 11 s mi SY fallig edge to SCLK fallig edge setup time t5 20 s mi Miimum SY high time t6 10 s mi 24 th SCLK fallig edge to SY risig edge t7 5 s mi Data setup time t8 5 s mi Data hold time t s max SY risig edge to BUSY fallig edge t10 1/1.5 μs typ/μs max BUSY pulse width low (sigle-chael update); see Table 9 t s max Sigle-chael update cycle time t12 20 s mi SY risig edge to LDAC fallig edge t13 10 s mi LDAC pulse width low t14 3 μs max BUSY risig edge to DAC output respose time t15 0 s mi BUSY risig edge to LDAC fallig edge t16 3 μs max LDAC fallig edge to DAC output respose time t17 20/30 μs typ/μs max DAC output settlig time t s max CLR/RESET pulse activatio time t19 30 s mi RESET pulse width low t μs max RESET time idicated by BUSY low t s mi Miimum SY high time i readback mode t s max SCLK risig edge to SDO valid t23 80 s max RESET risig edge to BUSY fallig edge 1 Guarateed by desig ad characterizatio; ot productio tested. 2 All iput sigals are specified with tr = tf = 2 s (10% to 90% of DVCC) ad timed from a voltage level of 1.2 V. 3 See Figure 4 ad Figure 5. 4 t9 is measured with the load circuit show i Figure 2. 5 t22 is measured with the load circuit show i Figure µA I OL TO OUTPUT PIN DV CC R L 2.2kΩ C L 50pF V OL Figure 2. Load Circuit for BUSY Timig Diagram TO OUTPUT PIN C L 50pF 200µA I OH V OH (MIN) V OL (MAX) Figure 3. Load Circuit for SDO Timig Diagram Rev. A Page 7 of 28

8 t 1 SCLK t 3 t 11 t 4 t 2 t 6 SY t 5 t 7 t 8 SDI DB23 DB0 t 9 BUSY t 10 t 12 t 13 LDAC 1 t 17 VOUTx 1 t 14 t 15 t 13 LDAC 2 t 17 VOUTx 2 t 16 CLR t 18 VOUTx t 19 RESET VOUTx BUSY t 18 t 20 t 23 1 LDAC ACTIVE DURING BUSY. 2 LDAC ACTIVE AFTER BUSY Figure 4. SPI Write Timig Rev. A Page 8 of 28

9 t 22 SCLK 48 t 21 SY SDI DB23 DB0 DB23 DB0 INPUT WORD SPECIFIES REGISTER TO BE READ NOP CONDITION SDO DB0 DB23 DB15 DB0 LSB FROM PREVIOUS WRITE Figure 5. SPI Read Timig SELECTED REGISTER DATA CLOCKED OUT OUTPUT VOLTAGE V MAX ACTUAL TRANSFER FUTION FULL-SCALE ERROR + ZERO-SCALE ERROR IDEAL TRANSFER FUTION 0 DAC CODE 2 N 1 = 16 FOR AD5362 = 14 FOR AD5363 V MIN ZERO-SCALE ERROR Figure 6. DAC Trasfer Fuctio Rev. A Page 9 of 28

10 ABSOLUTE MAXIMUM RATINGS TA = 25 C, uless otherwise oted. Trasiet currets of up to 60 ma do ot cause SCR latch-up. Table 5. Parameter Ratig VDD to AGND 0.3 V to +17 V VSS to AGND 17 V to +0.3 V DVCC to DGND 0.3 V to +7 V Digital Iputs to DGND 0.3 V to DVCC V Digital Outputs to DGND 0.3 V to DVCC V VREF0, VREF1 to AGND 0.3 V to +5.5 V VOUT0 through VOUT7 to AGND VSS 0.3 V to VDD V SIGGND0, SIGGND1 to AGND 1 V to +1 V AGND to DGND 0.3 V to +0.3 V MON_IN0, MON_IN1, MON_OUT VSS 0.3 V to VDD V to AGND Operatig Temperature Rage (TA) Idustrial (J Versio) 40 C to +85 C Storage Temperature Rage 65 C to +150 C Operatig Juctio Temperature 130 C (TJ max) θja Thermal Impedace 52-Lead LQFP 38 C/W 56-Lead LFCSP 25 C/W Reflow Solderig Peak Temperature 230 C Time at Peak Temperature 10 sec to 40 sec Stresses above those listed uder Absolute Maximum Ratigs may cause permaet damage to the device. This is a stress ratig oly; fuctioal operatio of the device at these or ay other coditios above those idicated i the operatioal sectio of this specificatio is ot implied. Exposure to absolute maximum ratig coditios for exteded periods may affect device reliability. ESD CAUTION Rev. A Page 10 of 28

11 PIN CONFIGURATION AND FUTION DESCRIPTIONS AGND DGND DV CC SDO PEC SDI SCLK SY DV CC DGND CLR LDAC AGND DGND DV CC SDO PEC SDI SCLK SY DV CC DGND LDAC 1 CLR 2 RESET 3 BIN/2SCOMP 4 BUSY 5 GPIO 6 MON_OUT 7 MON_IN V DD 11 V SS 12 VREF1 13 PIN 1 INDICATOR AD5362/ AD5363 TOP VIEW (Not to Scale) SIGGND0 37 VOUT3 36 VOUT2 35 VOUT1 34 VOUT0 33 TEMP_OUT 32 MON_IN1 31 VREF V SS 28 V DD 27 RESET 1 BIN/2SCOMP 2 BUSY 3 GPIO 4 MON_OUT 5 MON_IN V DD 12 V SS 13 VREF1 14 = NO CONNECT PIN 1 INDICATOR AD5362/ AD5363 TOP VIEW (Not to Scale) SIGGND0 39 VOUT3 38 VOUT2 37 VOUT1 36 VOUT0 35 TEMP_OUT 34 MON_IN1 33 VREF V SS 29 V DD = NO CONNECT VOUT4 VOUT5 VOUT6 VOUT7 SIGGND1 Figure Lead LQFP Pi Cofiguratio VOUT4 VOUT5 VOUT6 VOUT7 SIGGND1 Figure Lead LFCSP Pi Cofiguratio Table 6. Pi Fuctio Descriptios Pi No. LQFP LFCSP Memoic Descriptio 1 55 LDAC Load DAC Logic Iput (Active Low). See the BUSY ad LDAC Fuctios sectio for more iformatio CLR Asychroous Clear Iput (Level Sesitive, Active Low). See the Clear Fuctio sectio for more iformatio. 3 1 RESET Digital Reset Iput. 4 2 BIN/2SCOMP Data Format Digital Iput. Coectig this pi to DGND selects offset biary. Settig this pi to 1 selects twos complemet. This iput has a weak pull-dow. 5 3 BUSY Digital Iput/Ope-Drai Output. BUSY is ope drai whe it is a output. See the BUSY ad LDAC Fuctios sectio for more iformatio. 6 4 GPIO Digital I/O Pi. This pi ca be cofigured as a iput or output that ca be read back or programmed high or low via the serial iterface. Whe cofigured as a iput, this pi has a weak pull-dow. 7 5 MON_OUT Aalog Multiplexer Output. Ay DAC output, the MON_IN0 iput, or the MON_IN1 iput ca be routed to this output for moitorig. 8, 32 6, 34 MON_IN0, MON_IN1 Aalog Multiplexer Iputs. Ca be routed to MON_OUT. 9, 10, 14, 20 to 27, 30, 39 to 42 7 to 11, 15, 16, 22 to 28, 31, 32, 41 to 44 No Coect. 11, 28 12, 29 VDD Positive Aalog Power Supply; 9 V to 16.5 V for specified performace. These pis should be decoupled with 0.1 μf ceramic capacitors ad 10 μf capacitors. 12, 29 13, 30 VSS Negative Aalog Power Supply; 16.5 V to 8 V for specified performace. These pis should be decoupled with 0.1 μf ceramic capacitors ad 10 μf capacitors VREF1 Referece Iput for DAC 4 to DAC 7. This referece voltage is referred to AGND. 34 to 37, 15 to to 39, 17 to 20 VOUT0 to VOUT7 DAC Outputs. Buffered aalog outputs for each of the eight DAC chaels. Each aalog output is capable of drivig a output load of 10 kω to groud. Typical output impedace of these amplifiers is 0.5 Ω SIGGND1 Referece Groud for DAC 4 to DAC 7. VOUT4 to VOUT7 are refereced to this voltage VREF0 Referece Iput for DAC 0 to DAC 3. This referece voltage is referred to AGND. Rev. A Page 11 of 28

12 Pi No. LQFP LFCSP Memoic Descriptio TEMP_OUT Provides a output voltage proportioal to the chip temperature, typically 1.46 V at 25 C with a output variatio of 4.4 mv/ C SIGGND0 Referece Groud for DAC 0 to DAC 3. VOUT0 to VOUT3 are refereced to this voltage. 43, 51 45, 53 DGND Groud for All Digital Circuitry. Both DGND pis should be coected to the DGND plae. 44, 50 46, 52 DVCC Logic Power Supply; 2.5 V to 5.5 V. These pis should be decoupled with 0.1 μf ceramic capacitors ad 10 μf capacitors SY Active Low or SY Iput for SPI Iterface. This is the frame sychroizatio sigal for the SPI serial iterface. See Figure 4, Figure 5, ad the Serial Iterface sectio for more details SCLK Serial Clock Iput for SPI Iterface. See Figure 4, Figure 5, ad the Serial Iterface sectio for more details SDI Serial Data Iput for SPI Iterface. See Figure 4, Figure 5, ad the Serial Iterface sectio for more details PEC Packet Error Check Output. This is a ope-drai output with a 50 kω pull-up that goes low if the packet error check fails SDO Serial Data Output for SPI Iterface. See Figure 4, Figure 5, ad the Serial Iterface sectio for more details AGND Groud for All Aalog Circuitry. The AGND pi should be coected to the AGND plae. Exposed Paddle EP Exposed Paddle. Coect to VSS. Rev. A Page 12 of 28

13 TYPICAL PERFORMAE CHARACTERISTICS AD5362/AD5363 T A = 25 C V SS = 15V V DD = +15V V REF = V INL (LSB) 0 AMPLITUDE (V) DAC CODE TIME (µs) Figure 9. Typical AD5362 INL Plot Figure 12. Digital Crosstalk V DD = +15V V SS = 15V DV CC = +5V V REF = +3V INL ERROR (LSB) 0 DNL (LSB) TEMPERATURE ( C) Figure 10. Typical INL Error vs. Temperature DAC CODE Figure 13. Typical AD5362 DNL Plot T A = 25 C V SS = 15V V DD = +15V V REF = V AMPLITUDE (V) 0.01 OUTPUT NOISE (V/ Hz) TIME (µs) Figure 11. Aalog Crosstalk Due to LDAC FREQUEY (Hz) Figure 14. Output Noise Spectral Desity Rev. A Page 13 of 28

14 V SS = 12V V DD = +12V V REF = +3V DV CC = 5V T A = 25 C DI CC (ma) DV CC = +5.5V DV CC = +2.5V DV CC = +3.6V NUMBER OF UNITS TEMPERATURE ( C) DI CC (ma) Figure 15. DICC vs. Temperature Figure 18. Typical DICC Distributio I DD I DD /I SS (ma) 5.5 I SS VOLTAGE (V) V SS = 12V V DD = +12V V REF = +3V TEMPERATURE ( C) TEMPERATURE ( C) Figure 16. IDD/ISS vs. Temperature Figure 19. TEMP_OUT Voltage vs. Temperature V SS = 15V V DD = +15V T A = 25 C 1.0 FULL-SCALE NUMBER OF UNITS VOUTx MON_OUT (V) MIDSCALE ZERO-SCALE I DD (ma) Figure 17. Typical IDD Distributio MON_OUT CURRENT (ma) Figure 20. VOUTx MON_OUT Error vs. MON_OUT Curret Rev. A Page 14 of 28

15 TERMINOLOGY Itegral Noliearity (INL) Itegral oliearity, or edpoit liearity, is a measure of the maximum deviatio from a straight lie passig through the edpoits of the DAC trasfer fuctio. It is measured after adjustig for zero-scale error ad full-scale error ad is expressed i least sigificat bits (LSB). Differetial Noliearity (DNL) Differetial oliearity is the differece betwee the measured chage ad the ideal 1 LSB chage betwee ay two adjacet codes. A specified differetial oliearity of 1 LSB maximum esures mootoicity. Zero-Scale Error Zero-scale error is the error i the DAC output voltage whe all 0s are loaded ito the DAC register. Zero-scale error is a measure of the differece betwee VOUT (actual) ad VOUT (ideal), expressed i millivolts, whe the chael is at its miimum value. Zero-scale error is maily due to offsets i the output amplifier. Full-Scale Error Full-scale error is the error i the DAC output voltage whe all 1s are loaded ito the DAC register. Full-scale error is a measure of the differece betwee VOUT (actual) ad VOUT (ideal), expressed i millivolts, whe the chael is at its maximum value. Full-scale error does ot iclude zero-scale error. Gai Error Gai error is the differece betwee full-scale error ad zero-scale error. It is expressed as a percetage of the fullscale rage (FSR). Gai Error = Full-Scale Error Zero-Scale Error VOUT Temperature Coefficiet The VOUT temperature coefficiet icludes output error cotributios from liearity, offset, ad gai drift. DC Output Impedace DC output impedace is the effective output source resistace. It is domiated by package lead resistace. DC Crosstalk The DAC outputs are buffered by op amps that share commo VDD ad VSS power supplies. If the dc load curret chages i oe chael (due to a update), this chage ca result i a further dc chage i oe or more chael outputs. This effect is more sigificat at high load currets ad is reduced as the load currets are reduced. With high impedace loads, the effect is virtually immeasurable. Multiple VDD ad VSS termials are provided to miimize dc crosstalk. Output Voltage Settlig Time Output voltage settlig time is the amout of time it takes for the output of a DAC to settle to a specified level for a full-scale iput chage. Digital-to-Aalog Glitch Eergy Digital-to-aalog glitch eergy is the amout of eergy that is ijected ito the aalog output at the major code trasitio. It is specified as the area of the glitch i V-s. It is measured by togglig the DAC register data betwee 0x7FFF ad 0x8000 (AD5362) or 0x1FFF ad 0x2000 (AD5363). Chael-to-Chael Isolatio Chael-to-chael isolatio refers to the proportio of iput sigal from oe DAC referece iput that appears at the output of aother DAC operatig from aother referece. It is expressed i decibels ad measured at midscale. DAC-to-DAC Crosstalk DAC-to-DAC crosstalk is the glitch impulse that appears at the output of oe coverter due to both the digital chage ad subsequet aalog output chage at aother coverter. It is specified i V-s. Digital Crosstalk Digital crosstalk is defied as the glitch impulse trasferred to the output of oe coverter due to a chage i the DAC register code of aother coverter. It is specified i V-s. Digital Feedthrough Whe the device is ot selected, high frequecy logic activity o the digital iputs of the device ca be capacitively coupled both across ad through the device to appear as oise o the VOUT pis. It ca also be coupled alog the supply ad groud lies. This oise is digital feedthrough. Output Noise Spectral Desity Output oise spectral desity is a measure of iterally geerated radom oise. Radom oise is characterized as a spectral desity (voltage per Hz). It is measured by loadig all DACs to midscale ad measurig oise at the output. It is measured i V/ Hz. Rev. A Page 15 of 28

16 THEORY OF OPERATION DAC ARCHITECTURE The AD5362/AD5363 cotai eight DAC chaels ad eight output amplifiers i a sigle package. The architecture of a sigle DAC chael cosists of a 16-bit (AD5362) or 14-bit (AD5363) resistor-strig DAC followed by a output buffer amplifier. The resistor-strig sectio is simply a strig of resistors, of equal value, from VREF0 or VREF1 to AGND. This type of architecture guaratees DAC mootoicity. The 16-bit (AD5362) or 14-bit (AD5363) biary digital code loaded to the DAC register determies at which ode o the strig the voltage is tapped off before beig fed ito the output amplifier. The output amplifier multiplies the DAC output voltage by 4. The omial output spa is 12 V with a 3 V referece ad 20 V with a 5 V referece. CHANNEL GROUPS The eight DAC chaels of the AD5362/AD5363 are arraged ito two groups of four chaels. The four DACs of Group 0 derive their referece voltage from VREF0. The four DACs of Group 1 derive their referece voltage from VREF1. Each group has its ow sigal groud pi. Table 7. AD5362/AD5363 Registers Register Name Word Legth i Bits Descriptio X1A (Group) (Chael) 16 (14) Iput Data Register A, oe for each DAC chael. X1B (Group) (Chael) 16 (14) Iput Data Register B, oe for each DAC chael. M (Group) (Chael) 16 (14) Gai trim registers, oe for each DAC chael. C (Group) (Chael) 16 (14) Offset trim registers, oe for each DAC chael. X2A (Group) (Chael) 16 (14) Output Data Register A, oe for each DAC chael. These registers store the fial, calibrated DAC data after gai ad offset trimmig. They are ot readable or directly writable. X2B (Group) (Chael) 16 (14) Output Data Register B, oe for each DAC chael. These registers store the fial, calibrated DAC data after gai ad offset trimmig. They are ot readable or directly writable. DAC (Group) (Chael) Data registers from which the DACs take their fial iput data. The DAC registers are updated from the X2A or X2B registers. They are ot readable or directly writable. OFS0 14 Offset DAC 0 data register: sets offset for Group 0. OFS1 14 Offset DAC 1 data register: sets offset for Group 1. Cotrol 5 Bit 4 = overtemperature idicator. Bit 3 = PEC error flag. Bit 2 = A/B select. Bit 1 = thermal shutdow. Bit 0 = software power-dow. Moitor 6 Bit 5 = moitor eable. Bit 4 = moitor DACs or moitor MON_INx pi. Bit 3 to Bit 0 = moitor selectio cotrol. GPIO 2 Bit 1 = GPIO cofiguratio. Bit 0 = GPIO data. A/B Select 0 8 Bits [3:0] i this register determie whether a DAC i Group 0 takes its data from Register X2A or Register X2B (0 = X2A, 1 = X2B). A/B Select 1 8 Bits [3:0] i this register determie whether a DAC i Group 1 takes its data from Register X2A or Register X2B (0 = X2A, 1 = X2B). Table 8. AD5362/AD5363 Iput Register Default Values Register Name AD5362 Default Value AD5363 Default Value X1A, X1B 0x8000 0x2000 M 0xFFFF 0x3FFF C 0x8000 0x2000 OFS0, OFS1 0x2000 0x2000 Cotrol 0x00 0x00 A/B Select 0 ad A/B Select 1 0x00 0x00 Rev. A Page 16 of 28

17 A/B REGISTERS AND GAIN/OFFSET ADJUSTMENT Each DAC chael has seve data registers. The actual DAC data-word ca be writte to either the X1A or X1B iput register, depedig o the settig of the A/B bit i the cotrol register. If the A/B bit is 0, data is writte to the X1A register. If the A/B bit is 1, data is writte to the X1B register. Note that this sigle bit is a global cotrol ad affects every DAC chael i the device. It is ot possible to set up the device o a perchael basis so that some writes are to X1A registers ad some writes are to X1B registers. X1A REGISTER X1B REGISTER M REGISTER C REGISTER MUX X2A REGISTER X2B REGISTER MUX DAC REGISTER Figure 21. Data Registers Associated with Each DAC Chael DAC Each DAC chael also has a gai (M) register ad a offset (C) register, which allow trimmig out of the gai ad offset errors of the etire sigal chai. Data from the X1A register is operated o by a digital multiplier ad adder cotrolled by the cotets of the M ad C registers. The calibrated DAC data is the stored i the X2A register. Similarly, data from the X1B register is operated o by the multiplier ad adder ad stored i the X2B register. Although a multiplier ad a adder symbol are show i Figure 21 for each chael, there is oly oe multiplier ad oe adder i the device, which are shared amog all chaels. This has implicatios for the update speed whe several chaels are updated at oce, as described i the Register Update Rates sectio. Each time data is writte to the X1A register, or to the M or C register with the A/B cotrol bit set to 0, the X2A data is recalculated ad the X2A register is automatically updated. Similarly, X2B is updated each time data is writte to X1B, or to M or C with A/B set to 1. The X2A ad X2B registers are ot readable or directly writable by the user. Data output from the X2A ad X2B registers is routed to the fial DAC register by a multiplexer. A 4-bit A/B select register associated with each group of four DACs cotrols whether each idividual DAC takes its data from the X2A or X2B register. If a bit i this register is 0, the DAC takes its data from the X2A register; if 1, the DAC takes its data from the X2B register. Note that because there are eight bits i two registers, it is possible to set up, o a per-chael basis, whether each DAC takes its data from the X2A or X2B register. A global commad is also provided that sets all bits i the A/B select registers to 0 or to All DACs i the AD5362/AD5363 ca be updated simultaeously by takig LDAC low whe each DAC register is updated from either its X2A or X2B register, depedig o the settig of the A/B select registers. The DAC register is ot readable or directly writable by the user. LDAC ca be permaetly tied low, ad the DAC output is updated wheever ew data appears i the appropriate DAC register. OFFSET DACS I additio to the gai ad offset trim for each DAC, there are two 14-bit offset DACs, oe for Group 0 ad oe for Group 1. These allow the output rage of all DACs coected to them to be offset withi a defied rage. Thus, subject to the limitatios of headroom, it is possible to set the output rage of Group 0 or Group 1 to be uipolar positive, uipolar egative, or bipolar, either symmetrical or asymmetrical about 0 V. The DACs i the AD5362/AD5363 are factory trimmed with the offset DACs set at their default values. This gives the best offset ad gai performace for the default output rage ad spa. Whe the output rage is adjusted by chagig the value of the offset DAC, a extra offset is itroduced due to the gai error of the offset DAC. The amout of offset is depedet o the magitude of the referece ad how much the offset DAC moves from its default value. See the Specificatios sectio for this offset. The worst-case offset occurs whe the offset DAC is at positive or egative full scale. This value ca be added to the offset preset i the mai DAC chael to give a idicatio of the overall offset for that chael. I most cases, the offset ca be removed by programmig the C register of the chael with a appropriate value. The extra offset caused by the offset DAC eeds to be take ito accout oly whe the offset DAC is chaged from its default value. Figure 22 shows the allowable code rage that ca be loaded to the offset DAC, depedig o the referece value used. Thus, for a 5 V referece, the offset DAC should ot be programmed with a value greater tha 8192 (0x2000). VREF (V) OFFSET DAC CODE Figure 22. Offset DAC Code Rage RESERVED Rev. A Page 17 of 28

18 OUTPUT AMPLIFIER Because the output amplifiers ca swig to 1.4 V below the positive supply ad 1.4 V above the egative supply, this limits how much the output ca be offset for a give referece voltage. For example, it is ot possible to have a uipolar output rage of 20 V, because the maximum supply voltage is ±16.5 V. SIGGNDx R4 60kΩ OFFSET DAC DAC CHANNEL R3 20kΩ R5 60kΩ R1 20kΩ R2 20kΩ S2 CLR S1 CLR R6 10kΩ S3 SIGGNDx Figure 23. Output Amplifier ad Offset DAC OUTPUT Figure 23 shows details of a DAC output amplifier ad its coectios to the offset DAC. O power-up, S1 is ope, discoectig the amplifier from the output. S3 is closed, so the output is pulled to SIGGNDx (R1 ad R2 are greater tha R6). S2 is also closed to prevet the output amplifier from beig ope-loop. If CLR is low at power-up, the output remais i this coditio util CLR is take high. The DAC registers ca be programmed, ad the outputs assume the programmed values whe CLR is take high. Eve if CLR is high at power-up, the output remais i this coditio util VDD > 6 V ad VSS < 4 V ad the iitializatio sequece has fiished. The outputs the go to their power-o default value. TRANSFER FUTION The output voltage of a DAC i the AD5362/AD5363 is depedet o the value i the iput register, the value of the M ad C registers, ad the value i the offset DAC. AD5362 Trasfer Fuctio The iput code is the value i the X1A or X1B register that is applied to the DAC (X1A, X1B default code = 32,768). DAC_CODE = INPUT_CODE (M + 1)/ C 2 15 where: M = code i gai register default code = C = code i offset register default code = The DAC output voltage is calculated as follows: VOUT = 4 VREF (DAC_CODE (OFFSET_CODE 4))/ VSIGGND where: DAC_CODE should be withi the rage of 0 to 65,535. For 12 V spa, VREF = 3.0 V. For 20 V spa, VREF = 5.0 V. OFFSET_CODE is the code loaded to the offset DAC. It is multiplied by 4 i the trasfer fuctio because this DAC is a 14-bit device. O power-up, the default code loaded to the CLR offset DAC is 8192 (0x2000). With a 5 V referece, this gives a spa of 10 V to +10 V. AD5363 Trasfer Fuctio The iput code is the value i the X1A or X1B register that is applied to the DAC (X1A, X1B default code = 8192). DAC_CODE = INPUT_CODE (M + 1)/ C 2 13 where: M = code i gai register default code = C = code i offset register default code = The DAC output voltage is calculated as follows: VOUT = 4 VREF (DAC_CODE OFFSET_CODE)/ VSIGGND where: DAC_CODE should be withi the rage of 0 to 16,383. For 12 V spa, VREF = 3.0 V. For 20 V spa, VREF = 5.0 V. OFFSET_CODE is the code loaded to the offset DAC. O powerup, the default code loaded to the offset DAC is 8192 (0x2000). With a 5 V referece, this gives a spa of 10 V to +10 V. REFEREE SELECTION The AD5362/AD5363 have two referece iput pis. The voltage applied to the referece pis determies the output voltage spa o VOUT0 to VOUT7. VREF0 determies the voltage spa for VOUT0 to VOUT3 (Group 0), ad VREF1 determies the voltage spa for VOUT4 to VOUT7 (Group 1). The referece voltage applied to each VREF pi ca be differet, if required, allowig each group of four chaels to have a differet voltage spa. The output voltage rage ad spa ca be adjusted further by programmig the offset ad gai registers for each chael as well as programmig the offset DAC. If the offset ad gai features are ot used (that is, the M ad C registers are left at their default values), the required referece levels ca be calculated as follows: VREF = (VOUTMAX VOUTMIN)/4 If the offset ad gai features of the AD5362/AD5363 are used, the required output rage is slightly differet. The selected output rage should take ito accout the system offset ad gai errors that eed to be trimmed out. Therefore, the selected output rage should be larger tha the actual, required rage. The required referece levels ca be calculated as follows: 1. Idetify the omial output rage o VOUT. 2. Idetify the maximum offset spa ad the maximum gai required o the full output sigal rage. 3. Calculate the ew maximum output rage o VOUT, icludig the expected maximum offset ad gai errors. 4. Choose the ew required VOUTMAX ad VOUTMIN, keepig the VOUT limits cetered o the omial values. Note that VDD ad VSS must provide sufficiet headroom. 5. Calculate the value of VREF as follows: VREF = (VOUTMAX VOUTMIN)/4 Rev. A Page 18 of 28

19 Referece Selectio Example If Nomial output rage = 20 V ( 10 V to +10 V) Offset error = ±100 mv Gai error = ±3%, ad SIGGND = AGND = 0 V The Gai error = ±3% => Maximum positive gai error = 3% => Output rage icludig gai error = (20) = 20.6 V Offset error = ±100 mv => Maximum offset error spa = 2(100 mv) = 0.2 V => Output rage icludig gai error ad offset error = 20.6 V V = 20.8 V VREF calculatio Actual output rage = 20.6 V, that is, 10.3 V to V (cetered); VREF = (10.3 V V)/4 = 5.15 V If the solutio yields a icoveiet referece level, the user ca adopt oe of the followig approaches: Use a resistor divider to divide dow a coveiet, higher referece level to the required level. Select a coveiet referece level above VREF ad modify the gai ad offset registers to digitally dowsize the referece. I this way, the user ca use almost ay coveiet referece level but ca reduce the performace by overcompactio of the trasfer fuctio. Use a combiatio of these two approaches. CALIBRATION The user ca perform a system calibratio o the AD5362/ AD5363 to reduce gai ad offset errors to below 1 LSB. This reductio is achieved by calculatig ew values for the M ad C registers ad reprogrammig them. The M ad C registers should ot be programmed util both the zero-scale ad full-scale errors are calculated. Reducig Zero-Scale Error Zero-scale error ca be reduced as follows: 1. Set the output to the lowest possible value. 2. Measure the actual output voltage ad compare it to the required value. This gives the zero-scale error. 3. Calculate the umber of LSBs equivalet to the error ad add this umber to the default value of the C register. Note that oly egative zero-scale error ca be reduced. Reducig Full-Scale Error Full-scale error ca be reduced as follows: 1. Measure the zero-scale error. 2. Set the output to the highest possible value. 3. Measure the actual output voltage ad compare it to the required value. Add this error to the zero-scale error. This is the spa error, which icludes the full-scale error. 4. Calculate the umber of LSBs equivalet to the spa error ad subtract this umber from the default value of the M register. Note that oly positive full-scale error ca be reduced. AD5362 Calibratio Example This example assumes that a 10 V to +10 V output is required. The DAC output is set to 10 V but measured at V. This gives a zero-scale error of 30 mv. 1 LSB = 20 V/65,536 = μv 30 mv = 98 LSBs The full-scale error ca ow be calculated. The output is set to 10 V ad a value of V is measured. This gives a full-scale error of +20 mv ad a spa error of +20 mv ( 30 mv) = +50 mv. 50 mv = 164 LSBs The errors ca ow be removed as follows: 1. Add 98 LSBs to the default C register value: (32, ) = 32, Subtract 164 LSBs from the default M register value: (65, ) = 65, Program the M register to 65,371; program the C register to 32,866. ADDITIONAL CALIBRATION The techiques described i the previous sectio are usually eough to reduce the zero-scale ad full-scale errors i most applicatios. However, there are limitatios whereby the errors may ot be sufficietly reduced. For example, the offset (C) register ca oly be used to reduce the offset caused by the egative zero-scale error. A positive offset caot be reduced. Likewise, if the maximum voltage is below the ideal value, that is, a egative full-scale error, the gai (M) register caot be used to icrease the gai to compesate for the error. These limitatios ca be overcome by icreasig the referece value. With a 2.5 V referece, a 10 V spa is achieved. The ideal voltage rage, for the AD5362 or the AD5363, is 5 V to +5 V. Usig a +2.6 V referece icreases the rage to 5.2 V to +5.2 V. Clearly, i this case, the offset ad gai errors are isigificat, ad the M ad C registers ca be used to raise the egative voltage to 5 V ad the reduce the maximum voltage to +5 V to give the most accurate values possible. Rev. A Page 19 of 28

20 RESET FUTION The reset fuctio is iitiated by the RESET pi. O the risig edge of RESET, the AD5362/AD5363 state machie iitiates a reset sequece to reset the X, M, ad C registers to their default values. This sequece typically takes 300 μs, ad the user should ot write to the part durig this time. O power-up, it is recommeded that the user brig RESET high as soo as possible to properly iitialize the registers. Whe the reset sequece is complete (ad provided that CLR is high), the DAC output is at a potetial specified by the default register settigs, which is equivalet to SIGGNDx. The DAC outputs remai at SIGGNDx util the X, M, or C register is updated ad LDAC is take low. The AD5362/AD5363 ca be retured to the default state by pulsig RESET low for at least 30 s. Note that, because the reset fuctio is triggered by the risig edge, brigig RESET low has o effect o the operatio of the AD5362/AD5363. CLEAR FUTION CLR is a active low iput that should be high for ormal operatio. The CLR pi has a iteral 500 kω pull-dow resistor. Whe CLR is low, the iput to each of the DAC output buffer stages (VOUT0 to VOUT7) is switched to the exterally set potetial o the relevat SIGGNDx pi. While CLR is low, all LDAC pulses are igored. Whe CLR is take high agai, the DAC outputs retur to their previous values. The cotets of the iput registers ad DAC Register 0 to DAC Register 7 are ot affected by takig CLR low. To prevet glitches appearig o the outputs, CLR should be brought low wheever the output spa is adjusted by writig to the offset DAC. BUSY AND LDAC FUTIONS The value of a X2 (A or B) register is calculated each time the user writes ew data to the correspodig X1, C, or M registers. Durig the calculatio of X2, the BUSY output goes low. While BUSY is low, the user ca cotiue writig ew data to the X1, M, or C registers (see the Register Update Rates sectio for more details), but o DAC output updates ca take place. The BUSY pi is bidirectioal ad has a 50 kω iteral pull-up resistor. Whe multiple AD5362 or AD5363 devices are used i oe system, the BUSY pis ca be tied together. This is useful whe it is required that o DAC i ay device be updated util all other DACs are ready. Whe each device has fiished updatig the X2 (A or B) registers, it releases the BUSY pi. If aother device has ot fiished updatig its X2 registers, it holds BUSY low, thus delayig the effect of LDAC goig low. The DAC outputs are updated by takig the LDAC iput low. If LDAC goes low while BUSY is active, the LDAC evet is stored ad the DAC outputs are updated immediately after BUSY goes high. A user ca also hold the LDAC iput permaetly low. I this case, the DAC outputs update immediately after BUSY goes high. Wheever the A/B select registers are writte to, BUSY also goes low, for approximately 600 s. The AD5362/AD5363 have flexible addressig that allows writig of data to a sigle chael, all chaels i a group, or all chaels i the device. This meas that oe, two, four, or eight DAC register values may eed to be calculated ad updated. Because there is oly oe multiplier shared betwee eight chaels, this task must be doe sequetially, so the legth of the BUSY pulse varies accordig to the umber of chaels beig updated. Table 9. BUSY Pulse Widths Actio BUSY Pulse Width 1 Loadig iput, C, or M to 1 chael μs maximum Loadig iput, C, or M to 2 chaels 2.1 μs maximum Loadig iput, C, or M to 8 chaels 5.7 μs maximum 1 BUSY pulse width = ((umber of chaels + 1) 600 s) s. 2 A sigle chael update is typically 1 μs. The AD5362/AD5363 cotai a extra feature whereby a DAC register is ot updated uless its X2A or X2B register has bee writte to sice the last time LDAC was brought low. Normally, whe LDAC is brought low, the DAC registers are filled with the cotets of the X2A or X2B registers, depedig o the settig of the A/B select registers. However, the AD5362/ AD5363 update the DAC register oly if the X2A or X2B data has chaged, thereby removig uecessary digital crosstalk. BIN/2SCOMP PIN The BIN/2SCOMP pi determies if the output data is preseted as offset biary or twos complemet. If this pi is low, the data is straight biary. If it is high, the data is twos complemet. This affects oly the X, C, ad offset DAC registers; the M register ad the cotrol ad commad data are iterpreted as straight biary. TEMPERATURE SENSOR The o-chip temperature sesor provides a voltage output at the TEMP_OUT pi that is liearly proportioal to the Cetigrade temperature scale. The typical accuracy of the temperature sesor is +1 C at +25 C ad ±5 C over the 40 C to +85 C rage. Its omial output voltage is 1.46 V at 25 C, varyig at 4.4 mv/ C. Its low output impedace, low selfheatig, ad liear output simplify iterfacig to temperature cotrol circuitry ad aalog-to-digital coverters. Rev. A Page 20 of 28

21 MONITOR FUTION The AD5362/AD5363 cotai a chael moitor fuctio that cosists of a aalog multiplexer addressed via the serial iterface, allowig ay chael output to be routed to the MON_OUT pi for moitorig usig a exteral ADC. I additio, two moitor iputs, MON_IN0 ad MON_IN1, are provided, which ca also be routed to MON_OUT. The moitor fuctio is cotrolled by the moitor register, which allows the moitor output to be eabled or disabled, ad selects a DAC chael or oe of the moitor pis. Whe disabled, the moitor output is high impedace so that several moitor outputs ca be coected i parallel with oly oe eabled at a time. Table 10 shows the moitor register settigs. Table 10. Moitor Register Fuctios F5 F4 F3 F2 F1 F0 Fuctio 0 X X X X X MON_OUT disabled 1 X X X X X MON_OUT eabled MON_OUT = VOUT MON_OUT = VOUT MON_OUT = VOUT MON_OUT = VOUT MON_OUT = VOUT MON_OUT = VOUT MON_OUT = VOUT MON_OUT = VOUT MON_OUT = MON_IN MON_OUT = MON_IN1 The multiplexer is implemeted as a series of aalog switches. Because this could coceivably cause a large amout of curret to flow from the iput of the multiplexer (VOUTx or MON_INx) to the output of the multiplexer (MON_OUT), care should be take to esure that whatever is coected to the MON_OUT pi is of high eough impedace to prevet the cotiuous curret limit specificatio from beig exceeded. Because the MON_OUT pi is ot buffered, the amout of curret draw from this pi creates a voltage drop across the switches, which i tur leads to a error i the voltage beig moitored. Where accuracy is importat, it is recommeded that the MON_OUT pi be buffered. Figure 20 shows the typical error due to MON_OUT curret. GPIO PIN The AD5362/AD5363 have a geeral-purpose I/O pi, GPIO. This pi ca be cofigured as a iput or a output ad read back or programmed (whe cofigured as a output) via the serial iterface. Typical applicatios for this pi iclude moitorig the status of a logic sigal, a limit switch, or cotrollig a exteral multiplexer. The GPIO pi is cofigured by writig to the GPIO register, which has the special fuctio code of (see Table 15 ad Table 16). Whe Bit F1 is set, the GPIO pi becomes a output ad Bit F0 determies whether the pi is high or low. The GPIO pi ca be set as a iput by writig 0 to both Bit F1 ad Bit F0. The status of the GPIO pi ca be determied by iitiatig a read operatio usig the appropriate bits i Table 17. The status of the pi is idicated by the LSB of the register read. POWER-DOWN MODE The AD5362/AD5363 ca be powered dow by settig Bit 0 i the cotrol register to 1. This turs off the DACs, thus reducig the curret cosumptio. The DAC outputs are coected to their respective SIGGNDx potetials. The power-dow mode does ot chage the cotets of the registers, ad the DACs retur to their previous voltage whe the power-dow bit is cleared to 0. THERMAL SHUTDOWN FUTION The AD5362/AD5363 ca be programmed to shut dow the DACs if the temperature o the die exceeds 130 C. Settig Bit 1 i the cotrol register to 1 eables this fuctio (see Table 16). If the die temperature exceeds 130 C, the AD5362/AD5363 eter a thermal shutdow mode, which is equivalet to settig the power-dow bit i the cotrol register. To idicate that the AD5362/AD5363 have etered thermal shutdow mode, Bit 4 of the cotrol register is set to 1. The AD5362/AD5363 remai i thermal shutdow mode, eve if the die temperature falls, util Bit 1 i the cotrol register is cleared to 0. TOGGLE MODE The AD5362/AD5363 have two X2 registers per chael, X2A ad X2B, which ca be used to switch the DAC output betwee two levels with ease. This approach greatly reduces the overhead required by a microprocessor, which would otherwise eed to write to each chael idividually. Whe the user writes to the X1A, X1B, M, or C register, the calculatio egie takes a certai amout of time to calculate the appropriate X2A or X2B value. If a applicatio, such as a data geerator, requires that the DAC output switch betwee two levels oly, ay method that reduces the amout of calculatio time ecessary is advatageous. For the data geerator example, the user eeds oly to set the high ad low levels for each chael oce by writig to the X1A ad X1B registers. The values of X2A ad X2B are calculated ad stored i their respective registers. The calculatio delay, therefore, happes oly durig the setup phase, that is, whe programmig the iitial values. To toggle a DAC output betwee the two levels, it is oly required to write to the relevat A/B select register to set the MUX2 register bit. Furthermore, because there are four MUX2 cotrol bits per register, it is possible to update eight chaels with just two writes. Table 18 shows the bits that correspod to each DAC output. Rev. A Page 21 of 28

22 SERIAL INTERFACE The AD5362/AD5363 cotai a high speed SPI operatig at clock frequecies up to 50 MHz (20 MHz for read operatios). To miimize both the power cosumptio of the device ad o-chip digital oise, the iterface powers up fully oly whe the device is beig writte to, that is, o the fallig edge of SY. The serial iterface is 2.5 V LVTTL-compatible whe operatig from a 2.5 V to 3.6 V DVCC supply. It is cotrolled by four pis: SY (frame sychroizatio iput), SDI (serial data iput pi), SCLK (clocks data i ad out of the device), ad SDO (serial data output pi for data readback). SPI WRITE MODE The AD5362/AD5363 allow writig of data via the serial iterface to every register directly accessible to the serial iterface, that is, all registers except the X2A, X2B, ad DAC registers. The X2A ad X2B registers are updated whe writig to the X1A, X1B, M, ad C registers, ad the DAC data registers are updated by LDAC. The serial word (see Table 11 or Table 12) is 24 bits log: 16 (AD5362) or 14 (AD5363) of these bits are data bits; six bits are address bits; ad two bits are mode bits that determie what is doe with the data. Two bits are reserved o the AD5363. The serial iterface works with both a cotiuous ad a burst (gated) serial clock. Serial data applied to SDI is clocked ito the AD5362/AD5363 by clock pulses applied to SCLK. The first fallig edge of SY starts the write cycle. At least 24 fallig clock edges must be applied to SCLK to clock i 24 bits of data before SY is take high agai. If SY is take high before the 24th fallig clock edge, the write operatio is aborted. If a cotiuous clock is used, SY must be take high before the 25th fallig clock edge. This ihibits the clock withi the AD5362/ AD5363. If more tha 24 fallig clock edges are applied before SY is take high agai, the iput data becomes corrupted. If a exterally gated clock of exactly 24 pulses is used, SY ca be take high ay time after the 24th fallig clock edge. The iput register addressed is updated o the risig edge of SY. For aother serial trasfer to take place, SY must be take low agai. SPI READBACK MODE The AD5362/AD5363 allow data readback via the serial iterface from every register directly accessible to the serial iterface, that is, all registers except the X2A, X2B, ad DAC data registers. To read back a register, it is first ecessary to tell the AD5362/AD5363 which register is to be read. This is achieved by writig a word whose first two bits are the Special Fuctio Code 00 to the device. The remaiig bits the determie which register is to be read back. If a readback commad is writte to a special fuctio register, data from the selected register is clocked out of the SDO pi durig the ext SPI operatio. The SDO pi is ormally threestated but becomes drive as soo as a read commad is issued. The pi remais drive util the register data is clocked out. See Figure 5 for the read timig diagram. Note that due to the timig requiremets of t22 (25 s), the maximum speed of the SPI iterface durig a read operatio should ot exceed 20 MHz. REGISTER UPDATE RATES The value of the X2A register or the X2B register is calculated each time the user writes ew data to the correspodig X1, C, or M register. The calculatio is performed by a three-stage process. The first two stages take approximately 600 s each, ad the third stage takes approximately 300 s. Whe the write to a X1, C, or M register is complete, the calculatio process begis. If the write operatio ivolves the update of a sigle DAC chael, the user is free to write to aother register, provided that the write operatio does ot fiish util the first-stage calculatio is complete, that is, 600 s after the completio of the first write operatio. If a group of chaels is beig updated by a sigle write operatio, the first-stage calculatio is repeated for each chael, takig 600 s per chael. I this case, the user should ot complete the ext write operatio util this time has elapsed. Table 11. AD5362 Serial Word Bit Assigmet I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 M1 M0 A5 A4 A3 A2 A1 A0 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Table 12. AD5363 Serial Word Bit Assigmet I23 I22 I21 I20 I19 I18 I17 I16 I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 1 I0 1 M1 M0 A5 A4 A3 A2 A1 A0 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D Bit I1 ad Bit I0 are reserved for future use ad should be 0 whe writig the serial word. These bits read back as 0. Rev. A Page 22 of 28