FEATURES 4:1 single-ended multiplexer Q nominal output impedance: 7Ω (V DDO

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1 ICS8304I GENERAL ESCRIPTION The ICS8304I is a low skew, 4:1, Sigle-eded ICS Multiplexer ad a member of the HiPerClockS HiPerClockS family of High Performace Clock Solutios from IT The ICS8304I has four selectable sigleeded clock iputs ad oe sigle-eded clock output The output has a pi which may be set at 33,, or 18, makig the device ideal for use i voltage traslatio applicatios A output eable pi places the output i a high impedace state which may be useful for testig or debug purposes The device operates up to 0MHz ad is packaged i a 16 TSSOP package FEATURES 4:1 sigle-eded multiplexer Q omial output impedace: 7Ω ( = 33) output frequecy: 0MHz Propagatio delay: 3s (maximum), = = 33 Iput skew: (maximum), = = 33 Part-to-part skew: 780 (maximum), = = 33 Additive phase jitter, RMS: 019 (typical), 33/33 Operatig supply modes: / 33/33 33/ 33/18 / /18-40 C to 8 C ambiet operatig temperature Available i both stadard (RoHS ) ad lead-free (RoHS 6) packages BLOCK IAGRAM PIN ASSIGNMENT CLK0 CLK1 CLK CLK3 SEL1 SEL0 OE Q Q c OE CLK3 GN c SEL1 CLK c CLK0 c c CLK1 SEL0 ICS8304I 16-Lead TSSOP 44mm x 0mm x 09mm package body G Package Top iew IT / ICS 1 ICS8304AGI RE C MARCH 7, 008

2 TABLE 1 PIN ESCRIPTIONS Number Name Type escriptio Sigle-eded clock output LCMOS/LTTL iterface levels Output eable Whe LOW, outputs are i HIGH impedace Whe HIGH, outputs are active LCMOS / LTTL iterface 1 Q O utput 3 OE Iput Pullup state levels 4, 8, CLK3, CLK, 10, 14 CLK1, CLK0 Iput P ulldow Sigle-eded clock iputs LCMOS/LTTL iterface levels GN P ower Power supply groud 7, 9 SEL1, SEL0 Iput Pulldow Clock select iput See Cotrol Iput Fuctio Table LCMOS / LTTL iterface levels, 6, 11, 13, 1 c U used No coect 1 P ower Power ad iput supply pi 16 P ower Output supply pi NOTE: Pullup ad P ulldow refer to iteral iput resistors See Table, Pi Characteristics, for typical values TABLE PIN CHARACTERISTICS C IN R R PULLUP PULLOWN C P R OUT put Capacitace put Pullup Resistor put Pulldow Resistor O p I 4 F I 1 kω I 1 kω = pf Power issipatio Capacitace (per output) = 6 0 pf = pf = Ω Output Impedace = 6 7 Ω = Ω TABLE 3 CONTROL INPUT FUNCTION TABLE Cotrol Iputs SEL1 SEL0 Iput Selected to Q 0 0 CLK0 0 1 CLK1 1 0 CLK 1 1 CLK3 IT / ICS ICS8304AGI RE C MARCH 7, 008

3 ABSOLUTE MAXIMUM RATINGS Supply oltage, 46 Iputs, I -0 to + 0 Outputs, O -0 to + 0 Package Thermal Impedace, θ JA 89 C/W (0 lfpm) Storage Temperature, T STG -6 C to 10 C NOTE: Stresses beyod those listed uder Absolute Ratigs may cause permaet damage to the device These ratigs are stress specificatios oly Fuctioal operatio of product at these coditios or ay coditios beyod those listed i the C Characteristics or AC Characteristics is ot implied Exposure to absolute maximum ratig coditios for exteded periods may affect product reliability TABLE 4A POWER SUPPLY C CHARACTERISTICS, = = 33±%, TA = -40 C TO 8 C I I ower Supply oltage utput Supply oltage ower Supply Curret utput Supply Curret P O P 40 ma O ma TABLE 4B POWER SUPPLY C CHARACTERISTICS, = 33±%, = ±%, TA = -40 C TO 8 C I I ower Supply oltage utput Supply oltage ower Supply Curret utput Supply Curret P O P 40 ma O ma TABLE 4C POWER SUPPLY C CHARACTERISTICS, = 33±%, = 18±0, TA = -40 C TO 8 C I I ower Supply oltage utput Supply oltage ower Supply Curret utput Supply Curret P O P 40 ma O ma TABLE 4 POWER SUPPLY C CHARACTERISTICS, = = ±%, TA = -40 C TO 8 C I I ower Supply oltage utput Supply oltage ower Supply Curret utput Supply Curret P O P 3 ma O ma TABLE 4E POWER SUPPLY C CHARACTERISTICS, = ±%, = 18±0, TA = -40 C TO 8 C I I ower Supply oltage utput Supply oltage ower Supply Curret utput Supply Curret P O P 3 ma O ma IT / ICS 3 ICS8304AGI RE C MARCH 7, 008

4 TABLE 4F LCMOS/LTTL C CHARACTERISTICS, TA = -40 C TO 8 C IH IL I IH I IL OH OL Iput High oltage Iput Low oltage Iput High Curret Iput Low Curret Output Higholtage Output Low oltage CLK0:CLK3, SEL0, SEL1 OE CLK0:CLK3, SEL0, SEL1 OE NOTE 1: Outputs termiated with 0Ω to 33 ± % ± % 33 ± % ± = + = = = % 33 or ± % = 10 µ A 33 or ± % = µ A 33 or ± % = - µ A = 33 or ± % -10 µ A = 33 ± %; NOTE 1 6 = ± %; NOTE = 18 ± %; NOTE = 33 ± %; NOTE 1 0 = ± %; NOTE 1 04 = 18 ± %; NOTE 1 03 / See Measuremet sectio, "Load Circuit" diagrams O TABLE A AC CHARACTERISTICS, = = 33 ± %, TA = -40 C TO 8 C utput Frequecy ropagatio elay, Low to High; NOTE ropagatio elay, High to Low; NOTE put Skew; NOTE Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Sectio; NOTE 3 art-to-part Skew; NOTE, utput Rise/Fall Tim utput uty Cycle MUX Isolatio Measured from / of the iput to / of O This parameter is defied i accordace with rivig oly oe iput clock efied as skew betwee outputs o differet load coditios Usig the same type of iput MH p fmax O 0 z tplh s tphl 7 9 s t sk(i) I s tjit 1MHz, (1kHz to 0MHz) 019 t sk(pp) P t R / tf O e 0% to 80% 0 00 odc O 4 % 100MHz 4 db NOTE 1: the output NOTE : JEEC Stadard 6 NOTE 3: NOTE 4: devices operatig a the same supply voltages ad with equal o each device, the output is measured at / O IT / ICS 4 ICS8304AGI RE C MARCH 7, 008

5 TABLE B AC CHARACTERISTICS, = 33 ± %, = ± %, TA = -40 C TO 8 C utput Frequecy ropagatio elay, Low to High; NOTE ropagatio elay, High to Low; NOTE put Skew; NOTE Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Sectio; NOTE 3 art-to-part Skew; NOTE, utput Rise/Fall Tim utput uty Cycle MUX Isolatio Measured from / of the iput to / of O This parameter is defied i accordace with rivig oly oe iput clock efied as skew betwee outputs o differet load coditios Usig the same type of iput MH p fmax O 0 z tplh s tphl s t sk(i) I s tjit 1MHz, (1kHz to 0MHz) 014 t sk(pp) P t R / tf O e 0% to 80% 0 00 odc O 4 % 100MHz 4 db NOTE 1: the output NOTE : JEEC Stadard 6 NOTE 3: NOTE 4: devices operatig a the same supply voltages ad with equal o each device, the output is measured at / O TABLE C AC CHARACTERISTICS, = 33 ± %, = 18 ± %, TA = -40 C TO 8 C utput Frequecy ropagatio elay, Low to High; NOTE ropagatio elay, High to Low; NOTE put Skew; NOTE Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Sectio; NOTE 3 art-to-part Skew; NOTE, utput Rise/Fall Tim utput uty Cycle MUX Isolatio Measured from / of the iput to / of O This parameter is defied i accordace with rivig oly oe iput clock efied as skew betwee outputs o differet load coditios Usig the same type of iput MH p fmax O 0 z tplh s tphl s t sk(i) I s tjit 1MHz, (1kHz to 0MHz) 016 t sk(pp) P t R / tf O e 0% to 80% odc O 4 % 100MHz 4 db NOTE 1: the output NOTE : JEEC Stadard 6 NOTE 3: NOTE 4: devices operatig a the same supply voltages ad with equal o each device, the output is measured at / O IT / ICS ICS8304AGI RE C MARCH 7, 008

6 TABLE AC CHARACTERISTICS, = = ± %, TA = -40 C TO 8 C utput Frequecy ropagatio elay, Low to High; NOTE ropagatio elay, High to Low; NOTE put Skew; NOTE Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Sectio; NOTE 3 art-to-part Skew; NOTE, utput Rise/Fall Tim utput uty Cycle MUX Isolatio Measured from / of the iput to / of O This parameter is defied i accordace with rivig oly oe iput clock efied as skew betwee outputs o differet load coditios Usig the same type of iput 7 MH p fmax O 0 z tplh s tphl s t sk(i) I 60 1 s tjit 1MHz, (1kHz to 0MHz) 01 t sk(pp) P t R / tf O e 0% to 80% odc O % 100MHz 4 db NOTE 1: the output NOTE : JEEC Stadard 6 NOTE 3: NOTE 4: devices operatig a the same supply voltages ad with equal o each device, the output is measured at / O TABLE E AC CHARACTERISTICS, = ± %, = 18 ± -%, TA = -40 C TO 8 C utput Frequecy ropagatio elay, Low to High; NOTE ropagatio elay, High to Low; NOTE put Skew; NOTE Buffer Additive Phase Jitter, RMS; refer to Additive Phase Jitter Sectio; NOTE 3 art-to-part Skew; NOTE, utput Rise/Fall Tim utput uty Cycle MUX Isolatio Measured from / of the iput to / of O This parameter is defied i accordace with rivig oly oe iput clock efied as skew betwee outputs o differet load coditios Usig the same type of iput MH p fmax O 0 z tplh s tphl s t sk(i) I s tjit 1MHz, (1kHz to 0MHz) 017 t sk(pp) P t R / tf O e 0% to 80% odc O % 100MHz 4 db NOTE 1: the output NOTE : JEEC Stadard 6 NOTE 3: NOTE 4: devices operatig a the same supply voltages ad with equal o each device, the output is measured at / O IT / ICS 6 ICS8304AGI RE C MARCH 7, 008

7 AITIE PHASE JITTER The spectral purity i a bad at a specific offset from the fudametal compared to the power of the fudametal is called the dbc Phase Noise This value is ormally expressed usig a Phase oise plot ad is most ofte the specified plot i may applicatios Phase oise is defied as the ratio of the oise power preset i a 1Hz bad at a specified offset from the fudametal frequecy to the power value of the fudametal This ratio is expressed i decibels (dbm) or a ratio of the power i the 1Hz bad to the power i the fudametal Whe the required offset is specified, the phase oise is called a dbc value, which simply meas dbm at a specified offset from the fudametal By ivestigatig jitter i the frequecy domai, we get a better uderstadig of its effects o the desired applicatio over the etire time record of the sigal It is mathematically possible to calculate a expected bit error rate give a phase oise plot Additive Phase 1MHz (1kHz to 0MHz) = 019 typical SSB PHASE NOISE dbc/hz OFFSET FROM CARRIER FREQUENCY (HZ) As with most timig specificatios, phase oise measuremets has issues relatig to the limitatios of the equipmet Ofte the oise floor of the equipmet is higher tha the oise floor of the device This is illustrated above The device meets the oise floor of what is show, but ca actually be lower The phase oise is depedet o the iput source ad measuremet equipmet IT / ICS 7 ICS8304AGI RE C MARCH 7, 008

8 PARAMETER MEASUREMENT INFORMATION 16±% 1±% SCOPE,, LCMOS Qx LCMOS Qx SCOPE GN GN -16±% -1±% 33 CORE/33 OUTPUT LOA AC TEST CIRCUIT CORE/ OUTPUT LOA AC TEST CIRCUIT 0±% 1±% 4±% 09±% SCOPE SCOPE Qx Qx LCMOS GN LCMOS GN -1±% -09±% 33 CORE/ OUTPUT LOA AC TEST CIRCUIT 33 CORE/18 OUTPUT LOA AC TEST CIRCUIT 16±% 09±% SCOPE Part 1 Qx LCMOS GN Qx Part Qy tsk(pp) -09±% CORE/18 OUTPUT LOA AC TEST CIRCUIT PART-TO-PART SKEW IT / ICS 8 ICS8304AGI RE C MARCH 7, 008

9 CLK0:CLK3 80% 80% Q Q 0% t R t F 0% tp LH tp HL PROPAGATION ELAY OUTPUT RISE/FALL TIME CLKx Q Q t PW t P1 t PERIO odc = t PW t PERIO x 100% CLKy Q t P tsk(i) = t P t P1 INPUT SKEW OUTPUT UTY CYCLE/PULSE WITH/PERIO IT / ICS 9 ICS8304AGI RE C MARCH 7, 008

10 APPLICATION INFORMATION RECOMMENATIONS FOR UNUSE INPUT PINS INPUTS: CLK INPUTS For applicatios ot requirig the use of a clock iput, it ca be left floatig Though ot required, but for additioal protectio, a 1kΩ resistor ca be tied from the CLK iput to groud LCMOS CONTROL PINS All cotrol pis have iteral pull-u or pull-dows; additioal resistace is ot required but ca be added for additioal protectio A 1kΩ resistor ca be used IT / ICS 10 ICS8304AGI RE C MARCH 7, 008

11 RELIABILITY INFORMATION TABLE 6 θ JA S AIR FLOW TABLE FOR 16 LEA TSSOP θ JA by elocity (Liear Feet per Miute) Sigle-Layer PCB, JEEC Stadard Boards 1371 C/W 118 C/W 1068 C/W Multi-Layer PCB, JEEC Stadard Boards 890 C/W 818 C/W 781 C/W NOTE: Most moder PCB desigs use multi-layered boards The data i the secod row pertais to most desigs TRANSISTOR COUNT The trasistor cout for ICS8304I is: 874 PACKAGE OUTLINE AN PACKAGE IMENSIONS PACKAGE OUTLINE - G SUFFIX FOR 16 LEA TSSOP TABLE 7 PACKAGE IMENSIONS SYMBOL Millimeters N 16 A A A b c E 640 BASIC E e 06 BASIC L α 0 8 aaa Referece ocumet: JEEC Publicatio 9, MO-13 IT / ICS 11 ICS8304AGI RE C MARCH 7, 008

12 TABLE 8 ORERING INFORMATION Part/Order Number ICS8304AGI ICS8304AGIT ICS8304AGILF ICS8304AGILFT NOTE: Parts that are Markig Package Shippig Packagig Temperature 8304AGI 16 Lead TSSOP tube -40 C to 8 C 8304AGI 16 Lead TSSOP 00 tape & reel -40 C to 8 C 8304AIL 16 Lead "Lead-Free" TSSOP tube -40 C to 8 C 8304AIL 16 Lead "Lead-Free" TSSOP 00 tape & reel -40 C to 8 C ordered with a "LF" suffix to the part umber are the Pb-Free cofiguratio ad are RoHS compliat While the iformatio preseted herei has bee checked for both accuracy ad reliability, Itegrated evice Techology, Icorporated (IT) assumes o resposibility for either its use or for ifrigemet of ay patets or other rights of third parties, which would result from its use No other circuits, patets, or liceses are implied This product is iteded for use i ormal commercial ad idustrial applicatios Ay other applicatios such as those requirig high reliability or other extraordiary evirometal requiremets are ot recommeded without additioal processig by IT IT reserves the right to chage ay circuitry or specificatios without otice IT does ot authorize or warrat ay IT product for use i life support devices or critical medical istrumets IT / ICS 1 ICS8304AGI RE C MARCH 7, 008

13 Rev Table Page A T8 B C REISION HISTORY SHEET escriptio of Chage 1 rderig Iformatio Table - corrected Part/Order Numbers 1 Features Sectio - added Additive Phase Jitter bullet - 6 AC Characteristics Tables - added tjit row ad spec ate 1/3/0 O 6 TA - TE 4 01/04/07 7 Added Additive Phase Jitter sectio TA - TE 4-6 AC Characteristics Tables - chaged part-to-part skew specs 03/07/08 IT / ICS 13 ICS8304AGI RE C MARCH 7, 008

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