HVIC Technologies for IPM

Transcription

1 HVIC Techologies for IPM JONISHI, Akihiro AKAHANE, Masashi YAMAJI, Masaharu ABSTRACT A high voltage itegrated (HVIC), which is a gate driver IC with a high breakdow voltage, is oe of the key devices required i ehacig the fuctioality of itelliget power modules (IPMs). Fuji Electric has developed HVIC techology characterized by its advaced fuctioality, compactess, high reliability, ad guarateed idustrial use at 6 V/ 1,2 V for small- ad medium-capacity IPM. By reducig the area ad adoptig high breakdow voltage techology ad ehaced oise resistat level-shift techology, we have reduced the chip size by 2% while improvig the breakdow voltage ad reliability. I additio, we have achieved over-curret ad overheat protectio techology for upper-arm IGBT, as well as level-dow fuctioality for alarm s. 1. Itroductio A itelliget power module (IPM) is a power semicoductor module that itegrates ito oe package a driver IC with the gate drive ad protective fuctios together with isulated-gate bipolar trasistors (IGBTs) or other power switchig devices ad free wheelig diodes (FWDs). IPMs help reduce the umber of parts ad size ad simplify the desig of systems ad are used i wide-ragig applicatios icludig idustrial machies, cosumer electroics such as air coditioers ad power supply equipmet for servers. Fuji Electric developed the world s first IPM usig bipolar trasistors i Ever sice the, we have bee actively developig products that help to improve the reliability ad reduce the size of systems. Oe such product was the world s first IPM equipped with a IGBT chip overheat protectio fuctio that we released i 1997 (1). I 212, we commercialized a small-capacity IPM for iverter air coditioers. It elimiates the eed for a exteral isulatio or level-shift by employig a high-voltage itegrated (HVIC), which is a high breakdow voltage gate driver IC. Furthermore, we are workig o ways to icorporate HVICs i medium-capacity IPMs for idustrial use. HVICs to be mouted o IPMs are required to withstad 6 V ad 1,2 V accordig to the breakdow voltage class of the IPM. I additio, they must also offer high reliability to withstad the oise caused by IGBT switchig, itegrate various protectio s ad have a small chip size. Based o the 8-V breakdow voltage guarateed HVIC techology (2) developed i 21, Fuji Electric has developed ew idustrial 6-V/1,2-V breakdow voltage guarateed HVIC techology. It features high fuctioality, compactess ad high reliability ad is iteded for small- ad medium-capacity IPMs of up to the 1,2-V/1-A class. Of the ew techology, this paper describes the device-process techology ad compoet techology. 2. Features of HVIC for IPMs Figure 1 shows the 1,2-V breakdow voltage guarateed HVIC chip prototyped for medium-capacity IPMs ad Fig. 2 a block diagram of its ad peripheral. Oe feature of the HVIC is that it itegrates 3 s ito oe chip: a low-side operated based o the groud potetial, high-side operated based o the source potetial of the upper-arm IGBT to provide the gate drive fuctio, ad level-shift resposible for the level-up fuctio for cotrol s. The source potetial of the upperarm IGBT may vary from about 1 to over +1, V alog with switchig ad a high isolatio breakdow voltage is provided betwee the high-side ad low-side High-side HVJT Low-side High breakdow voltage -type High breakdow voltage p-type issue: Power Semicoductors Cotributig i Eergy Maagemet Electroic Devices Busiess Group, Fuji Electric Co., Ltd. Fig.1 1,2-V breakdow voltage guarateed HVIC chip 247

2 VCC Microcomputer IN AE HVIC Low-side Iput/ cotrol Alarm output Level-shift Level-up Leveldow High-side VS+15 V Gate drive VS+5 V Overheat/overcurret detectio protectio VB HO OC OH VS 4 V DC Upper-arm IGBT Lower-arm IGBT product) (b) Provisio of overheat/ overcurret detectio protective fuctio for upper-arm IGBT (c) Provisio of level-dow fuctio for alarm s (d) Reductio of area ad adoptio of high breakdow voltage techology (i-chip wire bodig high potetial wirig techology with the previous product) (e) Ehaced oise immuity (dv/dt oise immuity ±5 kv/ μs mi.) VCC/: Low-side power supply termials VB/VS: High-side power supply termials IN: Gate cotrol iput termial HO: Gate drive output termial OC/OH: Overheat/overcurret detectio termials AE: Alarm output termial Fig.2 Block diagram of 1,2-V breakdow voltage guarateed HVIC ad peripheral s. With the HVIC, the cotrol based o the groud potetial iput to the low-side is trasmitted through the level-shift to the gate drive i the high-side, which drives the upperarm IGBT. With a IPM icorporatig the HVIC, this level-shift fuctio makes it possible to drive the upper-arm IGBT without usig a optocoupler or other isulatio device. Features of the 1,2-V breakdow voltage guarateed HVIC iclude: (a) Guarateed breakdow voltage of 1,2 V, power supply voltage of up to 24 V (guarateed breakdow voltage 8 V with the previous 3. Device-Process Techology To achieve a compact ad high-reliability HVIC with advaced-fuctioality, we have developed 6-V/1,2-V high breakdow voltage CMOS process that itroduces a ew well structure ad high breakdow voltage techology. For device isolatio, the selfisolatio method has bee employed. 3.1 Reductio of area by usig divided high-side well structure Figure 3 shows the cross-sectioal structure of the HVIC. The HVIC is provided with a low-side well for formig the low-side ad high-side well for formig the high-side. Both are composed of a -type diffusio layer o the. The high-side well is separated from the low-side well by the high-voltage juctio termiatio (HVJT) ad the HVJT fuctios to maitai the high breakdow voltage betwee the high-side ad low-side s. (1) Issue with covetioal high-side well structure 15-V powered 15-V powered 5-V powered VS VB VS VB VL VS MV: well for 15-V powered LV: well for 5-V powered - - p p p MV MV LV HVJT High-side well HVJT Low-side well (a) Covetioal structure 15-V powered 5-V powered 15-V powered 5-V powered Field plate VS VB VL VS VS VB VL VS MV - p - - LV - MV p-isolatio - p p p LV MV LV p-isolatio HVJT High-side well HVJT Low-side well (b) Divided high-side well structure Fig.3 Cross-sectioal structure of HVIC 248 FUJI ELECTRIC REVIEW vol.61 o.4 215

3 As show i Fig. 3(a), the low-side well is composed of multiple diffusio layers correspodig to the power supply voltages of the idividual s. However, the high-side well is composed of a sigle diffusio layer i the covetioal HVIC. This is because it was difficult to divide the high-side well while maitaiig the high breakdow voltage with the covetioal techology. For that reaso, the high-side could oly support oe power supply voltage, which reduced the degree of freedom of desig. (2) Divided high-side well structure For the purpose of solvig the issue described above, we have developed the divided high-side well structure. Figure 3(b) shows the cross-sectioal structure of the HVIC that uses the divided high-side well structure. The high-side well is composed of 2 diffusio layers correspodig to 2 power supply voltages. A structure called p-isolatio, which cosists of lowcocetratio -type ad p-type diffusio layers, is used to separate the 2 diffusio layers from each other while the high breakdow voltage of the high-side well is maitaied. This allows multiple power supply voltage s to be used for cofigurig a for the high-side i the same way as the low-side. This improvemet of the degree of desig freedom has made it possible to realize a high-side such as the protective with a area reduced by approximately 2% from the previous product. 3.2 High breakdow voltage techology usig area-savig self-shieldig method The level-shift has the role of trasmittig s from the low-side to the high-side. Ad, whe the high-side is activated based o 4 V, for example, the level-shift must covert s based o the groud potetial to those based o 4 V. This level-up fuctio is realized by usig high breakdow voltage -type laterally diffused metal-oxide-semicoductor field-effect trasistors (s). Figure 4 shows the -type s of the 6-V breakdow voltage guarateed HVIC chip. (1) Covetioal high breakdow voltage -type LD- High-side (a) Covetioal method HVJT Chip size 2% reduced High breakdow voltage -type Low-side High breakdow voltage -type High-side Low-side (b) Self-shieldig method Fig.4 -type s of 6-V breakdow voltage guarateed HVIC chip MOSFET Figure 4(a) shows the 6 V guarateed HVIC chip with covetioal high breakdow voltage -type s that use wire bodig. With the covetioal HVIC, the high breakdow voltage -type s occupied a large portio of the area i the chip. (2) High breakdow voltage -type of self-shieldig type I order to reduce the chip size, we have employed the self-shieldig method that makes a high breakdow voltage possible with a reduced area. We have developed 6-V ad 1,2-V guarateed HVICs icorporatig high breakdow voltage -type s. Figure 4(b) shows the 6-V guarateed HVIC chip with the high breakdow voltage -type s usig the self-shieldig method. The self-shieldig method itegrates the high breakdow voltage -type ad HVJT. It allows the device footprit to be reduced from the covetioal method that requires idepedet high breakdow voltage -type s. This techology has meat we could successfully reduce the chip size by 2% from the previous product (3). 3.3 Level-dow high breakdow voltage device techology (1) Level-dow fuctio The prototyped 1,2-V breakdow voltage guarateed HVIC is equipped with the level-dow fuctio for alarm s. This allows alarm s for otificatio of errors of the upper-arm IGBT chip, such as overheat ad overcurret, to be trasmitted to the exteral microcomputer without requirig ay exteral isulatio device or level-shift. A alarm output from the abormal detectio i the high-side is coverted ito a based o the groud potetial by the leveldow fuctio of the level-shift to be trasmitted to the microcomputer through the low-side. While the level-up fuctio of the level-shift is realized by usig the high breakdow voltage -type, the level-dow fuctio uses the high breakdow voltage p-type. (2) Device structure Figure 5 shows the device structure of the 1,2- V breakdow voltage guarateed p-type that has bee developed. As with the high breakdow voltage -type, the structure itegrates the HVJT by usig the self-shieldig method. I order to guaratee the 1,2-V breakdow voltage, a high breakdow voltage structure called the double RESURF structure ad resistive field plate (RFP) structure have bee employed. The double RESURF structure cosists of a 3-layer structure icludig the, -type diffusio layer ad p-type diffusio layer o the surface. The -type diffusio layer ad the p-type diffusio layer of the surface become issue: Power Semicoductors Cotributig i Eergy Maagemet HVIC Techologies for IPM 249

4 completely depleted whe a high voltage is applied, which mitigates the electric field. The RFP structure has a polysilico resistor with the electrodes at both eds coected to the high potetial ad groud potetial provided i the high breakdow voltage regio. The uiform potetial gradiet geerated i the polysilico resistor mitigates the electric field i the high breakdow voltage regio. These structures are also used for the HVJT ad high breakdow voltage -type Drai-source curret -IDS (μa) Drai-source curret -IDS (ma) p Drai p - VGS= V RFP - p-type Gate Source 5 1, 1,5 Drai-source voltage -V DS (V) (a) Off-state breakdow voltage waveform Before profile optimizatio (V GS= 5V) p Fig.5 Device structure of 1,2-V breakdow voltage guarateed p-type 5 1, 1,5 Drai-source voltage -V DS (V) (b) Output characteristic waveforms V GS= 15 V 12 V 9V 6V 2, 3V 2, Fig.6 Characteristics of 1,2-V breakdow voltage guarateed p-type High-side well HVJT p-type. (3) Characteristics Figure 6 shows the characteristics of the 1,2-V breakdow voltage guarateed p-type. Figure 6(a) shows a off-state breakdow voltage waveform. Although beig a lateral device, it realizes a actual breakdow voltage of approximately 1,64 V. The leakage curret observed i the regio uder 1,7 V is due to the curret flowig i the RFP structure. By optimizig the resistace value of the RFP structure, a low leakage curret of 5 μa or less at room temperature is achieved while the high breakdow voltage is maitaied. Figure 6(b) shows output characteristic waveforms. At the gate-source voltage of 15 V ad drai-source voltage of 4 V, a drai curret of 5.4 ma is obtaied ad the o-state breakdow voltage of approximately 1,5 V is realized. The dotted lie i Fig. 6(b) shows the characteristic of the device prototyped i the iitial stage of developmet. The curret decrease observed aroud 8 V is due to the substrate leakage pheomeo recetly discovered, which has limited the o-state breakdow voltage to 8 V. Fuji Electric has clarified the detailed mechaism of how this pheomeo is geerated ad used the results as the basis for optimizig the diffusio layer profile. This has led to a reductio i the substrate leakage pheomea to 1,5 V, which has resulted i the realizatio of a high o-state breakdow voltage. 4. Circuit Compoet Techology 4.1 High oise immuity level-shift techology (1) Covetioal level-shift Figure 7 shows the covetioal level-shift for level-up shiftig. It is composed of 2 sets of commo-source amplifier s each usig a levelshift resistor ad a high breakdow voltage -type ad the latch i the high-side. By iputtig a cotrol from the low-side to the commo-source amplifier s, a voltage drop accordig to the cotrol is geerated i Set Lowside IN Reset Level-shift resistor R Latch S High breakdow voltage -type Level-shift Gate HO drive Fig.7 Covetioal level-shift for level-up shiftig VB VS 25 FUJI ELECTRIC REVIEW vol.61 o.4 215

5 Impedace adjustmet VB Overcurret detectio 8 μs V AE (5 V/div) Shutdow Overcurret detectio threshold 26 A Set Reset Latch Fig.8 Impedace coversio type level-shift the level-shift resistors, which switches the output of the latch. This operatio trasmits the s from the low-side to the high-side. (2) Circuit malfuctio caused by dv/dt oise of covetioal The covetioal level-shift had a issue of beig susceptible to malfuctios due to dv/dt oise. The dv/dt oise is geerated by rapid variatios i the referece potetial of the high-side due to switchig of the upper-arm IGBT. This dv/dt oise causes a oise curret to flow i the level-shift resistors, which geerates a voltage drop. Ad the output of the latch ad the output of the subsequet gate drive might be iverted erroeously. (3) Impedace coversio type level-shift Figure 8 shows the impedace coversio type level-shift (4) ewly developed for improvig the dv/dt oise immuity. The MOSFETs for impedace adjustmet are coected i parallel with the levelshift resistors. This structure dyamically optimizes the impedace of the level-shift resistors accordig to the output status of the latch. I this way, the voltage drop i the level-shift resistors due to the dv/ dt oise curret is cotrolled to prevet a malfuctio. 4.2 Overheat/ overcurret protectio techology The HVIC developed is equipped with a overheat/ overcurret protectio i the high-side well for protectig the upper-arm IGBT from overheatig ad overcurret. Overcurret detectio is achieved by moitorig the curret flowig i the curret sesig IGBT itegrated i the IGBT chip. This is doe by usig the shut resistor itegrated i the HVIC. Overheat detectio is achieved by moitorig the juctio voltage R S VS I C: Upper-arm IGBT collector curret V CE: Upper-arm IGBT collector-emitter voltage V AE: Alarm (low-active) Fig.9 Overcurret test waveforms of 1,2-V/1-A class IPM icorporatig HVIC of the temperature sesig diode. Figure 9 shows overcurret test waveforms of the 1,2-V/1-A class IPM that icorporates the HVIC prototyped. Immediately after a overcurret exceedig 26 A flows i the upper-arm IGBT, a alarm idicatig a overcurret is output ad the gate output of the HVIC is shut dow. The time from the geeratio of the overcurret to the shutdow is aroud 8 μs, which idicates that high-speed respose sufficiet for protectig the IGBT is possible. 5. Postscript I C (1 A/div) V CE (25 V/div) V, A This paper has described the ew HVIC techology for IPMs that has bee developed. This techology realizes ehaced fuctioality ad improved reliability of IPMs ad helps to improve the reliability ad reduce the size of power coversio systems. We ited to cotiue developig power IC techologies that help ehace the value of power coversio systems. Refereces (1) Shimizu, N. et al. V-Series Itelliget Power Modules. FUJI ELECTRIC REVIEW. 21, vol.56, o.2, p (2) Yamaji, M. et al. 8 V Class HVIC Techology. FUJI ELECTRIC REVIEW. 211, vol.57, o.3, p (3) Yamaji, M. et al. A 6 V High-Voltage IC Techique With a New Self-Shieldig Structure for High Noise Tolerace ad Die Shrik. IEEE Tras. Electro Devices, 215, vol.62, o.5, p (4) Akahae, M. et al. A ew level up shifter for HVICs with high oise tolerace. Proc. ECCE-ASIA, p issue: Power Semicoductors Cotributig i Eergy Maagemet HVIC Techologies for IPM 251

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