Two-Dimensional Carrier Profiling by Scanning Tunneling Microscopy and Its Application to Advanced Device Development

Transcription

1 Two-Dimesioal Carrier Profilig by Scaig Tuelig Microscopy ad Its Applicatio to Advaced Device Developmet Hideobu Fukutome (Mauscript received December 28, 2009) A high-resolutio two-dimesioal (2D) carrier profilig techique has bee desired to optimize the dopat profile aroud the source/drai ad extesio regio i trasistors to ehace electrical characteristics whe scalig the gate legth dow to less tha 50 m. At Fujitsu Semicoductor Ltd., high spatial resolutio of about 1 m has bee achieved by scaig tuelig microscopy to eable the 2D carrier profilig techique to be applied to the developmet of scaled trasistors beyod the 90-m techology ode. The depedece of the 2D carrier profile o process coditios was foud to agree well with that of electrical characteristics. O the basis of such profiles, the dopat profile i scaled trasistors has bee optimized. The techique also eables a evaluatio of dopat distributio fluctuatios that cause variability i trasistor performace. The dopat profile aroud the extesio regio was foud to deped o the gate lie edge roughess. O the basis of the measured results, various methodologies for suppressig trasistor performace variability have bee proposed. 1. Itroductio The scalig dow of trasistors the basic buildig blocks of large-scale itegrated circuits (LSIs) is beig actively pursued to icrease the performace ad itegratio of LSIs, which have foud widespread use i all sorts of equipmet icludig had-held devices, digital appliaces, ad maiframe computers. As show i Figure 1, a trasistor cosists of a gate electrode plus source ad drai electrodes that are formed by a dopat profile i the silico substrate below the gate. The trasistor fuctios as a switch betwee its o-state ad off-state by adjustig the curret that flows betwee the source ad drai at the gate. To scale dow gate dimesios to less tha 50 m without degradig trasistor performace, we must optimize the dopat profile formed below the gate. For example, if the distace betwee the source ad drai (effective chael legth) is short, the leakage curret i the off-state is high, so the power cosumed by the LSI i stadby mode is high, which is udesirable. There has thus bee a eed for a measuremet techique that ca visualize the Sample Probe Source Gate Sidewall structure Drai : Source/drai extesio regio X ov : Lateral overlap legth Figure 1 Schematics of cross-sectioal carrier profile i scaled trasistor ad its measuremet method. L g X ov L eff FUJITSU Sci. Tech. J., Vol. 46, No. 3, pp (July 2010) 237

2 H. Fukutome: Two-Dimesioal Carrier Profilig by Scaig Tuelig Microscopy ad Its Applicatio to Advaced Device Developmet aoscale dopat profile i the lateral directio (L g directio i Figure 1). I this paper, I describe the results of applyig a two-dimesioal (2D) dopat profilig techique that my coworkers ad I have developed usig scaig tuelig microscopy (STM) 1) to the research ad developmet of scaled trasistors. 2. STM-based 2D dopat profilig techique Dopat profilig techiques ca be divided ito two groups accordig to the object of measuremet. That is, there are techiques that measure the total umber of impurity atoms ad those that measure electrically active dopats. A typical example of the former is secodary io mass spectrometry, which correspods to oe-dimesioal dopat profilig. STM-based dopat measuremet is a example of the latter type. Both types of techiques are importat i achievig efficiet fabricatio of scaled trasistors. At the same time, various types of dopat profilig equipmet based o a microscope ad probe cofiguratio have bee researched ad developed. Each of these reflects the features of this maistay cofiguratio. I geeral-purpose scaig capacitace microscopy, the probe tip has a large diameter, which has made it difficult to achieve the aoscale spatial resolutio eeded for evaluatig scaled trasistors beyod the 90-m ode. I cotrast, STM ca achieve high-resolutio 2D profilig of dopats i the silico substrate, as described below. 2.1 Basic priciple of STM STM is a surface-measuremet techology that uses the tuelig curret flowig betwee the metallic probe ad the surface of a sample. This tuelig curret flows whe the probe is brought sufficietly close to the sample to which a fixed voltage has bee applied. Here, a 2D topographic image, of atomic steps for example, ca be obtaied by scaig the sample surface with the probe while keepig the tuelig curret fixed by cotrollig it through a feedback loop. Sice the tuelig curret chages expoetially with respect to the tip-sample distace, excellet spatial resolutio i the vertical directio ca be achieved. I additio, the use of tuelig pheomea via a atom at the tip of the probe leads to extremely high resolutio i the horizotal directio as well. I short, STM has atomic-scale resolutio that ca visualize idividual surface atoms. The tuelig curret is a physical quatity that reflects the local carrier cocetratio ear the sample surface, ad sice it atteuates expoetially with tip-sample distace, as log as there is o local Fermi-level piig o the surface, the local carrier cocetratio reflected by the dopat cocetratio i the silico substrate ca be measured by STM. Appropriate applicatio of hydroge termiatio to the surface of a silico sample ca elimiate Fermi-level piig o the surface, ad this has made it possible to experimetally cofirm the depedece of the tuelig curret o sample voltage accordig to coductio type ad carrier cocetratio. 2),3) Moreover, measuremets ca be made i a high vacuum to reduce the effects of surface-adsorbed material ad to maitai a hydroge-termiated surface, thereby eablig measuremets to be repeated a sufficiet umber of times at the same locatio. 4) 2.2 Acquisitio of 2D carrier profile images by CITS As described above, a topographic image of a sample s surface ca be obtaied by STM. Sice the sample-voltage (V s ) depedece of the tuelig curret (I t ) reflects the local carrier cocetratio i the silico substrate, curret imagig tuelig spectroscopy (CITS), 5) which ca provide both a topographic image of the sample surface ad the 2D distributio of the local I t -V s characteristic simultaeously, ca be used i cojuctio with a measuremet locatio idetificatio techique to obtai 2D carrier 238 FUJITSU Sci. Tech. J., Vol. 46, No. 3 (July 2010)

3 H. Fukutome: Two-Dimesioal Carrier Profilig by Scaig Tuelig Microscopy ad Its Applicatio to Advaced Device Developmet profile images. A tuelig curret image of a aoscale p juctio as a specific example of how a 2D carrier profile ca be obtaied by CITS is show i Figure 2. As show o the left, the probe is scaed above the p juctio while the tip-sample distace is kept roughly costat. This eables the p-type ad -type regios, which exist as alterate strips with widths of about 100 m, to be visualized because the tuelig curret flowig betwee the tip ad sample fluctuates as coductio type ad carrier cocetratio chage. I this way, a 2D carrier profile ca be measured by CITS as a tuelig curret profile. 2.3 Resolutio of STM-based 2D carrier profilig Here, I describe the resolutio of STMbased 2D carrier profilig. Although STM itself has atomic resolutio, there are other factors that determie the spatial resolutio i carrier cocetratio measuremet. I particular, eergy bad bedig, which occurs as the probe approaches the sample surface, ca be cosidered to be a primary factor, which sets a fudametal resolutio limit that is estimated to be 1 2 m. The carrier cocetratio measuremet rage, meawhile, is about cm -3, ad the cocetratio resolutio whe expressed i scietific otatio is oe sigificat digit. 3) Thus, STM ca achieve the level of resolutio required for developig devices beyod the 90-m ode. 3. Better performace for scaled trasistors The results of observig a cross sectio of a scaled trasistor as a example of STM-based 2D carrier profilig are show i Figure 3. This is a 2D carrier profile of a p-type metal-oxidesemicoductor field-effect trasistor (MOSFET) with a gate legth of 38 m. To eable STM measuremets, the sample cross sectio was first polished to obtai a flat observatio surface with ueveess of less tha 1 m. Next, the sample was immersed i a hydrofluoric acid solutio to selectively remove silico dioxide film. This treatmet resulted i hydroge termiatio of the silico surface to be measured by STM. 6) After the hydroge termiatio was completed, the sample was trasported to a ultrahigh vacuum ad STM measuremets were performed. As described above, the outer geometric shape of the MOSFET, such as the gate electrode, was measured from a surface topographic image, ad the 2D carrier profile was simultaeously obtaied as a tuelig curret profile image. By combiig these two, we could successfully visualize the state of the source/drai extesio () regios of the source/drai electrodes uder the gate electrode. The obtaied 2D carrier profile ca be used to determie the aoscale lateral overlap legth of the uder the gate, X ov (show i Figure 1). Usig this evaluatio method, we measured Gate X ov Probe p Source Drai Tuelig curret p Figure 2 Tuelig curret image of aoscale p juctio. Figure 3 2D cross-sectioal carrier profile of 38-m p-mosfet. FUJITSU Sci. Tech. J., Vol. 46, No. 3 (July 2010) 239

4 H. Fukutome: Two-Dimesioal Carrier Profilig by Scaig Tuelig Microscopy ad Its Applicatio to Advaced Device Developmet various trasistor cross sectios fabricated uder differet coditios ad clarified that a differece i those coditios could chage the average value of X ov by 2 m. 7) We also foud that the STM measuremet results agreed well with the device threshold voltage roll-off characteristics (threshold voltage gate-legth depedece). I other words, we foud that STM-based 2D carrier profilig techology has a spatial resolutio of better tha 2 m, which makes it capable of cotributig to the optimizatio of trasistor process coditios. Thus, by usig STM techology to deepe our uderstadig ad kowledge of the mechaisms behid dopat diffusio suppressio techiques, 8) such as fluorie co-implatatio, we were able to achieve dopat profile optimizatio i a relatively short time, which accelerated the developmet of advaced high-performace devices beyod the 90-m ode. By usig STM, we were also able to directly evaluate the effects of small chages i the shape of the sidewall spacer 9) o the dopat profile ad directly examie lateral aomalous diffusio of dopats alog the iterface of the sidewall spacer. 10) By correlatig these fidigs with device performace, we were able to cotribute to the optimizatio of 2D dopat profiles i the regios. 4. Reduced variability i trasistor performace I additio to observig trasistor cross sectios, we also measured surface carrier profiles directly uder the gate electrode. scaled trasistors, the threshold voltage is ofte determied by the leakage curret betwee the source ad drai, so the effective chael legth (L eff ) is a importat evaluatio item. We therefore measured, for the first time i the world, the correlatio betwee the gate lie edge roughess (LER) ad profile. 4) There have bee cocers that gate LER variability ca affect the performace of scaled trasistors. I the past, there was o way other tha computer I simulatio 11) to check this, but ow such pheomea ca be evaluated directly by STM. 4.1 Evaluatio of correlatio betwee gate LER ad profile Here, I outlie a method for evaluatig the correlatio betwee gate LER ad profile. First, the gate is selectively removed to expose the active regios to be observed. Next, the same processig as i the cross-sectio measuremets is applied to remove the sidewall structure ad gate isulatio film, ad the active-regio surface is hydroge termiated. As a result, at the time of gate processig, the silico substrate i the trasistor fabricatio process is dug away by several aometers, which trasfers the gate shape to the active-regio surface. Cosequetly, the positio of the gate edge ca be extracted from a topographic image, ad at the same time, the 2D carrier profile of the active-regio surface ca be obtaied by measurig the tuelig curret profile. By combiig these two pieces of iformatio, we ca evaluate the correlatio betwee gate LER ad L eff fluctuatio or X ov fluctuatio. 4.2 Evaluatio results A typical 2D carrier profile of the ad the chael regio directly udereath the gate electrode i a -MOS trasistor with sub-50-m gate legths is show i Figure 4. As show i Figure 4 (a), gate legth L g (y), lateral overlap legth X ov (y), ad effective gate legth L eff (y) ca be locally determied. I additio, we ca see from the results i Figure 4 (b) that there is a correlatio betwee gate LER ad X ov. Moreover, the -edge fluctuatio icreases or decreases accordig to this correlatio. Thus, if we suppress dopat diffusio i order to operate a trasistor with a relatively short L g, the lateral edge will fluctuate, reflectig the gate LER, ad L eff fluctuatio will icrease. We also cofirmed that if L eff fluctuatio icreases as predicted from STM measuremets, V th (threshold voltage) fluctuatio 240 FUJITSU Sci. Tech. J., Vol. 46, No. 3 (July 2010)

5 H. Fukutome: Two-Dimesioal Carrier Profilig by Scaig Tuelig Microscopy ad Its Applicatio to Advaced Device Developmet Source Gate Drai L g (y) p dopat oly (1) dopat oly (2) Dopat-diffusio suppressio Fully diffused X ov (y) X ov (m) 10 L eff (y) 5 0 Diffusio suppressed 20 m Gate LER (m) (a) 2D carrier profile i active-regio surface uder gate Figure 4 Relatioship betwee gate LER ad carrier profile aroud extesio regio. (b) Relatioship betwee X ov i extesio uder gate ad gate LER will likewise icrease. 4.3 Improved trasistor fabricatio From the above discussio, we ca expect performace variability, which hiders the ormal operatio of circuits, to become a serious problem whe we scale dow trasistors to raise LSI performace ad itegratio. By utilizig the STM measuremet results, we developed trasistor fabricatio methods that reduce dopat profile fluctuatio. For example, we developed a amorphous gate as a fabricatio method for improvig dopat profile fluctuatio. 12) We also devised a io implatatio method for formig the regios ad showed that it could reduce a scaled trasistor s L eff fluctuatio by 15% ad V th fluctuatio by 15%. 13) Techiques like these for reducig trasistor performace variability are oe of the most importat ways to make possible advaced devices of the 40-m process geeratio ad beyod, ad 2D carrier profilig has played a importat role i their developmet. 5. Fault aalysis 2D carrier profilig of active-regio surfaces ca also be used to evaluate the dopat profile of the active regio modulated ear the shallow trech isolatio regio. For example, we have clarified that X ov gradually decreases at poits closer to the shallow trech isolatio regio. 14) It is also possible to apply 2D carrier profilig to active-regio surfaces of arrow-chael MOSFETs typical of static radom access memory (SRAM), ad we have show that the dopat profile of scaled trasistors i SRAM ca sigificatly chage from the ideal state through the effects of gate LER ad shallow trech isolatio. 14) These results suggest that a STM system with auxiliary equipmet for idetifyig the probe positio could be used to aalyze SRAM defect locatios. 6. Coclusio This paper described STM-based 2D carrier profilig ad preseted examples of its applicatio to semicoductor device developmet. This techique, which eables 2D dopat profiles to be actually observed, has cotributed to the efficiet developmet of advaced semicoductor devices. Lookig forward, we foresee ew applicatio methods that exploit the advatages of STM as a surface-sesitive measuremet techology FUJITSU Sci. Tech. J., Vol. 46, No. 3 (July 2010) 241

6 H. Fukutome: Two-Dimesioal Carrier Profilig by Scaig Tuelig Microscopy ad Its Applicatio to Advaced Device Developmet (havig high 2D resolutio o the measuremet surface) as i the evaluatio of dopat profile fluctuatio, ad we evisio combiatios of STM with other measuremet techologies ad techology computer aided desig (TCAD). Refereces 1) G. Biig et al.: Surface Studies by Scaig Tuelig Microscopy. Phys. Rev. Lett., Vol. 49, Issue 1, pp (1982). 2) M. B. Johso et al.: Scaig tuelig microscopy ad spectroscopy for studyig crosssectioed Si (100). J. Vac. Sci. Techol., B, Vol. 10, Issue 1, pp (1992). 3) H. Fukutome et al.: Two-dimesioal characterizatio of carrier cocetratio i metal-oxide-semicoductor field-effect trasistors with the use of scaig tuelig microscopy. J. Vac. Sci. Techol., B, Vol. 22, Issue 1, pp (2004). 4) H. Fukutome et al.: Direct Evaluatio of Gate Lie Edge Roughess Impact o Extesio Profiles i Sub-50-m -MOSFETs. IEEE Trasactios o Electro Devices, Vol. 53, No. 11, pp (2006). 5) R. J. Hamers et al.: Surface Electroic Structure of Si(111)-(7 7) Resolved i Real Space. Phys. Rev. Lett., Vol. 56, Issue 18, pp (1986). 6) Y. Morita et al.: Ideal hydroge termiatio of Si (001) surface by wet-chemical preparatio. Appl. Phys. Lett., Vol. 67, Issue 18, pp (1995). 7) H. Fukutome et al.: Gate isulatig layer impact o the extesio profile of the sub-50 m p-mosfet. Ext. Abstr. Iteratioal Workshop o Juctio Techology 2002, 2002, pp ) H. Fukutome et al.: Fluorie Implatatio Impact i Extesio Regio o the Electrical Performace of Sub-50 m p-mosfets. Iteratioal Electro Devices Meetig Tech. Digs., 2003, pp ) H. Fukutome et al.: Direct Measuremet of Offset Spacer Effect o Carrier Profiles i Sub- 50 m p-metal Oxide Semicoductor Field-Effect Trasistors. J. Jp. Appl. Phys, Vol. 45, No. 4B, pp (2006). 10) H. Fukutome et al.: Aomalous diffusio i the extesio regio of aoscale MOSFETs. Iteratioal Electro Devices Meetig Tech. Digs., 2001, pp ) A. Aseov et al.: Itrisic Parameter Fluctuatios i Decaaometer MOSFETs Itroduced by Gate Lie Edge Roughess. IEEE Trasactios o Electro Devices, Vol. 50, No. 5, pp (2003). 12) H. Fukutome et al.: Suppressio of Poly-Gateiduced Fluctuatio i Carrier Profiles of Sub-50 m MOSFETs. Iteratioal Electro Devices Meetig Tech. Digs., 2006, pp ) H. Fukutome et al.: Comprehesive Desig Methodology of Dopat Profile to Suppress Gate- LER-iduced Threshold Voltage Variability i 20 m NMOSFETs. Tech. Digs. of Symposia o VLSI techology, 2009, pp ) H. Fukutome et al.: Direct Measuremet of Effects of Shallow-Trech Isolatio o Carrier Profiles i Sub-50 m N-MOSFETs. Tech. Digs. of Symposia o VLSI Techology, 2005, pp Hideobu Fukutome Fujitsu Semicoductor Ltd. Dr. Fukutome received B.S., M.S., ad Ph.D. degrees i Solid State Physics from Osaka Uiversity, Osaka, Japa i 1994, 1996, ad 1999, respectively. I 1999, he joied Fujitsu Laboratories Ltd., Atsugi, Japa, where he has bee egaged i research ad developmet of a two-dimesioal carrier profilig techique ad developmet of the 90-, 65-, 45-, ad 32-m-ode CMOS devices usig this techique. He moved to Fujitsu Semicoductor Ltd. i He was a visitig researcher at ETH Zurich (Swiss Federal Istitute of Techology) i He received the Youg Scietists Prize from the Miistry of Educatio, Culture, Sports, Sciece ad Techology i He left Fujitsu Semicoductor Ltd. i April FUJITSU Sci. Tech. J., Vol. 46, No. 3 (July 2010)