DDR4 Board Design and Signal Integrity Verification Challenges

Transcription

1 DesigCo 2015 DDR4 Board Desig ad Sigal Itegrity Verificatio Challeges Niti Bhagwath, Metor Graphics Chuck Ferry, Metor Graphics Atsushi Sato, Fujitsu Semicoductor Limited Motoaki Matsumura, Fujitsu Semicoductor Limited Akihiro Miki, Fujitsu VLSI Limited Rady Wolff, Micro Techology Arpad Murayi, Metor Graphics

2 Abstract Besides faster data rates, the ew DDR4 stadard icorporates additioal chages from prior DDR techologies which impact the board desig egieer. New factors i DDR4 such as a asymmetric termiatio scheme, data bus iversio ad sigal validatio usig eye masks require ew methods of validatig desigs through simulatio. This paper ivestigates the effects of DDR4 s Pseudo Ope Drai (POD) driver o data bus sigalig ad describes methodologies for dyamically calculatig the DRAM s iteral VrefDQ level required for data eye aalysis, methodologies for geeratig ad verifyig the data eye as well as ways of icorporatig write levelig ad calibratio ito the simulatio. Additioally, evaluatio of Simultaeous Switchig Noise (SSN) by icorporatio of power itegrity effects ito the sigal itegrity aalysis is also critical to board desig ad timig closure ad will be elaborated with examples. A system desig example usig IBIS 5.0 power aware models will be described icludig a simulatio accuracy study comparig the IBIS results with trasistor-level models. Authors Biographies Niti Bhagwath is a Techical Marketig Egieer at Metor Graphics. He has desiged ad architected high-speed systems for Hewlett Packard ad Cisco for te years. He has bee with the highspeed simulatio group at Metor Graphics for two years, where he advises simulatio desig o multigigabit SerDes sigals, power itegrity ad DDR memory. Niti represets Metor Graphics at JEDEC for the memory groups. Niti has a bachelors i Electroic Egieerig from Bagalore Uiversity, a MS i EE from Purdue Uiversity ad a MBA from the Idia Istitute of Maagemet, Bagalore. Chuck Ferry is a product marketig maager at Metor Graphics Corporatio. Chuck focuses o product defiitio ad validatio for sigal itegrity ad power itegrity solutios. He has spet the last 16 years tacklig a broad rage of high speed digital desig challeges spaig from system level desig to multigigabit chael aalysis developig ad icorporatig detailed characterizatios of the IC, packages, coectors ad multiple boards. He has delivered sigal itegrity services ad semiars usig a wide rage of EDA tools as well as performed modelig services creatig ad validatig IC models. Chuck graduated Maga cum Laude from the Uiversity of Alabama with a BSE i electrical egieerig ad cotiued graduate course work i the areas of sigal processig ad hardware descriptio laguages. Atsushi Sato is maager of Desig Methodology Developmet Divisio at Fujitsu Semicoductor. Curretly, he maages a team resposible for LSI-PKG-Board co-desig Methodology Developmet for sigal ad power itegrity. Sice joiig Fujitsu Semicoductor i 2006, he had worked at Fujitsu Laboratory as a Research Egieer of sigal ad power itegrity. He received his M.S. degree i Electroics Egieerig from Tohoku Uiversity i Japa. Motoaki Matsumura is a Hardware Egieer at Fujitsu Semicoductor. He curretly works o modelig ad simulatio of DDR4 Memory Iterfaces. His prior work ivolved full board simulatios ad timig aalysis icludig Simultaeous Switchig Noise (SSN) effects. He has a Master degree i Elemetary Particle Physics from Tohoku Uiversity i Japa. Akihiro Miki joied Fujitsu VLSI te years ago. Akihiro is ow a Memory Solutio Developmet

3 Maager for IP Platform Solutios Divisio. His work is supports Memory Iterfaces IP. Rady Wolff is a Pricipal Egieer ad leads the Silico Sigal Itegrity team at Micro Techology. He is curretly resposible for IBIS ad HSPICE model developmet for most DRAM, NAND ad NOR products. He has also served as Secretary of the IBIS Ope Forum committee sice He received his B.S. degree i electrical egieerig, graduatig cum laude from Motaa State Uiversity. Arpad Murayi joied Metor Graphics Corporatio i His work icludes developig ad testig advaced modelig ad simulatio techologies for Metor's leadig edge sigal itegrity simulatio products. He also serves as the chairma of the IBIS Advaced Techology Modelig Task Group which is resposible for developig support for such ew techologies i the IBIS specificatio. He was oe of the co-fouders of the IBIS specificatio. Before he joied Metor, Arpad worked at Itel Corporatio i Folsom, CA as a Sigal Itegrity egieer. He was oe of the first members of the Sigal Itegrity group i the Chipset Divisio of Itel Corporatio i Folsom. His job assigmets icluded sigal itegrity simulatios o umerous bus iterfaces, icludig the first 33 MHz PCI bus for the PCISet products. Arpad was also ivolved with developig ew behavioral I/O buffer modelig algorithms ad methodologies at Itel for advaced buffers usig the Verilog-AMS ad VHDL-AMS modelig laguages. Arpad graduated i 1991 from the Califoria State Uiversity Sacrameto with a BSEE degree.

4 Itroductio DDR4 is the ext step i JEDEC s family of DRAM parts. It has bee developed to serve the market eeds of higher speeds ad lower power cosumptio. These factors have cotributed to ew features i DDR4, as well as ew requiremets which eed to be accouted for while desigig a DDR4 system. The first sectios of this paper ivestigate DDR4 s Pseudo Ope Drai driver ad what its use meas for power cosumptio ad Vref levels for the receivers. Subsequet sectios of the paper look at a DDR4 system desig example ad the eed for simulatig with IBIS power aware models versus trasistor level models for Simultaeous Switchig Noise characterizatio. Advatage of POD over SSTL Oe of the major market forces actig o the DRAM idustry is the demad for lower power cosumptio of the memory devices. To this ed, DDR4 uses a ew drive stadard, kow as Pseudo Ope Drai, or POD. I POD, the receiver termiates the sigal to a high level, rather tha to half the rail voltage. Figure 1 - Termiatio of DDR4 (POD) ad DDR3 (SSTL) To see the differece that the termiatio scheme makes i the total power cosumptio, the curret draws i the low ad high states ca be compared. Whe i the low state, there is a curret draw i both SSTL ad i POD. I fact, POD might draw slightly higher curret sice the termiatio is to the voltage rail whereas the termiatio is to oly half the voltage rail i SSTL. This is somewhat offset by a slightly lower voltage rail i DDR4. Figure 2 - Curret Compariso whe drivig Low However, the mai differece betwee the two drive optios is highlighted whe a high is drive. Whereas SSTL cotiues to draw curret at a rate approximately equal to whe drivig low, POD draws o power whe drivig a high.

5 Figure 3 - Curret compariso whe drivig High So, the way to decrease system power with DDR4 is to maximize the umber of highs beig drive. This is where the DBI feature comes i hady. If there are at least 5 DQ sigals i a 8-bit lae which are drive low, the all bits are toggled, ad the Data Bus Iversio (DBI) sigal is asserted low to idicate that the iversio has take place. This way, out of the total of 9 sigals (8 DQ sigals ad oe DBI), at least five are drive high. If the origial data cotais four or more DQ sigals beig drive high, the the DBI sigal is de-asserted high, oce agai esurig at least 5 of the total 9 bits beig drive high. This way, o each trasactio, it is guarateed that at least 5 of the 9 bits are drive i the power reduced high state. Figure 4 - With DBI, if 5 or more lows are drive, toggle the etire byte Calculatio of Vref I DDR3, a exteral referece voltage is used to compare the iput sigal to determie a high vs. a low. This exteral voltage is ofte a geerated either by a voltage divider which is the filtered, or by a exteral precisio voltage regulator. DDR4 however, requires that the Vref be geerated withi the DRAM, ad be adjustable. The Vref will be set to a value o each powerup. Need for dyamically calculatig Vref To highlight why this variable Vref is eeded i DDR4, cosider a simple setup of a DDR3 ad DDR4 driver drivig ito a termiatio resistor which has bee strapped to the appropriate voltage. By calculatig the voltage at the receiver whe a high is drive, ad whe a low is drive, the average will be the ideal voltage to be used as the referece threshold voltage sice this level will be equidistat to the high ad low sigals. To calculate this ceter voltage a simple setup with driver ad termiatio is aalyzed. To simplify calculatios, the trasmissio lie is take to be very short, ad the driver stregth whe drive high ad low is assumed to be equal. We ca first cosider the DDR3 case.

6 Figure 5 - DDR3 drivig high (left) ad low (right) Whe drivig high, the voltage at the receiver will be the superpositio of the effect of the two voltage sources, Vdd/2 ad Vdd. R t V h = (V dd ) ( ) + ( V dd R t + Z d 2 ) ( Z d ) R t + Z d V h = ( V dd 2 ) (2R t+z d R t + Z d ) Whe drivig low, the voltage at the receiver will be a simple voltage divider V l = ( V dd 2 ) ( Z d R t + Z d ) The ceter voltage for this DDR3 setup ca the be obtaied by takig the average of the two results. V avg = V h + V l 2 = V dd 2 = [( V dd 2 ) (2R t+z d ) + ( V dd R t + Z d 2 ) ( Z d )] [( V dd R t + Z d 2 ) (2R t+2z d )] R 2 = t + Z d 2 This value is always half the rail voltage. It is costat with respect to all other aspects of the setup, icludig termiatio values or drive stregths. We ca the cosider the DDR4 case, ad apply the same sequece as above. Whe DDR4 is drive high, the voltage at the receiver is simply Vdd sice both the termiatio ad the driver are strapped to Vdd. Similar to DDR3 whe drivig low, the receiver voltage is the result of the voltage divider. Figure 6 - DDR4 drivig high (left) ad low (right)

7 Agai, the ceter of the receiver eye will be the average of the two values. V avg = V h + V l 2 = Z d [(V dd ) + (V dd ) ( R t + Z )] d 2 = ( V dd 2 ) + (V dd 2 ) ( Z d R t + Z d ) Note that i this situatio, the ceter voltage value is depedet o ot oly the supply voltage, but also o the characteristics of the trasmitter ad receiver. This implies that the ideal voltage to be used at the receiver will deped o the setup, o the silico batch, read vs. write ad other system variables. To see the effects, we ca cosider a simple driver, trasmissio lie, receiver setup. The termiatio resistace of the receiver is varied to see the effect of the eye for DDR3 ad DDR4. Figure 7 - setup to observe eye ceter vs. receiver termiatio First, with DDR3, as the receiver termiatio is weakeed from 40 Ohms to 60 Ohms to 120 Ohms, the sigal is allowed to freely go towards greater extremes both highs ad lows. However, the ceter of the eye for all three settigs is always fixed at Vdd/2. Figure 8 - DDR3 eyes with ODT sweep For the DDR4 setup, the receiver ODT is varied from 40 to 60 to 80 Ohms. With the weaker termiatio, the lows are allowed to go lower, but the high value stays more or less fixed. This causes the ceter value of the eye to icrease with stroger (lower value) termiatio.

8 Figure 9 - DDR4 eyes with ODT sweep Compariso of algorithms for calculatig Vref Now, each pi of a give device might have differet requiremets for referece voltage due to slight variatios betwee the pis ad layout. However, the device cost, both i terms of silico ad power, would be too prohibitive to set a separate referece for each pi separately. So, a commo referece voltage eeds to be calculated which optimizes the respose of all the pis usig this referece. We will compare two optios for calculatig this commo referece voltage below. The first optio ( Optio 1 ) to geerate the referece voltage takes the average of all the sigals. The secod optio ( Optio 2 ) uses oly the extreme sigals ad use the average of the extreme sigals. As a example, if a 8-pi device receives optimal referece voltages o the 8 pis as 800mV, 750mV, 730mV, 725mV, 720mV, 710mV, 705mV ad 700mV, the the device Vref will be as follows: Optio 1: Optio 2: = 750mV 2 = 730mV To aalyze the effects of usig the two optios, let us first cosider the average margi loss for the device whe usig each of these optios. Cosider a pi x i a device d. The receiver eye at the pi might have a voltage ceter, Vx, which is optimal for that pi. The device however has a differet referece voltage, Vd, which it uses for several pis i that device. Correspodig to each of these referece voltages will be a set of high ad low threshold levels. Now, for a give sigal (show i red i the diagram below), the optimal margi from the threshold level will be Mp. However, sice the actual voltage beig used for the threshold might ot be optimal, the actual margi is give by Md.

9 Figure 10 - Margi for pi The Margi lost o accout of usig the device referece istead of the optimal referece of the pi is give by: Margi Loss = M p M d = V d V x Note that the margi lost ca be egative, which implies a margi gai. For a margi lost o the high side, a equivalet margi will be lost o the low side, ad vice versa. Next, we ca compare the average margi loss usig two differet algorithms to determie Vref. Optio 1 uses the average of all the sigals as the referece voltage. V d = V x. (Device Vref is average of all pis) So, Average Margi Loss = (V d V x ) = V d V x = V d V d = 0 This is somewhat ituitively expected. Whe the referece voltage is obtaied by usig all the sigals, the average margi loss is zero because for each pi, the margi lost will be offset by the margi gaied by aother set of pis i the group. Now, cosiderig optio 2, the referece voltage for the device is take as the average of the highest ad lowest voltages. V d = V max+v mi. (Device Vref is average of extreme pis) 2 So, Average Margi Loss = (V d V x ) = (V d V max ) + (V d V mi ) + x max,mi (V d V x ) = (V d V max ) + (V d V mi ) + x max,mi (V d V x ) = 2V d (V max + V mi ) + (V d V x ) x max,mi

10 = 2 (V max + V mi 2 = x max,mi (V d V x ) ) (V max + V mi ) + x max,mi (V d V x ) The average margi loss is ot zero. Either o the high or the low side, the average margi loss will be greater tha zero. However, although it may appear that optio 1 might be the better course, optio 2 actually works out better whe we cosider the extreme sigals. Let us take as a example a eyemask requiremet of DDR4. The eyemask height requiremet is 136mV, or threshold±68mv. Figure 11 - DDR4 eyemask example So, if optio 1 were used, the the requiremet for the sigal would be 730±68, or 662mV o the low side ad 798mV o the high side. Similarly, with optio 2, the requiremet for the sigal would be 750±68, or 682mV o the low side ad 818mV o the high side. Next, we ca take a look at the pi which has a optimal ceter of 800mV, ad compare the results with a referece voltage usig optio 1 vs. optio 2. Let us assume that the sigal arrivig at this pi has a peak-to-peak swig of 260mV, or 800±130mV (730mV o high side, ad 670mV o low side). This eye should be able to pass all sigals if a optimal threshold is selected. As ca be see from the diagram below, this implies that the sigal with optio 1 (730mV) as Vref will have a large margi o the high side, but will fail o the low side. The sigal usig optio 2 (750mV) as Vref, however, will have a smaller margi o the high side, but will pass o the low side as well. Figure 12 - Eye behavior with differet Vref calculatios

11 I geeral, if the extreme high ad low requiremets across all pis of the device are give by Vh ad Vl, the icomig eye eeds to have a eye-height of at least Vh-Vl if a commo referece voltage is to be used. I this case, assumig that the high ad low requiremets from the threshold are equal, the threshold eeds to be at (Vh+Vl)/2, which oly cosiders the two extreme sigals, ad ot the other sigals. A threshold set to ay other level might cause issues with some sigals eve if the eye opeig is at least Vh-Vl. By takig oly the extreme sigals ito accout whe calculatig the referece voltage to be used, the margi of the remaiig sigals may be reduced. However, by esurig that the extreme high ad low sigals pass, it will be esured that all the other sigals pass as well. Geeratio of the Data Eye DDR4 has borrowed the cocept of a eye-mask from SerDes techology to validate receiver sigals, as see i Figure 11. However, ulike SerDes sigals, the DDR4 sigals do t have a clock embedded withi the data stream. The data is clocked by a exteral sigal DQS for data ad CLK for the address/commad. So, the geeratio of the eye either whe simulatig or whe measurig o a oscilloscope must ot be geerated by wrappig the DQ waveform aroud itself at a fixed bit period. Sice the DQ sigal is sampled usig the explicit DQS, the eye must be formed by samplig aroud the DQS. This will accout for the irregularities of the DQS sigal. Oe method to do so would be to sample the data sigal for a predetermied time widow aroud each strobe crossig as i Figure 13. If the strobe is early, the some parts of the data sigal might be shifted. If the strobe is delayed, there might be parts of the data which are ot visible i the widow. This is how the actual device would react, sice ay shift i the DQS will affect the samplig of the sigal. Figure 13 - Eye created by widowig data aroud strobe To illustrate this, the followig is a simulatio of a DQS ad a DQ. The two parts of the DQS are itetioally mismatched so as to create a o-ideal strobe at the receiver. The sigal is ru at 2400Mbps.

12 Figure 14 - Setup to highlight effect of imperfect strobe If the receiver sigal is simply wrapped aroud at ps (oe UI at 2400Mbps), the the eye has a jitter of about 12ps. Figure 15 - Data eye with o strobe variatio effect (left) vs. Data eye icludig strobe imperfectios (right) However, if the eye is created by samplig the sigal aroud the strobe, the eve discoutig the rut sigal caused by the iitial strobe trasiet, the jitter as see by the data sigal icreases to 20ps. Power Aware IBIS for DDR4 simulatio IO models (SPICE Netlist or IBIS 4.2 vs IBIS 5.0) Wide parallel memory busses ca preset sigificat desig challeges whe it comes to desigig a robust power delivery etwork (PDN). Oe critical focus of PDN desig is delivery of power to the memory chip output drivers. The o-chip data (DQ) drivers ca require sigificat amouts of curret delivered through sometimes highly iductive package coectios. These simultaeous switchig outputs (SSO) ca cause sigificat oise issues that traslate ito timig jitter ad sigal itegrity (SI) problems.

13 Mitigatig SSO issues i a system requires optimizig the desig of the PDN of the prited circuit board (PCB), package ad o-die. Detailed circuit models are eeded for each piece. Historically, these circuit models are combied ad simulated i SPICE based simulators to aalyze SSO effects. These simulatios are computatioally itesive ad lead to legthy simulatio times of hours to days. For solutio-space ad what-if aalysis, simulatio times are simply too log. SPICE-based trasistor level models of the o-die drivers are ofte the most complex part of the system model. This is especially true for the most accurate models that iclude layout-based RC parasitic circuit elemets. Oe effective way to reduce simulatio time is to use behavioral buffer models. Behavioral models use simpler algorithms tha SPICE models, eablig faster simulatio with ofte similar levels of accuracy. The I/O Buffer Iformatio Specificatio (IBIS) is a behavioral modelig format used idustry-wide for SI simulatio. Commoly used versios of the IBIS specificatio iclude IBIS 4.2 ad IBIS 5.0. Figure 16 shows commo implemetatios of a IO circuit model usig a SPICE etlist, IBIS 4.2 ad IBIS 5.0. Figure 16 - Setup compariso betwee SPICE, IBIS 4.2 ad IBIS 5.0 IBIS 4.2 ad IBIS 5.0 have tables of data that describe circuit characteristics of the fial IO buffer. IBIS 4.2 assumes ideal power coected to the buffer. Thus, the SSO oise caot be take ito accout i the simulatio. IBIS 5.0 exteded the usefuless of IBIS for Power Itegrity (PI) simulatio specifically eablig the simulatio of SSO oise. New keywords i IBIS 5.0 specific to PI iclude [Composite Curret], [ISSO PU] ad [ISSO PD]. [Composite Curret] data are I-T tables that describe the shape of the risig ad fallig edge curret waveforms from the power referece termial of the buffer (VDE). This switchig curret icludes

14 cotributios from the o-die decouplig circuit, crow-bar curret, ay termiatio curret, sigal driver curret ad pre-driver curret. Fial driver curret could be derived accurately by simulatig IBIS 4.2 models, but this ca sigificatly uderestimate the total driver curret without details of the pre-driver cotributio. [ISSO PU] ad [ISSO PD] data are tables describig the effective curret of the pullup ad pulldow driver trasistors as a fuctio of the voltage o the pullup ad pulldow supply referece odes. The PI problem beig modeled is kow as gate modulatio ad is caused by droopig power supply voltages o-die as the die PDN attempts to pull curret istataeously through the iductive package PDN. I additio to the [Composite Curret], [ISSO PU] ad [ISSO PD] data tables i the IBIS file, it is ecessary to iclude the characteristics of the o-die power supply decouplig structure. Due to limitatios i the IBIS specificatio, a model of the decouplig s electrical behavior must be icluded i SSO simulatios exteral to the IBIS buffer model, coected across the power ad groud referece termials. Trade-offs betwee SPICE Netlist, IBIS 4.2 ad IBIS 5.0 Table 1 shows a compariso of simulatio time betwee the models. Simulatio with IBIS models (both 4.2 ad 5.0) is about te times faster tha with the SPICE etlist. There is a tedecy of simulatio time of SPICE etlists to icrease with faster data rates. SPICE Netlist IBIS 4.2 IBIS 5.0 Simulatio time Loger Shorter Shorter SI simulatio accuracy High High High PI simulatio accuracy High Low High Table 1 - Modelig trade-offs For improved SI, DDR3 used ZQ (Zero Quotiet) calibratio ad ODT (O Die Termiatio). I additio to those, DDR4 has Vref traiig fuctioality i the IO circuit, which ca make SPICE Netlists much larger. For example, i DDR4 the umber of elemets (that icludes both MOSFET ad parasitic RC) per SPICE etlist balloos to several tes of thousads. I order to simulate SSO oise, it is ecessary to model the full data chael, so the umber of elemets ca reach several hudreds of thousads. With this may elemets, simulatio time ca take days. DDR4 simulatio with SPICE etlists of the IO is ot realistic. Sice IBIS models have oly data tables modelig the output circuits, simulatio time is sigificatly shorteed. IBIS 4.2/5.0 both provide accurate simulatio results with ideal power coditios. Whe SSO oise is imposed, IBIS 4.2 has accuracy issues, but IBIS 5.0 gives a good match to SPICE etlist simulatio. As see i Figure 17, there is a trade-off betwee simulatio time ad accuracy whe SPICE etlists ad IBIS 4.2 models are the choices. However, IBIS 5.0 balaces both performace ad accuracy well.

15 Figure 17 - Voltage oise compariso betwee SPICE etlist, IBIS 4.2 ad IBIS 5.0 Old but ew issue of IBIS model Over Clockig IBIS models have assumptio of a maximum workig frequecy that provides better accuracy. If a buffer is switched faster tha that frequecy, the accuracy will be sacrificed. This pheomeo is called Over Clockig. The maximum workig frequecy depeds o the waveform described i the V-T tables. These waveforms ca be broke dow ito three sectios: iitial delay area, active area, ad iactive area as see i Figure 18. To get a accurate result, the followig formula eeds to be satisfied: Legth of a half cycle Legth of Iitial Delay + Legth of Active Area Figure 18 - Overclockig waveform regios It is commo i simulatio software to remove the iitial delay area i a IBIS 4.2 model, which helps avoid the Over Clockig problem. However, this techique caot be used for IBIS 5.0 models. Sice [Composite Curret] icludes the curret of the pre-driver, the iitial delay area caot be trucated sice curret is see i this area (see Figure 19).

16 Figure 19 - Clippig output waveforms with composite curret To avoid Over Clockig problems, simulators are required to deal with waveforms that have log iitial delay areas for IBIS 5.0 simulatio. The simulator must support Legth of a half cycle = Legth of Active Area. Figure 20 illustrates the cocept of how each area of the V-T ad I-T waveforms eeds to be hadled to geerate the correct voltage ad curret waveforms that do ot show artifacts of overclockig problems. Figure 20 - Composite Curret calculatio

17 Figure 21 shows a compariso betwee two simulatio egies. The blue lie i the figure shows the waveform geerated by a traditioal simulator. The correct waveform result i red is geerated by a simulator that employed the improved simulatio techique. Figure 21 - Waveform icorporatig Overclockig Challeges to DDR4 SSO Noise Simulatio Figure 22 shows the simulatio setup for a DDR4 memory iterface desig (also see simulatio schematic i Figure 23). The cotroller is i a FCBGA (Flip Chip Ball Grid Array) package ad two 2400Mbps speed-grade DDR4 SDRAMs are mouted o a 6-layer PCB. Various simulatios were ru usig either SPICE etlists or IBIS 5.0 models for the IO circuits. For the SPICE etlist simulatio, the cotroller IO sigal ad power circuits are modeled i the SPICE etlist, the packages ad PCB are modeled with S-parameters, ad the SDRAMs are modeled with IBIS 5.0. For the IBIS 5.0 simulatio, the cotroller IO sigal circuit is modeled with a IBIS 5.0 buffer model, the IO power circuit is modeled as a RC equivalet circuit, ad the package, PCB, ad SDRAMs are modeled the same as i the SPICE etlist simulatio. Figure 22 - Simulatio Setup

18 Figure 23 - Simulatio Schematic First, a compariso was doe betwee the SPICE etlist model ad IBIS 5.0 model simulatios that do ot have SSO oise or crosstalk oise. The DQS sigal ad oe DQ bit were stimulated at 2400Mbps i Write mode. The measuremet was doe at the die pad of the SDRAM with the DQS as the trigger. Both simulatios matched well as see i Figure 24. The eye widths, referred to as VdiVW, were withi 10ps differece. For this simulatio, the IBIS 5.0 model provides eough accuracy. Figure 24 - SPICE ad IBIS 5.0 compariso without SSO effects Next, SSO oise was examied. The DQS sigals ad 32 DQ bits were operated at 2400Mbps i Write mode, ad the SDRAM die pad ad VDE voltage at the cotroller were measured. The upper waveform i Figure 25 shows the VDE waveform, ad the lower waveform is a DQ sigal s waveform at the SDRAM die pad. Due to the 32 bits of DQ sigals switchig, VDE voltage at the cotroller is fluctuatig, which is the SSO oise. The SPICE etlist model (blue lie) ad IBIS 5.0 model (red lie) meet almost perfectly. It is cofirmed that SSO oise was accurately simulated usig the IBIS 5.0 model.

19 Figure 25 - Power affected by DQ sigal Next, a compariso was doe where SSO oise ad crosstalk oise were imposed. The DQS sigals ad oe DQ sigal (victim) were operated at 2400Mbps i Write mode with the other 31 bits (aggressors) operated both i phase ad out-of-phase with the DQ victim. The measuremet was doe at the SDRAM die pad with the DQS as the trigger. Results are show i Figure 26 Figure 26 - Eyes icorporatig SSO Noise The eye widths i Figure 26 became geerally smaller tha the widths i Figure 24 due to the SSO oise. Comparig results betwee the SPICE etlist model simulatio ad IBIS 5.0 model simulatio shows that IBIS 5.0 eye width is larger (300ps versus 278ps). The IBIS 5.0 model simulatio uderestimated the SSO oise ifluece by 22ps (8%). This uderestimatio was caused by igorig the delay fluctuatios i the pre-driver circuitry. IBIS 5.0 models igore the effects of voltage chages o pre-driver circuitry. Icreasig voltage o-die will make trasistors i the pre-driver circuits switch faster; the opposite effect is see with decreasig voltage. These voltage chages ca lead to mismatches i timig betwee pre-driver pullup ad pulldow sigal paths as well as overall icreased or decreased delay of the driver switchig. Fially, simulatio times were compared. Oe cycle of PRBS7 stimulus for DDR4-2400Mbps is 60s. It took 221 hours (9.2 days) to simulate the schematic show i Figure 23 with the SPICE etlist model. The simulatio of the IBIS 5.0 model was completed i 3 hours, which is a 98.6% reductio from the

20 SPICE etlist model. IBIS 5.0 is useful for large scale simulatio, which is required for chip-package- PCB level co-desig. Figure 27 - Executio time compariso Note: The performace results are based o simulatios i which o attempts were made to esure set up of equivalet simulatio coditios such as time step, hardware, etc. Coclusio A successful DDR4 board desig ca be accomplished usig the aalysis techiques described i this paper. EDA software updated to support DDR4 simulatio ca help the desiger properly use DBI, calculate the proper Vref level for aalysis, apply the DDR4 receiver mask for timig verificatio ad geerate data eyes with correct jitter cotributios. Usig IBIS 5.0 power aware models ca sigificatly speed up simulatio time while allowig for reasoably accurate simulatio of SSO jitter effects.