Adiabatic Array Logic Design of 4x1 MUX and 8x1 MUX without Redundancy

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1 Adiabatic Array Logic Desig of 4x1 MUX ad 8x1 MUX without Redudacy Shivagii 1, Yamii Verma 1, Ashwai Kumar PG Studet [VLSI Desig], Dept. of ECE, IGDTUW, Kashmere Gate, New Delhi, Idia 1 Professor, Dept. of ECE, IGDTUW, Kashmere Gate, New Delhi, Idia ABSTRACT: Adiabatic array logic allows desigig low power digital circuits with more power savig despite havig a equal umber of trasistors with the covetioal CMOS logic style ad PASCL I this paper, 4x1 MUX ad 8x1 MUX is desiged usig Adiabatic Array Logic ad by removig redudat trasmissio gates from Adiabatic Array Logic. The proposed desiged shows the reduced power dissipatio ad also trasistor cout i compariso with basic Adiabatic Array Logic desig. The compariso of power dissipatio is also carried out with siusoidal power supply over a frequecy rage of 100MHz-600MHz. The simulatios are carried out i Cadece Virtuoso at 180m techology, 1.8V CMOS stadard process techology. KEYWORDS: Adiabatic logic; Adiabatic Array Logic; charge recovery; power cosumptio; redudacy; power savig I.INTRODUCTION The icreasig demad of mobile devices ad the eed to limit power cosumptio i VLSI chips led to rapid ad iovative developmets i low power circuit desig durig recet years [6]. The mai motive behid these developmets is mobile devices requirig low power cosumptio ad high throughput. I low power desig techiques, adiabatic logic circuits break the lower limit of the eergy dissipatio i static CMOS which equals to C V / by usig AC power supply istead of the DC power supply. There are several adiabatic logics [4][7][8] have bee developed i several years. Adiabatic Array Logic [1][][3] is ew adiabatic techique which is recetly proposed. It employs a AND plae of trasmissio gates to realize ANDed terms ad a wired OR-plae to OR them. Before the actual work is discussed, a brief theory of adiabatic ad CMOS logic alog with Adiabatic Array Logic is show. Cosider a CMOS iverter with DC supply voltagev. The eergy dissipatio durig chargig/dischargig cycle of load capacitace is give by where α is the switchig probability. 1 E CMOS C LV (1) I adiabatic iverter circuit, the eergy dissipatio durig chargig/dischargig is give by: RC E adia _ diss CV () T The above equatio shows that this eergy loss is iversely proportioal to the chargig time, T. This implies that slower the capacitor is charged, lesser eergy will be dissipated. Also eergy dissipatio govered by the resistace R which is ot i case of the CMOS logic. Copyright to IJAREEIE DOI: /IJAREEIE

2 As adiabatic logic aims to miimize the eergy dissipatio, we have to: E AL E CMOS RC CV T RC T 4 1 CV Or Or (3) This coditio is required for adiabatic logic to better tha the static CMOS logic. The physical sigificace of equatio (3) is that the chargig time T of the capacitor should be high i.e., the chargig process should be slow. This is achieved by usig a AC supply such as ramp or siusoidal voltage istead of the DC voltage. Figure 1. Ramp voltage Figure. DC voltage Ramp voltage used i adiabatic logic is called the power clock. It has four itervals: evaluate (E), hold (H), recover (R) ad wait (W), as show i Fig.3. Fig.3. Phase i a Adiabatic Power Supply The adiabatic array logic is drive by a siusoidal power supply, the power clock. The logic is show below: Fig.4. Adiabatic Array Logic Copyright to IJAREEIE DOI: /IJAREEIE

3 It cosists of a array of trasmissio gates to form AND plae ad wired OR plae. This circuit ca be aalyzed by trasmissio gate i the ON state represeted with a liear model made up of a resistace R ad a capacitace C [5] at the output ode as show i Fig.4. 1 R V 1 V V t l( ) W t tp C V V V ox L 1 V Vtp l( ) Wp V Vt Vtp pcox Lp Wp p 1 Lp l( Wp W W pcox C ox L Lp L Assumig the triode regio for both PMOS ad NMOS trasistors, the capacitace C is give by: C ON where, L is the overlap ad capacitace ) 1 W ( L L) Cox C (5) jb C jb is due to the juctio betwee the diffusio ad the bulk. II.PROPOSED WORK The Adiabatic Array Logic desigs have some repeated trasmissio gates which cosumes area as well as power. Therefore it is ecessary to make the adiabatic array logic redudat. Here, we have take two circuits 4x1 MUX ad 8x1 MUX to compare basic Adiabatic Array Logic ad Redudat Adiabatic Array Logic. A multiplexer [10][15] (or MUX) is a device that selects oe of several iput sigals ad forwards the selected iput ito a sigle lie. A multiplexer of iputs has select lies, which are used to select which iput lie to sed to the output. 4x1 Multiplexer has 4 iputs, select lies ad 1 output lie. The select lies select oe of the data ad give it to the output. The expressio for the 4x1 MUX is show below: (4) Y S1S 0I 0 S1S 0I1 S1S 0I S1S 0I 3 (6) 8x1 Multiplexer has 8 iputs, 3 select lies ad 1 output lie. The select lies select oe of the data ad give it to the output. The expressio for the 8x1 MUX is show below: Y S3S1S0I 0 S3S1S 0I1 S3S1S 0I S3S1S 0I3 (7) S3S1S0I 4 S3S1S 0I1 S3S1S0I S3S1S 0I 3 Their proposed circuits are show i figures which are desiged usig Cadece Virtuoso at 180m, 1.8V CMOS stadard process techology with W/L=0.6μm/0.18μm for both PMOS ad NMOS, V clk 1. 8V (peak-to-peak), ad Copyright to IJAREEIE DOI: /IJAREEIE

4 load capacitace 0.01pF. Simulatig these circuits provided the output waveforms, below their respective circuits. Four termial MOS trasistors have bee used whose substrate is coected to V ad groud for PMOS ad NMOS respectively. Fig.5(a).4x1 MUX usig Adiabatic Array Logic Fig.5(b).Output Waveform Of 4x1 MUX Adiabatic Array Logic Copyright to IJAREEIE DOI: /IJAREEIE

5 Fig.6(a). Proposed 4x1 MUX Adiabatic Array Logic without redudacy Fig.6(b).Output Waveform Of 4x1 MUX Adiabatic Array Logic without redudacy Copyright to IJAREEIE DOI: /IJAREEIE

6 Fig.7(a).8x1 MUX usig Adiabatic Array Logic Fig.7(b). Output Waveform of 8x1 MUX usig Adiabatic Array Logic Copyright to IJAREEIE DOI: /IJAREEIE

7 Fig.8(a). Proposed 8x1 MUX Adiabatic Array Logic without redudacy Fig.8(b).8x1 MUX usig Adiabatic Array Logic without redudacy Copyright to IJAREEIE DOI: /IJAREEIE

8 III. RESULTS AND DISCUSSION The total power dissipatio of ay circuit ca be defied as the sum of the products of the voltage ad curret of all power sources preset withi the circuit. To calculate the power savigs i the circuits, the eergy cosumptio E is computed as below: s s E T s 0 i 1 V pi I pi dt Where T (=1/ f ) = the period of the primary iput sigal; V = the power supply voltage, p (8) I p = the power supply curret, ad i = umber of power supply. Therefore, eergy dissipatio E is equal to the et eergy flowig ito the circuit from the power supply. The propagatio delay [5] of the circuit should be cosidered to measure performace of the circuit. The trasmissio gate ca be modelled as a ohmic series resistace R bouded by capacitace by two grouded capacitace C. The step respose delay t of chai of RC elemet is give by t RC D RC D i0 R C i i where i is o of ode. (10) The total power dissipatio ad propagatio delay of the proposed circuit ad basic Adiabatic Array Logic circuits are evaluated by doig trasiet aalysis at differet frequecy ragig from 100 MHz to 600 MHz of siusoidal power supply. Area per chip is calculated by formula W*L*Trasistor cout. TABLE I. PERFORMANCE ANALYSIS OF ADIABATIC ARRAY LOGIC STYLE AND CMOS LOGIC STYLE FOR 4X1 MUX AND ADIABATIC ARRAY LOGIC WITHOUT REDUNDANCY Parameter Adiabatic Array Logic CMOS logic Adiabatic Array Logic without redudacy Trasistor cout Area per chip(μm ) Dissipatio(μW) at 00 MHz Delay at 00MHz TABLE II. Frequecy of Siusoidal Power Supply (MHz) POWER DISSIPATION OF ADIABATIC ARRAY LOGIC STYLE AND PROPOSED ADIABATIC ARRAY LOGIC 4X1 MUX AT DIFFRENT FREQUENCY OF SINUSOIDAL POWER SUPPLY Dissipatio(μW ) of Adiabatic Array Logic Style Dissipatio (μw) of Adiabatic Array Logic Style Without redudacy Propagatio Delay(s) of Adiabatic Array Logic Propagatio Delay(s) of Adiabatic Array Logic Without redudacy Copyright to IJAREEIE DOI: /IJAREEIE

9 Frequecy of Siusoidal Power Supply (MHz) ISSN (Prit) : Dissipatio(μW ) of Adiabatic Array Logic Style Dissipatio (μw) of Adiabatic Array Logic Style Without redudacy Propagatio Delay(s) of Adiabatic Array Logic Propagatio Delay(s) of Adiabatic Array Logic Without redudacy TABLE III. PERCENTAGE CHANGE OF PARAMETERS OF PROPOSED DESIGN WITH RESPECT TO VARIOUS LOGIC STYLE FOR 4X1 MUX Parameter Adiabatic Array Logic CMOS logic Trasistor cout 0% Less 0% Less Area per chip(μm ) 0.09% Less 0.09% Less Dissipatio(μW) at 00 MHz 3.81% Less 45.51% Less Delay at 00MHz 0.78% Less 10.3% More TABLE IV. PERFORMANCE ANALYSIS OF ADIABATIC ARRAY LOGIC STYLE AND CMOS LOGIC STYLE FOR 8X1 MUX AND ADIABATIC ARRAY LOGIC WITHOUT REDUNDANCY Parameter Trasistor cout Adiabatic Array Logic Adiabatic Array Logic without Redudacy CMOS Logic Area per chip(μm ) Dissipatio(μW) at 00 MHz Copyright to IJAREEIE DOI: /IJAREEIE

10 Parameter Delay at 00MHz Adiabatic Array Logic Adiabatic Array Logic without Redudacy CMOS Logic TABLE V. Frequecy of Siusoidal Power Supply (MHz) 100 POWER DISSIPATION OF ADIABATIC ARRAY LOGIC STYLE AND PROPOSED ADIABATIC ARRAY LOGIC 8X1 MUX AT DIFFRENT FREQUENCY OF SINUSOIDAL POWER SUPPLY Dissipatio(μW) of Adiabatic Array Logic Style Dissipatio(μW) of Adiabatic Array Logic Style Without redudacy 7 Propagatio Delay(s) of Adiabatic Array Logic Propagatio Delay(s) of Adiabatic Array Logic Without redudacy TABLE VI. PERCENTAGE CHANGE OF PARAMETERS OF PROPOSED DESIGN WITH RESPECT TO VARIOUS LOGIC STYLE FOR 8X1 MUX Trasistor cout Parameter Area per chip(μm ) Adiabatic Array Logic CMOS logic % Less 45.45%Less 45.45% Less 45.45% Less Dissipatio(μW) at 00 MHz 0 % 10.17% Less Delay at 00MHz 0.01% Less 1.19% More VI.CONCLUSION I this paper, redudacy of the Adiabatic Array Logic is removed to achieve reduced power cosumptio ad propagatio delay. The proposed Adiabatic Array Logic has reduced o of trasistor cout i compariso with Adiabatic Array Logic ad covetioal CMOS Logic which has same umber o of trasistor cout. At higher Copyright to IJAREEIE DOI: /IJAREEIE

11 frequecy, these circuits dissipate larger power. Though the propagatio delays of these circuits are higher up to small cotet, these circuits are reliable with low frequecy. REFERENCES [1] Tomita.Y, Takahashi.Y, Sekie, T., "Adiabatic array logic," Sigals ad Electroic Systems (ICSES), 010 Iteratioal Coferece o, vol.o., pp. 69,7, 7-10 Sept [] Shruti Kowar, Thockchom Birjit Sigha, Soumik Roy, Power Efficiet Code Coverters Usig Adiabatic Array Logic, 014 Fourth Iteratioal Coferece of Emergig Applicatios of Iformatio Techology o pp , 19-1 Dec [3] Thockchom Birjit Sigha, Shruti Kowar, Soumik Roy, Low Power Desig ad Aalysis of Fudametal Logics Usig Adiabatic Array Logic Low Power Desig ad Aalysis of Fudametal Logics Usig Adiabatic Array Logic, 014 Iteratioal Coferece o Sigal Propagatio ad Computer Techology (ICSPCT) o pp ,1-13 Jul [4] Auar.N, Takahashi.Y, Sekie.T, "Two phase clocked adiabatic static CMOS logic," System-o-Chip, 009. Iteratioal Symposium o, vol., o., pp.083, 086, 5-7 Oct [5] Alioto, M.; Palumbo, G., "Power estimatio i adiabatic circuits: a simple ad accurate model," Very Large Scale Itegratio (VLSI) Systems. IEEE Trasactios o, vol.9, o.5, pp.608,615, Oct [6] William C. Athas, Lars J. Svesso, Jeffrey G. Koller, Nestoras Tzartzais, ad Eric Yig-Chi Chou, Low-Power Digital Systems based o Adiabatic switchig Priciples, IEEE Trasactios O Very Large Scale Itegratio (VLSI) Systems, VOL., NO. 4, Dec [7] A. K. Bakshi ad M. Sharma, "Desig of basic gates usig ECRL ad PFAL," 013 Iteratioal Coferece o Advaces i Computig, Commuicatios ad Iformatics (ICACCI), Mysore, 013, pp [8] Yog Moo ad Deog-Kyoo Jeog, "A efficiet charge recovery logic circuit," i IEEE Joural of Solid-State Circuits, vol. 31, o. 4, pp , Apr [9] M. L. Keote ad P. T. Karule, "Desig ad implemetatio of eergy efficiet Adiabatic ECRL ad basic gates," 015 Iteratioal Coferece o Soft Computig Techiques ad Implemetatios (ICSCTI), Faridabad, 015, pp [10] Aru Kumar, Maoj Sharma, Desig ad aalysis of MUX usig adiabatic techiques ECRL ad PFAL, Iteratioal Coferece o Advaces i Computig, Commuicatios ad Iformatics (ICACCI), pp , 013. [11] P. Bhati ad N. Z. Rizvi, "Adiabatic logic: A alterative approach to low power applicatio circuits," 016 Iteratioal Coferece o Electrical, Electroics, ad Optimizatio Techiques (ICEEOT), Cheai, Idia, 016, pp [1] A. K. Kumar, D. Somasudareswari, D. Duraisamy ad G. Sabariatha, "Asychroous desig of eergy efficiet full adder," 013 Iteratioal Coferece o Computer Commuicatio ad Iformatics, Coimbatore, 013, pp. 1-6 [13] Auar, N., Takahashi, Y., Sekie, T., "XOR evaluatio for 4 4-bit array two-phase clocked adiabatic static CMOS logic multiplier," Circuits ad Systems (MWSCAS), rd IEEE Iteratioal Midwest Symposium o, vol., o., pp.85,88, 1-4 Aug [14] Auar, N.Takahashi, Y. Sekie, T., "4-bit ripple carry adder usig two phase clocked adiabatic static CMOS logic," TENCON IEEE Regio 10 Coferece, vol., o., pp.1,6, 3-6 Ja [15] Leach Doald P., Digital Priciples ad Applicatios, Tata Mcgraw Hill Educatio Private Limited, 010 Editio. [16] Auar, N. ; Takahashi, Y.; Sekie, T., "Fudametal logics based o two phase clocked adiabatic static CMOS logic," Electroics, Circuits, ad Systems, 009. ICECS th IEEE Iteratioal Coferece o pp.503,506,13-16dec.009 Copyright to IJAREEIE DOI: /IJAREEIE