Ultra Low Power Wake-Up Receiver with Unique Node Addressing for Wireless Sensor Nodes

Transcription

1 Ultra Low Power Wake-Up Receiver with Uique Node Addressig for Wireless Sesor Nodes Travis Lee Cochra Thesis submitted to the faculty of the Virgiia Polytechic Istitute ad State Uiversity i partial fulfillmet of the requiremets for the degree of Master of Sciece I Electrical Egieerig Dog S. Ha, Chair Patrick Robert Schaumot Yalig Yag December 6 th, 2011 Blacksburg, VA Keywords: wake-up receiver, ultra-low power, wireless sesor etwork, serial code detector Copyright 2011 by Travis Lee Cochra

2 Ultra Low Power Wake-Up Receiver with Uique Node Addressig for Wireless Sesor Nodes Travis Lee Cochra (ABSTRACT) Power cosumptio ad battery life are of critical importace for medical implat devices. For this reaso, devices for Wireless Body Area Network (WBAN) applicatios must cosume very little power. To save power, it is desirable to tur off or put to sleep a device whe ot i use. However, a trasceiver, which is the most power hugry block of a wireless sesor ode, eeds to liste for the icomig sigal cotiuously. A alterative scheme, is to liste for the icomig sigal at a predetermied iteral, which saves power at the cost of icreased latecy. Aother ad more sophisticated scheme is to provide a wake-up receiver, which listes for the icomig sigal cotiuously, ad upo detectio of a icomig sigal, it wakes the primary trasceiver up. A wake-up receiver is typically simple ad dissipates little power to make the scheme useful. This thesis proposes a low-power wake-up receiver, which listes for a wake-up sigal, idetifies the target ode, ad wakes up the primary receiver oly whe that specific ode is called upo. Whe a wake up sigal is trasmitted to all of the odes o a etwork, our wake-up receiver allows all the odes o a etwork except the targeted ode to remai asleep to save power. Several wake-up receiver topologies have bee proposed. This work uses a passive Cockcroft-Walto multiplier circuit as a RF evelope detector followed by a simple detector circuit. A ovel serial code detector is the used to decode the pulse width modulated iput sigal to wake-up the desigated ode. A passive RF frot ed ad simple decodig circuit reduce power cosumptio substatially at the cost of low sesitivity. The

3 sesitivity of the wake-up receiver ca be improved though the additio of a RF amplifier, but at the cost of icreased power cosumptio. iii

4 Ackowledgemets I would like to thak all those who helped me get to where I am today. First I would like to thak my parets for all their love ad support ad always pushig me to excel i all my edeavors. I also wat to thak to my sister for always settig a great example. I thak Dr. Ha for his guidace ad metorship as my advisor. I have grow as a egieer ad a perso uder his tutelage ad through my research, projects ad writigs. My time as a member of the Virgiia Tech VLSI for Telecommuicatios Lab will be the foudatio of the rest of my career. I would like to thak my committee members Dr. Patrick Schaumot ad Dr. Yalig Yag for their time ad their iterest i my research. I would also like to thak all of the members of the VTVT lab who I ve worked with other the past two year. Namely, Justi Cartwright, Na Kog, Jeogki Kim, Jihoo Jeog, Jisik, Yu, Joh Turer, Shaver Deyerle, Carlos Qeumada, ad Jebreel Salem. iv

5 Cotets 1. Itroductio Backgroud Wake-Up Receivers About Wake-Up Receivers Key Techical Problems Wake-Up Receiver Topologies FSK Wake-up Receivers Evelop Detectio Wake-up Receivers Idetificatio of Nodes to Wake up Architecture ad Operatio of the Proposed Wake-Up Receiver Matchig Circuit ad Multiplier Sigal Decodig Block Operatio Commuicatios Protocol Wake-Up ID Packet Structure System Level Desig Costraits Desig of Proposed System Discussio of Techology Matchig Network Cockcroft-Walto Multiplier Over Voltage protectio DC Detector Circuit Serial Code Detector Delay Buffer Desig Pass-Gate Flip-Flop Desig Combiatioal Logic ad Node ID storage Circuit Simulatios Trasiet Aalysis Power Aalysis Future Work v

6 7. Coclusio Works Cited vi

7 List of Figures Figure 1: Wireless Boady Area Network... 1 Figure 2: Super Hederodye Wake-Up Receiver... 8 Figure 3: IF Evelope Detectio Figure 4: Three BAW's coected to a Die Figure 5: Cockcroft-Walto Wake-Up Circuit Figure 6: Diagram of Wake-Up Receiver with Microprocessor Figure 7: RF Evelope Detector with base bad amplificatio Figure 8: Proposed Sigal Chai Figure 9: Cockcroft-Walto Multiplier Operatio Figure 10: Passive RF frot ed Figure 11: Low Power Serial Code Detector Circuit Figure 12: Log ad Short Pulses Detected Figure 13: Clock Sigal Geeratio Figure 14: Restricted Node ID's Figure 15: Sample Wake-Up Packet Figure 16: System Schematic i Cadece Figure 17: Multiplier Circuit S-Parameters Figure 18: Pi Match Schematic Figure 19: S11 of Multiplier circuit with Matchig Network Figure 20: Matchig Network with ad without iductor resistace Figure 21: S21 of Impedace Matchig Network Figure 22: Cockcroft-Walto Multiplier Schematic Figure 23: Over Voltage Protectio Circuit Figure 24: Over-Voltage Protectio Kickig i at 1.6V Figure 25: DC Detector Schematic Figure 26: Serial Code Detector Schematic Figure 27: Delay Buffer Stage Schematic Figure 28: Pass Gate Flip Flop Schematic Figure 29: Trasiet Simulatio Figure 30: Pulse Width Modulated Sigal ad Delayed Copy Figure 31: Flip Flop Output Figure 32: Trasiet Power Cosumptio whe receivig a message.41 Figure 33: Compariso of Wake-Up Receivers Performace vii

8 List of Tables Table 1: Power Cosumptio of Decodig Blocks Table 2: Compariso with other Desigs viii

9 1. Itroductio Wireless body area etworks (WBANs) are expected to make sweepig chages i the medical field as well as may other applicatios [5]. The Wireless Body Area Network (WBAN) draft stadard, IEEE Draft , is beig developed for the commuicatio of wireless devices about your perso for medical, athletic, ad multimedia applicatios. The etwork cosists of a cetral hub, which commuicates with wireless devices withi a 2 meter rage. These devices ca iclude medically implated sesors/devices such as pacemakers, blood glucose sesors, ad blood pressure sesors, wearable sesors such as pedometers, ad ehaced reality or multimedia devices. The etwork protocol is also desig to commuicate with exteral wireless iterfaces, which ca be added to the etwork or relayed to through a exteral hub. These devices ca iclude a electroic doctor s chart to read your medical sesor data, a wireless smart home system, ad may other applicatios. Figure 1: Wireless Boady Area Network [1] Used uder fair use guidelies,

10 The wireless sesors o the etwork should have as log a battery life as possible to reduce frequecy batteries eed to be replaced. This ca be achieved through low power desig ad eergy scavegig. Surgically implated medical sesors are especially critical sice replacig the battery may require additioal surgery. It may be possible to recharge some of these sesors iductively but extedig the battery life through low power desig allows for less iteractio by the user. WBAN devices should be able to ru off of small batteries or eergy scaveged from the ambiet eviromet, allowig them to be implatable or wearable for medical applicatios. The power cosumptio of a WBAN device is of critical importace ad poses sigificat desig challeges. Frequet battery rechargig or replacemet of implated sesors etails surgical operatios ad possible exposure to harmful ifectios. Therefore, a advaced power maagemet scheme is required to prolog the battery life ad icrease the lifespa of WBAN devices. The RF frot-ed of a wireless device is resposible for major power dissipatio i the system, ad it is particularly true for small wireless devices i WBANs, where data commuicatio occurs for a short period of time. Reducig power cosumptio of the RF frot-ed while the ode is idle is very importat. Duty cyclig is a popular wake-up scheme [6]. WBAN odes sleep i a idle state most of the time, while wakig up at the predefied time to commuicate with the host. This approach ca reduce the amout of eergy used by exploitig the iheret low frequecy chages characteristic of biomedical iformatio. However, the low duty cycle results i icreased latecy i commuicatio. Moreover, WBAN devices still wake up eve if there is o data to trasmit or receive, which results i redudat eergy dissipatio. This thesis presets a wake-up receiver, which targets for the 2.4 GHz ISM bad although the mai trasceiver is likely to operate i the MHz medical implat commuicatio service (MICS) bad. The wake-up receiver ca operate i whichever bad is allocated for the target applicatio with little 2

11 modificatio. The proposed wake-up receiver cosists of a carrier sesig circuit ad a serial code detector. The carrier sesig circuit is implemeted with passive elemets ad is triggered by radio eergy to miimize power dissipatio. Meawhile, the code detector decodes the received sigal ad geerates a asychroous iterrupt sigal to the mai processor ad trasceiver whe the ode is called upo, thus eablig the mai trasceiver to react quickly. We propose a simple protocol to support the proposed asychroous wake-up receiver. The mai cotributio of this thesis is combiig a low power wake-up receiver frot ed with a serial code detectio circuit which ca decode the pulse width modulated iformatio from the carrier. This decoded ode ID is compared to each ode s assiged ID ad a iterrupt is geerated at the target ode to wake the processor ad mai RF trasceiver. For other proposed wake-up receivers the processor has to wake o every ode to decode the icomig packets, wastig power ad lowerig the wireless odes battery life. This thesis is orgaized as follows: Chapter 2 provides the backgroud for wake-up receivers with special cosideratio for WBAN s ad differet power savig techiques for wireless sesor etworks. This icludes both MAC layer power savigs as well as differet wake-up receiver desigs. Several geeral types of wake-up receivers are discussed with specific examples give ad aalyzed. Chapter 3 covers the architecture of the proposed wake-up receiver with system level desig costraits ad cocers. Several possible desig tradeoffs are discussed which would allow the performace of the proposed desig to be tailored for a specific applicatio. Chapter 4 goes ito the details of this wake-up receiver desig. The desig of each block i the sigal chai is discussed ad aalyzed, startig with the iput at the atea, through a matchig etwork, the Cockcroft-Walto multiplier, ad the DC detector. Followed by the 3

12 serial code detector ad the desig of its compoets, e.g. the pass gate flip flops ad delay buffer. I Chapter 5, the simulatio results of the proposed wake-up receiver are aalyzed. These results are compared to other recetly published wake-up receiver desigs to illustrate the tradeoffs betwee the desig primarily with regards to power cosumptio, sesitivity, ad bit rate. I Chapter 6, the future plas for this work are discussed to see this desig fabricated ad tested to verify the simulatios as well as possible improvemets. I Chapter 7, we coclude this thesis by summarizig the beefits ad uique features of the proposed wake-up receiver. 4

13 2. Backgroud This chapter provides the backgroud for wake-up receivers with special cosideratio for WBAN s ad differet power savig techiques for wireless sesor etworks. This icludes both MAC layer power savigs as well as differet wake-up receiver desigs. Several geeral types of wake-up receivers ad their topologies are discussed with specific examples give ad aalyzed. 2.1 Wake-Up Receivers The primary purpose of a wake-up receiver is to lower the power cosumptio of the primary trasceiver for wireless sesor etworks. A wake-up receiver should dissipate low power, typically less tha 100µW. The required data rate of a wake-up receiver is much lower tha that for the primary trasceiver. The RF sesitivity is also aroud 30dB less tha that of primary receivers [1] About Wake-Up Receivers A wake-up receiver eables a wireless sesor etwork to save power by turig off the mai trasceiver uless it is eeded. There are two mai power savig optios provided i the draft stadard for Wireless Body Area Networks (WBANs), IEEE Draft [2]. The first techique is the use of Beaco Periods, i which the hub assigs each etwork ode a specific time slot to commuicate with the hub. The ode also has the optio to sleep for a umber of beaco periods before wakig up to trasmit the data or to simply sychroize with the hub ad retur to sleep [3]. This MAC layer power savig optio allows for the ode to sleep, turig off its trasceiver ad other system compoets util the ext scheduled beaco period. A major shortcomig of this optio is latecy. If the odes are sleepig through may beaco periods before commuicatig, the latecy ca be large. The log latecy is udesirable for medical applicatios such as the oes for WBANs. To set the time to wake up ad commuicate with a beaco period, the wireless ode must have a accurate clock ruig. Also the 5

14 accuracy of the timer determies how log a ode ca sleep through beaco periods ad correctly wakes up withi its predetermied time slot to avoid overlap the commuicatios with followig odes. The secod power savig optio comes from the physical layer through the adoptio of a wakeup receiver. If a ode o the etwork idicates that it has a wake-up receiver, the hub requests the specific ode via the wake-up receiver ad the commuicates with the ode oce the mai trasceiver is powered up. This optio icurs low latecy compared with sleepig through may beaco periods. The wake-up receiver latecy is oly limited by the bit rate (which is usually low) of the wake-up receiver ad the wake-up time of the RF trasceiver ad the processor. This optio does ot eed a digital clock ad a timer, although the additio of the wake-up receiver will cosume more power tha the mai trasceiver aloe Key Techical Problems Miimizig the power cosumptio is a major cocer for ay wake-up receiver desig. However, lowerig the power cosumptio usually results i decrease of the iput sesitivity, which decreases the rage ad icreases the BER (bit error rate). Also sice a wake-up receiver is supplemetal to the mai RF trasceiver, its footprit should be miimized, so its cost does ot outweigh the power savigs. 2.2 Wake-Up Receiver Topologies There are two major commuicatio schemes used for wake-up receivers, which are discussed below with their respective topologies. First there are FSK wake-up receivers which ecode the packet data i frequecy variatio. These are usually more complex but higher performig tha other desigs. Typically super-heterodye or super-regeerative receiver topologies are used. The other mai commuicatio scheme uses simple o-off keyig ad evelope detectio i the receiver. These receivers ca use a mixer to brig the icomig sigal dow to basebad or do the evelope detectio 6

15 at high frequecy. The Cockcroft-Walto multiplier is a commoly used circuit for high frequecy evelope detectio. There are may proposed topologies for wake-up receivers. Two primary modulatio schemes, o-off keyig (OOK) ad frequecy-shift keyig (FSK), are commoly used due to their simplicity for demodulatio, ad the simplicity allows for low power cosumptio [4]. However, these modulatio schemes provides low data rates compared with more sophisticated codig schemes, but a high data is ot required for a wake-up receiver FSK Wake-up Receivers A FSK receiver is less sesitive to path loss tha a evelope detector ad is iheretly more liear. The RF carrier of a super-heterodye FSK receiver is dow-coverted to a itermediate frequecy (IF), which mitigates adverse effects of parasitics. Further, a IF amplifier cosumes less power tha a RF amplifier due to a lower operatig frequecy. Figure 2 shows a super-heterodye receiver which mixes i icidet sigal with two sigals 90 degrees out of phase with each other, yieldig a I ad Q sigal at low frequecy, which are the amplified. A super-heterodye FSK wake-up receiver ca achieve a reasoably high data rate usig both the I ad Q chael, ad high sesitivity but at the cost of high power cosumptio. The local oscillator (LO) of a super-heterodye FSK wake-up receiver cosumes a lot of power i this topology. For example, the FSK wake-up receiver i [2] achieves 50 kbps ad -65 dbm, but cosumes 126, which is quite high. 7

16 Figure 2: Super Hederodye Wake-Up Receiver [5] Used uder fair use guidelies, Super regeerative receivers, first proposed by Armstrog back i 1922, are also applied for FSK wake-up receivers. Super regeerative receivers achieve high gai ad low power cosumptio, as they operate ear the threshold of istability. Negative feedback i the form of a quechig circuit is ofte used to keep the amplifier stable. A super regeerative receiver ca also be used for evelope detectio [5] Evelop Detectio Wake-up Receivers Evelope detectio is popular for wake-up receivers due to its simplicity. A simple evelope detector receiver is composed of a diode rectifier followed by a low pass filter. Such a simple receiver has very low sesitivity. Two approaches have bee used to boost the sesitivity, dow-mixig with low frequecy amplificatio ad voltage multipliers, both illustrated below Itermediate Frequecy Evelope Detectio 8

17 There are several proposed wake-up receiver desigs which mix the RF sigal dow to a itermediate frequecy before the evelop detector. Figure 3 uses a local oscillator (LO) ad a mixer to covert the icomig RF sigal dow to IF. The lower frequecy sigal is the amplified before passig through a evelope detector geeratig a basebad sigal. The basebad packet data is decoded by the processor to determie if the ode is goig to wake up. The beefit of this desig is that to achieve the same receiver sesitivity, the IF amplifier dissipates less power tha a RF amplifier [4]. However, the LO required for the super-heterodye topology is power hugry. Oe uique approach is to use a rig oscillator with a ukow exact frequecy [6] istead of a traditioal LC oscillator. A rig oscillator dissipates less power tha a LC oscillator, but its frequecy is depedet o process ad temperature variatio which causes the IF to vary. This would be a problem for a fixed IF architecture, but the exact frequecy of the IF is irrelevat for the evelop detector. This architecture achieves a sesitivity of -72 dbm at 100 kbps with a power cosumptio of 52 µw [6]. A similar desig achieves -87 dbm at 250kbps for 83µW of power cosumptio [7]. Oe caveat of this desig is that the iput filter has to have a high Q to reject adjacet chaels due to the widebad amplificatio which would amplify other earby sigals which were mixed dow ear the IF. 9

18 Figure 3: IF Evelope Detectio [7] Used uder fair use guidelies, Aother approach which has bee proposed is to duty cycle the operatio of the wake-up receiver such that it effectively samples the chael every bit period for the wake-up sigal [8]. By duty cyclig the operatio of the wake-up receiver the effective power cosumptio ca be reduced ad the latecy will ot be icreased sigificatly as log as the duty cycle period is short. Oce a iitial wakeup preamble (1kbps) is detected the wake-up receiver ca stay active to decode the icomig packet at a higher data rate of 200kbps before returig to the duty cyclig operatio. I [9] a dow samplig clock is used to covert the sigal to a IF before amplifyig ad digitizig the sigal. A Clock Harvestig GSM circuit is used as a wake-up receiver i [10] uses both a LNA before a mixer as well as several IF amplifier stages after the mixer to achieve a sesitivity of -87dBm although the umber of amplifiers yields a high power cosumptio of 126µW. This desig like several other evelope detectors uses a Surface Acoustic Wave (SAW) resoator to achieve high selectivity o the 10

19 iput [11]. This allows for out of bad sigals to be filtered out before the mixer ad evelope detector. Both SAW s ad thi-film bulk acoustic resoators (FBAR or BAW) are useful for high Q RF filters ad have a smaller form factor tha crystal filters or off chip LC filters. Because of their small size, a BAW ca be implemeted i the same package as the IC die ad coected through wire bods [12]. Figure 4: Three BAW's coected to a Die [13] Used uder fair use guidelies, High Frequecy Evelope Detectio A amplificatio of a RF sigal is ofte eeded for the evelope detectio. Istead of usig a RF amplifier (which dissipates power), it ca be accomplished with a voltage multiplier like a Cockcroft- 11

20 Walto circuit [13]. The Cockcroft-Walto Multiplier was first developed for geeratig large DC voltages for particle physics experimets i 1922 by Joh Cockcroft ad Erest Walto. Although desiged for high power applicatios this circuit is also useful for low power circuits as well. Fuctioally the Cockcroft-Walto multiplier works o the same priciple as a voltage doubler, just with some umber of stages stacked i series. The modelig of this multiplier circuit at UHF [14] shows the maximum sesitivity of the receiver with the multiplier circuit to be -32dBm [14]. Figure 5 shows a circuit diagram of their work. From the atea i they have a power matchig etwork to esure maximum power trasfer of the received RF sigal. Next they have a N stage Cockcroft-Walto voltage multiplier. The DC output voltage of this circuit is ideally 2N times larger tha the peak to peak iput RF voltage. However, there are losses i the diodes which prevet this. Their work iteds to geerate a 1 V output. If the output voltage ca be detected as a smaller voltage, the the sesitivity could be improved. The circuit has also bee applied for supplyig the operatig power for very low power applicatios such as RFID [15]. Figure 5: Cockcroft-Walto Wake-Up Circuit [17] Used uder fair use guidelies,

21 2.3 Idetificatio of Nodes to Wake up Existig wake-up receiver desigs based o the Cockcroft-Walto Multiplier have a similar sigal chai from the atea through the multiplier, ad ito some sort of detector with a digital output. However, the output of the detector is used i differet ways. Most commoly a microprocessor is used to read the output of the detector. This output has bee used directly as a iterrupt [16], but this requires every wake-up receiver o the etwork to wake the processor whe the carrier is detected o a predetermied chael. It also requires each processor to stay active for the decodig of the etire of the wake-up packet to decode the icomig OOK message [17]. Simply usig the wake-up receiver as a carrier detectio circuit also requires that a chael is dedicated to wake-up commuicatio oly, limitig the chaels available for the active odes to use for commuicatio. Aother approach proposed has bee to use multiple multiplier circuits i parallel; each iput filtered to receiver a differet frequecy [18]. Usig this method the presece or absece of the carrier at each frequecy ca be used idetify the specific ode the hub is tryig to wake-up. This has the beefit or oly wakig a sigle ode o the etwork ad ot all, savig power. The uused wake-up chaels ca possibly be used for data commuicatios with possibility of accidetally wakig up other odes. However, this system requires a larger footprit o the die. As the umber of odes o the etwork grows the umber of multiplier circuits eeded icreases as where: The use multiple chaels i the bad to wake a sigle ode o the etwork is also a very iefficiet use of the available RF spectrum. 13

22 Usig the processor o the ode to decode the icomig sigal for ode addressig removes the eed for a dedicated wake-up chael ad/or havig multiple multipliers. The processor iput is still used as a iterrupt but after the processor is active, it ca decode the icomig sigal either usig ooff keyig (OOK) or pulse width modulatio (PWM). The mai drawback of this system is that the processor for every ode i the etwork has to wake up ad decode each wake-up sigal o the etwork as well as false wake ups whe the carrier for a ormal packet is detected i the same chael. Sice it will oly stay awake ad perform the requested fuctio if it correctly reads the ID for that specific ode this does ot hurt the operatio of the system. Istead the costat use of the processor wastes power uecessarily. I several papers discrete microcotrollers have bee used to this ed. For a TI MSP430 which is a low power processor, the power cosumptio chages from 440W to aroud 1mW whe switchig to active operatio [19]. The wake-up receiver proposed i this thesis attempts to address these problems. The proposed receiver has a simple ad dedicated decoder for idetificatio of odes, which decodes the wake-up packet received ad wakes up oly the desigated ode. Figure 6: Diagram of Wake-Up Receiver with Microprocessor Aother issue with the multiplier circuit is that it has widebad operatio. This requires the Q of the iitial filter to be sufficietly high such that the adjacet chaels ot beig used to wake-up sigals are filtered out. Due to the limitatios for the Q of o chip iductors, it has bee proposed to use a BAW 14

23 [6] to achieve a high Q iput filter for RFIC desigs. A BAW ca have a Q from several thousad to several millio, allowig for a very arrow bad filter to be created. Figure 7: RF Evelope Detector with base bad amplificatio [12] Used uder fair use guidelies,

24 3. Architecture ad Operatio of the Proposed Wake-Up Receiver The proposed architecture for this wake up receiver combies the use of a carrier detectio circuit ad the proposed Serial Code Detector to read data from the carrier. Followig the sigal path from the atea, there is a matchig etwork ad filter for maximum power trasfer ad to filter out adjacet chaels. Next i the sigal path is a Cockcroft-Walto multiplier which works like a charge pump to create a DC voltage from the received RF sigal [20] [21] [22]. After the multiplier, there is a overvoltage circuit to prevet the DC voltage o the output of the multiplier from risig to levels where it could damage the system. A DC detector circuit geerates a digital output from the carrier pulses received ad coverted to DC pulses. The serial code detector allows for pulse width modulated data to be read from the carrier without ay form of sychroizatio. The serial code detector the geerates a iterrupt to wake the ode s processor ad mai RF block to respod to the wake-up sigal as eeded. Figure 8: Proposed Sigal Chai 3.1 Matchig Circuit ad Multiplier The matchig circuit coectig the atea to the rest of the circuit serves two fuctios. First it matches the iput impedace of the multiplier to the atea. This provides maximum power trasfer of the received sigal. Secodly the matchig circuit filters out other frequecy bads so oly the carrier i the chael desigated for wake up sigals will be detected. For adjacet chaels to be filtered out 16

25 the Q of the matchig circuit must be sufficietly high. For wide chael spacig the LC etwork used is adequate but if the applicatio requires the chaels to be closely spaced a better filter will be required. Next i the sigal chai a Cockcroft-Walto multiplier, costructed of N stages where each stage doubles the output voltage of the circuit. However, for large umbers of stages, losses from the capacitors i each stage, especially ear the iput cause the output voltage to sag. A sigle stage of the multiplier is show i Figure 2.a. Whe the polarity of the iput voltage is egative, a curret is coducted through D2, chargig up the capacitor C2. The whe the polarity of the iput chages the charge o C2 coducts through D1 to charge C1. The voltage o the iput plus the voltage across C2 yields twice i iput voltage o C1 for 10 V i this case, as a voltage doubler should operate. The operatio of this multiplier is the same as additioal stages are added, allowig for the iput to be multiplied to a large voltage. C2 C2 - + C2 - + AC C1 AC - + 5V I AC + 5V - 5V I 10V + - C1 Figure 9: Cockcroft-Walto Multiplier Operatio Up till this part i the circuit all of the circuit elemets are passive [4]. This meas that there is o active curret or leakage curret for the RF frot ed of the receiver. Amog several DC sesig circuits proposed so far [1] [6][7][8][10], the most basic desig is a series of iverters, which yields a digital output. The iverter i [2] has a sesitivity of aroud -30 dbm ad a static curret cosumptio of 2.6 µa. The power cosumptio sesitivity level of -72 dbm with 52 µw power cosumptio has bee achieved 17

26 o chip at the cost of icreased complexity [10]. A discrete comparator was used for -65 dbm with 2.8 µw [6]. A itegrated solutio i [7] has a sesitivity of -31 dbm with a curret of oly 900 A. Figure 10: Passive RF Frot Ed 3.2 Sigal Decodig Block To determie if the received wake-up packet is addressed for the wireless ode the packet must be decoded ad the ode ID compared to the odes uique ID o the etwork. All of the wake-up receivers previously aalyzed, the packet data is simply set to a processor to be checked agaist the ode ID. This requires a processor i every sesor ode o the etwork to wake to check the ID before returig to sleep. By comparig the received ID to the ode s ID, oly the processor o the requested ode is woke up Operatio The mai cotributio of this paper is the combiatio of the carrier detectio circuit ad a ode idetificatio circuit as described i the followig. The digital data from the DC detector circuit is applied ito a pipelie of f D flops as show i Figure 4, where f is the umber of bits eeded to uiquely idetify each ode o a WBAN. Because there is o clock sigal, the iput from the DC detector is delayed through a series of buffers before its risig edge ca trigger the flip flops. The delay of these buffers is sigificat ad will be discussed later i more detail. Oce the data i the flip-flops matches a preset 18

27 idetifier i a register, or some other memory device, a iterrupt is set to the ode processor, which resets the pipelied flip-flops, ad turs o the primary trasmitter ad receiver. It ca the respod to the hubs wake up request, ad hadle ay ecessary tasks before disablig the primary receiver ad returig to sleep. Figure 11: Low Power Serial Code Detector Circuit A typical scheme for timig is established through a alteratig sequece such as at the preamble of the message, which is used to sychroize the receiver. The scheme is widely used, but requires a level of sophisticatio beyod what is eeded for a simple wake-up receiver. Other methods such as pulse iterval ecodig have bee proposed [1], but require a costat clock to determie the legth of these itervals. Istead, we propose adoptio of pulse width ecodig to differetiate betwee logical oe ad zero. The differet widths are used such that the delay is loger tha the short pulse (logical 0), but shorter tha the log pulse (logical 1). This meas that whe the flip-flop reads the iput after time delay, a log pulse keeps the iput high, but the short pulse has goe low already. This scheme allows for a biary message to be received by the receiver without sychroizatio or usig a timer. 19

28 The timig diagram i Figure 5 shows the carrier pulses chargig up the RF frot ed ad the resultat output of the DC detector. Note that the setup ad hold time of the flip-flops is short compared to the pulse widths ad time delay. Figure 6 shows clock sigal geeratio, where the iput sigal is delayed through a buffer chai to create the clock sigal. Figure 12: Log ad Short Pulses Detected Figure 13: Clock Sigal Geeratio 20

29 3.2.2 Commuicatios Protocol Oe difficulty with the proposed system is that the stregth of the carrier sigal decreases with as the receiver moves away from the trasmitter. Although the distace i a WBAN should ot exceed two meters [5], this still affects the received power. A wake-up receiver closer to the trasmitter charges its voltage multiplier more rapidly, yieldig loger pulse widths for both the short ad log pulses. Likewise a receiver far from the trasmitter has shorter pulses. To solve this problem, we propose that the iitial wake up sigal set from the hub uses the miimum power ad carrier pulse width. If the hub receives o respose from the ode, the it successively icreases the trasmissio power or pulse width util a respose is received from the ode. Iitially all of the pulses should be relatively short causig the circuit i Figure 3 to read all zeros. As the pulse width icreases i steps less tha, the correct ode reaches the threshold, where the log ad short pulses are read correctly as oes ad zeros regardless of its proximity to the trasmitter. If the icrease i the pulse width is larger tha, there is a possibility of readig all zeros ad the all oes i two successive messages ad ot correctly receivig the actual sigal. If the rage of the etwork is exteded further, this problem becomes more proouced, ad the latecy of the system icreases as the system takes loger to sweep the etire pulse widths. Two solutios are possible to this problem. First, the hub ca remember the required pulse width of the target ode at the last trasmissio ad starts from oly a slightly smaller width tha the required oe. Assumig that the path to that ode does ot chage dramatically betwee two successive wake-ups it should oly take several tries to wake the ode startig from mius oe or two pulse widths from the previous message. Secodly, two or more serial code detectors are implemeted i parallel receivig data from the same DC detector, effectively dividig up the search space. Each detector should have a differet buffer delay, ad, which allows for the correct pulse width to be foud more rapidly, reducig the latecy 21

30 3.2.3 Wake-Up ID Packet Structure The wake-up ID packet should be as simple as possible to keep the legth of the packet small. At a miimum, the packet must cosist of a header, ad the ID of the ode which is beig requested by the hub. The header is to esure that the full packet has bee decoded by the serial code detector ad ot half a packet beig shifted i or out. The cotets of the header must be reserved, ad ot duplicated i the rest of the packet. Otherwise whe a ew packet was beig received, it would shift to the head of the packet, ad cause a uecessary wake-up. As see i Figure 14, for the header 1001, the ode ID for every ode o the etwork caot start with 001, or ed with xxxxx x-forbidde, header repeats i packet Xxxxxx xxxxx forbidde previous packet causes header to repeat Figure 14: Restricted Node ID's The heart of the packet is the ode ID. The legth of the ode ID is determied by the maximum umbers of odes o the etwork where ( ) ( ) is the maximum umber of odes o the etwork for bits i the ID. The ( ) term removes all of the restricted ID s startig with 001 or edig with 100 for the header value of 1001 to prevet uecessary wake-ups. To remove ay ID s which cotai the header withi itself the ( ) term is added. Figure 15 illustrates the packet structure with the preamble, ode ID, ad potetially a parity bit for error checkig. 22

31 Preamble 100 Node ID Parity Bit Figure 15: Sample Wake-Up Packet System Level Desig Costraits There are several desig costrais o a wake-up receiver for it to be practical for use i a real applicatio. First the sesitivity of the receiver must be high eough that the sigal ca be recovered with the give source trasmit power ad maximum path loss. This may also iclude path losses through body tissue i the case of medical implat devices which will atteuate the sigal more tha free space. Aother costrait pertais to the chael used for the wake-up sigals ad the data packets o the same chael ad/or adjoiig chaels. The wake-up packet is usually set at a slower rate, 1kbps- 100kbps, tha the data packets which ca be trasmitted at 10Mbps [23]. If the frequecy selectivity o the iput of the wake-up receiver is low, the the data packets from the adjoiig chael may cause eough oise to corrupt the wake-up packet. If there is error checkig i the wake-up packets such as a parity bit this will help prevet uecessary wake-ups but it will icrease the latecy of the wake-up packets have to be sed repeatedly. The latecy of the system must also be low eough for the wake-up receiver to outperform duty-cyclig of the mai processor for the same power savigs. For the power savigs to be equal betwee duty-cycled operatio ad a ultra-low power wake-up receiver, the duty cycle period will have to be loger tha the latecy of the wake-up receiver. The system ca wake quickly oce the wakeup packet is decoded, o the order of several microsecods [24]. The latecy of the system may be costraied for the give applicatio but this ca be traded for power cosumptio by usig a differet wake-up receiver topology. 23

32 4. Desig of Proposed System The desig of the proposed wake up receiver will be discussed startig from the receivig atea ad matchig etwork ad the follow the sigal path through the multiplier circuit, DC detector, ad serial code detector. RF Atea Cockcroft-Walto Multiplier DC Detector Serial Code Detector Iterrupt to Processor Node ID Figure 16: System Schematic 4.1 Discussio of Techology For this desig the Natioal Semicoductor 180m process has bee used although this process lacks Schottky diodes which are preferable for this desig. Istead diode coected NMOS FET trasistors are used for the Cockcroft-Walto multiplier. The desig was simulated with a off chip iductor for a higher Q although a o chip iductor could be used. 24

33 4.2Matchig Network The atea s 50 Ohm impedace eeds to be matched to the iput impedace of the Cockcroft-Walto Multiplier for maximum power trasfer. For this to be doe the iput impedace of the multiplier must first be foud by measurig the S-Parameters. Figure 17: Multiplier Circuit S-Parameters These measuremets are the used to calculate the iput reflectio coefficiet. 25

34 Where With the iput reflectio coefficiet the iput impedace ca easily be foud usig the ormalized impedace of 50 Ohms. For this applicatio a relatively high Q is desired for the matchig etwork to filter out ay adjacet chaels so oly the target carrier frequecy will charge the multiplier circuit. A π match is used to allow for cotrol of the Q. The value of each compoet ca be foud from the followig equatios where X3 is a iductor ad the rest are capacitors. [ ] 26

35 Figure 18: Pi Match Schematic Figure 19: S11 of Multiplier circuit with Matchig Network 27

36 This provides a good match at the target frequecy with a s11 of -46dB at 2.4GHz. However, this is for a ideal iductor. Assumig the Q of the iductor is 100, which is more practical of a off chip iductor, we get a s11 of -10dB. This is still a reasoable match ad ca be see i Figure 20 compared to the lossless iductor. Figure 20: Matchig Network with ad without iductor resistace The additio of the iductor resistace also turs this matchig etwork ito a lossy etwork as see by the s21 i Figure 21. The etwork was simulated to have a loss of 2.5dB at 2.4 GHz. If the iductor was implemeted with a low Q o chip spiral iductor this loss would be higher. If available a high Q 28

37 filter could be implemeted with a acoustic resoator. This could be implemeted i the same package ad coected by bod wires as i [6]. Figure 21: S21 of Impedace Matchig Network 4.3 Cockcroft-Walto Multiplier Evelope detectors are a well-kow circuit for receivig AM sigals. The simplicity of such circuits makes them desirable for low power wireless applicatios. A Cockcroft-Walto multiplier circuit, show i Figure 22, eables a carrier to be detected by chargig up a DC voltage whe receivig a AC sigal. This works like a evelope detector if the iformatio i the carriers trasitios slowly 29

38 compared to the charge time of the multiplier circuit with the beefit of ot eedig active amplificatio. Iput 1 pf 1 pf 1 pf 1 pf 1 pf 1 pf 1 pf 1 pf 1 pf 1 pf 1 pf 1 pf Output Figure 22: Cockcroft-Walto Multiplier Schematic The output voltage of the multiplier circuit is a fuctio of the umber of stages ad the voltage drop of each stage. This ca be estimated by followig equatio eglectig losses. The voltage drop is also depedet o the load curret ad ca be calculated as. [ ] ( ) Where C is the stage capacitace, f is the AC frequecy, ad is curret through the load. The DC output will also have a AC ripple which is fed through from the iput. This ripple ca be calculated as [ ] ( ) be. For a iput of 0.2 volts peak to peak ad 6 stages the output voltage of our multiplier should [ ] ( ) 30

39 This matches closely to the simulatio results show i the ext sectio. A more accurate model for a Cockcroft-Walto Multiplier show below is give i [20]. This model takes ito accout the diode characteristics ad uses Bessel ad the Lambert W fuctios if a precise aalytical solutio is eeded but for desig purposes it is more efficiet to use the simple model above ad the tue the desig usig a CAD simulatio package. ( ( ) ) More stages ca be added to the multiplier to icrease the gai for better sesitivity. However, the losses from the diodes icrease with the umber of staged with a cubed ad a squared term for dimiishig returs. Also icreasig the umber of stages icreases the desig cost as the size of the receiver o the die will icrease. 4.4 Over Voltage protectio. The DC output of the multiplier is depedet o the umber of stages i the multiplier, but also the RF power level. The sesitivity of the receiver is low compared to active receiver desigs, ad a iput of -10dBm is required to geerate a DC voltage of several hudred millivolts where it ca be detected by the rest of the circuit. However, if the RF power is large the DC output could easily reach a voltage where it could damage compoets. This is ot surprisig, sice the origial applicatio for the Cockcroft-Walto Multiplier was to geerate kilovolt DC levels for particle physics experimets. To prevet high voltages from damagig the circuit, over voltage protectio is icluded to bleed off curret whe the voltage surpasses a set threshold. The simplest desig is a diode to groud. Whe 31

40 the voltage reaches the threshold voltage for the diode it will begi to coduct curret, keepig the voltage at safe levels. However, the tur o voltage of a sigle diode is low (~0.7V), so several diodes ca be coected i series to raise the voltage at which all of the diodes begi to coduct. I additio to bleed off curret faster the odes betwee those diodes ca be used to tur o NMOS FETS coected to groud. Iput 20 kω 1 pf u Output 20 kω u u Figure 23: Over Voltage Protectio Circuit 32

41 Figure 24: Over-Voltage Protectio Kickig i at 1.6V 4.5 DC Detector Circuit The DC Detector circuit is eeded to detect whe the output voltage of the multiplier circuit reaches a certai threshold. Because the RF power received by the atea is ukow, it is difficult to predict what the voltage o the output of the multiplier circuit will charge too. To improve the sesitivity of the receiver the DC detector s threshold is set to 0.1 V. The figure below shows the schematic for the DC detector with a iverter followig for a active high output. The sectio of the circuit iside the box is a beta multiplier which is used to geerate the bias voltages for the PMOS loads for the two iverter stages. I a fully itegrated desig these bias voltages may available from a global voltage bias to reduce power cosumptio. 33

42 Curret Source Beta Multiplier Bias Circuit Ω Figure 25: DC Detector Schematic 4.6 Serial Code Detector The serial code detector decodes the wake up ID for the wireless sesor ode from the pulse width modulated sigal. This detector cosists of three compoets. A buffer chai to delay the iput sigal, a series of D-flip flops to store each bit i the packet, ad the combiatioal logic to compare the cotets of the flip flop to the ode s ID. 34

43 Figure 26: Serial Code Detector Schematic Delay Buffer Desig The delay of the buffer chai must be larger tha the short pulse,, while shorter tha the log pulse,. To achieve this log delay the capacitace is icreased betwee the two iverters of each buffer stage. This is accomplished addig a capacitor after each iverter, icreasig the parasitic delay. Lowerig the drive of the first iverter also icreases the delay of the buffer by makig the buffer take loger to charge up the capacitace betwee the iverters. 35

44 1.5V Vb1 I pf Out vb2 Figure 27: Delay Buffer Stage Schematic Trasistors M5 ad M8 are used to lower the power cosumptio of the circuit ad ca be used to further reduce the drive of the iverters if eeded with a exteral voltage referece Pass-Gate Flip-Flop Desig The pipelie of D-Flip Flops ca be implemeted with ay stadard cell desig, but to improve the power cosumptio they were desiged usig pass gates. Pass gates have the beefit of o static or dyamic power cosumptio. Oly the iverter stages betwee pass gates coduct curret from Vdd to groud. The umber of flip-flops i the pipelie is equal to the umber of bits i the wake-up packet. Each bit is sequetially shifted through the pipelie util the etire wake-up packet is stored i the flipflops. The setup ad hold time of the flip flops is sufficietly small compared to the pulse width ad period of the icomig sigal that it ca be igored. 36

45 Clk Clk D Q Clk Clk Clk Clk Clk Clk Q Figure 28: Pass Gate Flip Flop Schematic Combiatioal Logic ad Node ID storage The cotets of the flip flop are compared to a preset value via combiatioal logic. The preset value, which is the odes uique ID, may be the cotets of a memory address, register, or other memory type accessible o the IC. It should ot be hardwired because this would ot allow for differet odes to be programed with their ow uique address. The output of each flip-flop is XNOR ed with the preset value. Whe the received packet matches the preset ode ID all of the XOR gates yield a low iput which are AND ed together. However, to prevet a AND gate with a large umber of iputs, it is broke up ito two layers of logic with NOR gates feedig ito NAND gates. 37

46 5. Circuit Simulatios The mai performace parameters of wake-up receivers are the power cosumptio, sesitivity, ad the latecy of its respose to the hub. The two parameters are ofte traded as for the case of duty cycled wake-ups. The more ofte it wakes up, the shorter the latecy is, but the larger the power cosumptio. The sesitivity of the receiver determies how powerful the hub trasmitter must be. If a hub has a larger power budget, a desig with a lower sesitivity ad hece more power efficiet, ca be used. The proposed serial code detector circuit was desiged ad simulated usig Natioal Semicoductor 180m CMOS techology. To reduce the leakage curret, the flip-flops use pass gates, ad the buffers ad digital logic operate with a raised threshold voltage. The icreased delay from the raised threshold voltage is acceptable due to the low bit rate of the message. I fact, it is beeficial for the delay buffer due to a loger delay for each stage. 5.1 Trasiet Aalysis The trasiet respose of both a log ad short pulse ca be see i Figure. The icomig RF pulses are at 2.4GHZ, with a short pulse width of 100s ad a log pulse width of 1µs. The Cockcroft- Walto multiplier output is labeled ad reaches 0.5 volts to be detected by the DC detector circuit. The DC detector output pulses are loger tha the icomig RF pulse because the Cockcroft-Walto multiplier charges up to the DC detectors tur o voltage quickly but because of the high impedace load the charge o the output takes loger to dissipate, causig a loger pulse. The output of the delay buffer ca be see delayed 500s after the output of the DC detector. 38

47 DC Detector Output Delay Buffer Output CW Multiplier Figure 29: Trasiet Simulatio Figure shows the DC detector output agai with the delayed copy of it self while receivig six bits. Below it i Figure the output of the first flip flop is show o the same time scale for compariso. Notice that the time betwee pulses ca vary ad ot have ay effect o the output. After receivig these six bits the cotets of the first six flip flops reads

48 Figure 30: Pulse Width Modulated Sigal ad Delayed Copy Figure 31: Flip Flop Output 5.2 Power Aalysis The simulatio results idicate that the leakage curret of the etire serial code detector is about 1 A with a 0.9 V supply. Whe the code detector receives a message with a bit rate of 200 Kbps, the average curret is 1.65 µa ad power cosumptio of µw. Figure shows the curret profile while receivig the data. Each curret spike correlates to a carrier pulse beig received ad triggig the clock for all of the flip-flops. 40

49 Figure 32: Trasiet Power Cosumptio whe receivig a message Table 1 shows the power cosumptio of a typical microcotroller, ad the proposed serial code detector. A Texas Istrumets low power microcotroller MSP430 dissipates 440 µw i active mode. Our serial code detector dissipates oly 1.48 µw, for a power dissipatio two orders of magitude less tha that of the microcotroller. So that our serial code detector ca save power sigificatly by ot wakig up a microcotroller for idetificatio of odes. However we ca assume that the ode will still eed a processor so the leakage power of the ode while sleepig will still be icreased with the additio of the wake-up receiver, but i this case, by oly 1 W. Table 1: Power Cosumptio of Decodig Blocks Block Leakage Power Dyamic Power MSP430 (LMP4 ad Active Mode at 2.2V) Serial Code Detector 220 W 440 µw 1 W 1.48 µw 41

50 We illustrate a wireless etwork with 20 odes to compare our wake-up receiver to a existig system based o processors for ode idetificatios. Let s suppose that the wake up sigal takes 1 ms to process for the existig system ad for our wake-up receiver, ad the target ode is further processed for 30 ms for our system. A existig system with the above microcotroller cosumes 440 uw for 1ms for each ode for the ode idetificatio, ad the total power cosumptio for 20 odes is 8.8 mw. The proposed serial code detector cosumes 1.48 uw for 1 ms ad 29.6 µw for 20 odes. After all the odes o the etwork have decoded the wake up sigal for our system, oly the target ode wakes for 30 ms to cosume 440 µw for 30 ms. The proposed wake-up receiver scheme saves eergy by about 300 times compared with a existig system. Existig systems usig a microprocessor to decode a received wake up sigal cosume more power tha the proposed serial detector, but icur less latecy. Pulse iterval ecodig [1] or other ecodig schemes are able to wake up odes ad respod quickly regardless of its distace to the hub because as log as the SNR of the received sigal is high eough, the sigal ca be decoded. I cotrast, the proposed serial code detector ad the associated protocol rely o successive trasmissios util the ode ca wake up to respod. Theoretically the target ode ca respod after oe request from the hub, but is likely that multiple tries will be eeded. The umber of tries eeded is determied by the lik budget of coectio, the time delay of the buffer chai, ad the differece i pulse widths betwee the large ad small pulses. Further, the latecy of our system icreases as the wake up time of the ode icreases. However, the icrease ca be as little as 3 µs [3], which ca be acceptable for a WBAN system. The results of this work as well as other recet publicatios o wake-up receivers are listed i Table 2. Also the power cosumptio is plotted versus the RF sesitivity i Figure. The power cosumptio of our system icludes the serial code detector which oly cosumes a additioal 1.48 µw while receivig a packet, for all of the other receivers i the compariso a processor o the ode has to be used. 42