AN Interconnection between JESD204A compliant devices. Document information

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1 Rev September 2010 Applicatio ote Documet iformatio Ifo Keywords Abstract Cotet JESD204A, Data coverters, CML, LVDS, Jitter, Couplig This documet describes the itercoectios that are required betwee the data coverter device ad the logic device for a JESD204A stadard compliat system. It also depicts the types of iterface that are ecessary for the various sigals.

2 Revisio history Rev Date Descriptio Secod, updated issue First issue Cotact iformatio For more iformatio, please visit: For sales office addresses, please sed a to: salesaddresses@xp.com All iformatio provided i this documet is subject to legal disclaimers. NXP B.V All rights reserved. Applicatio ote Rev September of 9

3 1. Itroductio The JDEC JESD204A is a serial iterface stadard dedicated to data coverters. It has bee defied by all the major stakeholders i the idustry, ivolvig System itegrators, IC suppliers (icludig ) ad Field Programmable Gate Array (FPGA) producers. This ecosystem is very useful as it allows easy iteroperability betwee IC providers ad FPGA makers. Its mai purpose is to simplify PCB desig ad facilitate loger trasmissios with guarateed itegrity. offer the followig JESD204A compliat devices, as part of its portfolio: DAC1408D bit dual DAC, JESD204A compliat, 650 Msps maximum output rate; see Ref. 1 Data sheet DAC1408D650 DAC1408D bit dual DAC, JESD204A compliat, 750 Msps maximum output rate; see Ref. 2 Data sheet DAC1408D750 ADC1413D 14-bit dual ADC, JESD204A compliat, f s = 125 Msps, 105 Msps, 80 Msps ad 65 Msps; Ref. 3 Data sheet ADC1413D series ADC1213D 12-bit dual ADC, JESD204A compliat, f s = 125 Msps, 105 Msps, 80 Msps ad 65 Msps Ref. 4 Data sheet ADC1213D series ADC1113D 11-bit dual ADC, JESD204A compliat, f s =125Msps Ref. 5 Data sheet ADC1113D125 ADC1413S 14-bit sigle ADC, JESD204A compliat, f s = 125 Msps, 105 Msps, 80 Msps ad 65 Msps Ref. 6 Data sheet ADC1413S series ADC1213S 12-bit sigle ADC, JESD204A compliat, f s = 125 Msps, 105 Msps, 80 Msps ad 65 Msps Ref. 7 Data sheet ADC1213S series Xilix Virtex5 documetatio is available from: Documets of iterest are UG196 (Virtex-5 FPGA RocketIO GTP Trasceiver) ad DS202 (Virtex-5 FPGA Data Sheet: DC ad Switchig Characteristics). This applicatio ote does ot ited to replace these. JESD204A has bee issued by the JEDEC committee. This specificatio ca be dowloaded from the web site NXP also provides a applicatio ote (AN10812_1, JESD204A: New serializatio techology for high speed data coverters) to give the customer sufficiet backgroud o that stadard. All iformatio provided i this documet is subject to legal disclaimers. NXP B.V All rights reserved. Applicatio ote Rev September of 9

4 2. Efficietly coectig JESD204A DAC to Xilix FPGA Fig 1. Lae itercoect example JESD204A is a poit-to-poit protocol. There are three categories of coectios: Laes: Carry the data. SYNC: This is a sychroizatio sigal used at the begiig of the trasmissio. It is also used by the receiver to trigger loss of sychroizatio ad requests reiitializatio. Frame clock: This is the system clock. 2.1 Virtex5 FPGA The key feature that these devices require is a SerDes macro. It esures the proper serializatio/deserializatio of the data at very high speeds. Moreover, they have extra features such as Phase Locked Loops (PLL) ruig at very high frequecies (> 1 GHz) ad hard wired 8b/10b codig/decodig. I Xilix termiology, these highly specialized macros are amed GTP or GTX depedig o their characteristics. The commercial ame used is RocketIO. All Virtex5 devices, with part umbers edig "T", cotai such trasceivers (eg XC5VLX50T, XC5VFX70T, etc.). GTP ad GTX have a fixed locatio iside the FPGA. This is a importat poit for board desig strategy. 2.2 Laes JESD204A specifies that the data lik should be Curret Mode Logic (CML) compliat. This implies curret switchig with the positive supply, V DD as referece. This also meas that each lae is made up of a differetial pair. The termiatio level o both sides of the lik is set to. As V DD is the referece, special care must be take whe the trasmitter (a FPGA) ad receiver (a DAC) have differet supply voltages. This ca lead to differet commo-mode voltages o each side, thus creatig a potetial differece. JESD204A has itroduced the cocept of AC or DC couplig to avoid differet commo-mode voltages o each side. This prevets static curret from flowig from oe device to the other. All iformatio provided i this documet is subject to legal disclaimers. NXP B.V All rights reserved. Applicatio ote Rev September of 9

5 V DD1 (1) V DD2 (1) V DDD data i + Zdiff = 100 Ω data i + Zdiff = 100 Ω data i data i 019aaa aaa377 Fig 2. AC couplig Fig 3. DC couplig The AC couplig capacitor ad the load resistors create a high pass filter. The value of the capacitor determies the lower cut-off frequecy of this first order filter. A 10 F capacitor is sufficiet to esure correct AC couplig, as the cut-off frequecy is at 0.3 MHz ad is therefore ot see by the high frequecy sigals. Example: The DAC1408D650 demoboard features a DAC1408D650 ad a XC5VLX50T. The DAC1408D has a default commo-mode voltage of 800 mv. Virtex5 GTP has a commo-mode voltage of 800 mv, so o capacitor is required. The DAC1408D650 has a cofigurable commo-mode voltage, which covers a rage of 700 mv to 1400 mv if aother device is used. 2.3 Frame clock This clock must be provided to the FPGA ad to the data coverter device. They must have the same frequecy but the phase relatioship ca have ay value (e.g. 180 º). aalog i SAMPLE CLOCK idle mode DUMMY BITS A/D DUMMY BITS A/D PLL M frame clock FRAME ASSEMBLY 10 ON/OFF SCRAMBLING SYNC INSERTION SYNC DECODE CODEGR SYNC 8 ERR data B10B SER DESER 8B10B CHARACTER CLOCK LINE CLOCK FRAME CLOCK ADC TX syc LOGIC DEVICE RX REFCLK PLL 10 phase select COMMA DETECT SIGNAL DETECT FRAME SYNC ON/OFF DESCRAMBLING 8 loss of sigal FRAME REASSEMBLY CHARACTER CLOCK FIFO CORE LOGIC frame clock cotrol iterface 019aaa374 Fig 4. System descriptio of the JESD204A with clock distributio All iformatio provided i this documet is subject to legal disclaimers. NXP B.V All rights reserved. Applicatio ote Rev September of 9

6 All clocks are based o the frame clock, which is the absolute timig referece i the JESD204A system. It is a relatively low frequecy clock which is also the samplig clock of the ADC or the DAC. It is distributed as a separate sigal ad supplied to all trasmitter ad receiver devices i the pipe. The JESD204A trasmitter ad receiver must first sychroize through the SYNC iterface. This iterface is used as a time-critical retur path from the receiver(s) to the trasmitter(s). It is sychroous with the frame clock iput of the devices. The JESD204A data iterface guaratees the sychroizatio betwee differet devices. This allows for good matchig betwee data laes, which is very beeficial for the iteroperability betwee FPGA vedors. As metioed i Sectio 2.1 a 8b/10b codig is used to ecode data before trasmissio. The 8b/10b codes have the followig properties: The global clock etwork The dedicated macro iput Xilix recommeds the dedicated macro iput for best jitter performaces. This dedicated iput is differetial. It is very similar to CML ad is termiated by a resistor to a commo-mode voltage. Drivig these pis directly is oly possible with a driver that has the same commo-mode voltage. Otherwise, bypass capacitors must be set up o the ets. Whe a clock is provided to the ADC device, it should be i a suitable differetial iterface, LVDS, LVPECL, SINE or LVCMOS. It is the samplig clock ad it will ifluece the quality of the ADC. 2.4 Covertisseur Grade Vitesse (CGV) implemetatio CGV desigates compliat, superset implemetatio of the JEDEC JESD204A iterface stadard, with a ehaced rate (4.0 Gbps typical), a ehaced reach (100 cm typical), ehaced features (multiple DAC sychroizatio) ad a assured FPGA iteroperability. offers ehacemets i terms of trasceiver rate (up to 4.0 Gbps agaist the stadard rate of Gbps, a 28 % icrease) ad trasmitter reach (up to 100 cm versus the stadard reach of 20 cm, a 400 % icrease). The ehaced CGV features iclude Multi Device Sychroizatio (MDS), which is ot specified, but iformatively discussed i the JEDEC specificatio. has implemeted this optioal feature to eable LTE MIMO base statios ad other advaced multichael applicatios. The implemetatio of MDS eables up to sixtee DAC data streams to be sample sychroized ad phase coheret. 2.5 Layout Two types of buses are required to itercoect JESD204A data coverter device ad a Virtex5: LVDS CML All iformatio provided i this documet is subject to legal disclaimers. NXP B.V All rights reserved. Applicatio ote Rev September of 9

7 3. Refereces LVDS routig LVDS sigalig has very fast edges. Use differetial routig with cotrolled impedace. Impedace discotiuities must be avoided as they create high frequecy spurs, which ca create oise whe coupled to the rest of the circuit. Target impedace is 100 Ω differetial CML routig The same layout costraits as for LVDS apply here. Target impedace is also 100 Ω differetial. Both the JESD204A DAC ad the Virtex5 FPGA have lae polarity swappig capability to ease PCB routig. This allows the differetial pairs to be routed i the most direct way possible ad the polarity issue to be dealt with very easily. [1] Data sheet DAC1408D650 Dual 14-bit DAC; up to 650 Msps; 2, 4 or 8 iterpolatig [2] Data sheet DAC1408D750 Dual 14-bit DAC; up to 750 Msps; 2, 4 or 8 iterpolatig [3] Data sheet ADC1413D series Dual 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A iterface [4] Data sheet ADC1213D series Dual 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps [5] Data sheet ADC1113D125 Dual 11-bit ADC; serial JESD204A iterface [6] Data sheet ADC1413S series Sigle 14-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps; serial JESD204A iterface [7] Data sheet ADC1213S series Sigle 12-bit ADC; 65 Msps, 80 Msps, 105 Msps or 125 Msps All iformatio provided i this documet is subject to legal disclaimers. NXP B.V All rights reserved. Applicatio ote Rev September of 9

8 4. Legal iformatio 4.1 Defiitios Draft The documet is a draft versio oly. The cotet is still uder iteral review ad subject to formal approval, which may result i modificatios or additios. does ot give ay represetatios or warraties as to the accuracy or completeess of iformatio icluded herei ad shall have o liability for the cosequeces of use of such iformatio. 4.2 Disclaimers Limited warraty ad liability Iformatio i this documet is believed to be accurate ad reliable. However, does ot give ay represetatios or warraties, expressed or implied, as to the accuracy or completeess of such iformatio ad shall have o liability for the cosequeces of use of such iformatio. I o evet shall be liable for ay idirect, icidetal, puitive, special or cosequetial damages (icludig - without limitatio - lost profits, lost savigs, busiess iterruptio, costs related to the removal or replacemet of ay products or rework charges) whether or ot such damages are based o tort (icludig egligece), warraty, breach of cotract or ay other legal theory. Notwithstadig ay damages that customer might icur for ay reaso whatsoever, aggregate ad cumulative liability towards customer for the products described herei shall be limited i accordace with the Terms ad coditios of commercial sale of. Right to make chages reserves the right to make chages to iformatio published i this documet, icludig without limitatio specificatios ad product descriptios, at ay time ad without otice. This documet supersedes ad replaces all iformatio supplied prior to the publicatio hereof. Suitability for use products are ot desiged, authorized or warrated to be suitable for use i life support, life-critical or safety-critical systems or equipmet, or i applicatios where failure or malfuctio of a product ca reasoably be expected to result i persoal ijury, death or severe property or evirometal damage. accepts o liability for iclusio ad/or use of products i such equipmet or applicatios ad therefore such iclusio ad/or use is at the customer s ow risk. Applicatios Applicatios that are described herei for ay of these products are for illustrative purposes oly. makes o represetatio or warraty that such applicatios will be suitable for the specified use without further testig or modificatio. Customers are resposible for the desig ad operatio of their applicatios ad products usig products, ad accepts o liability for ay assistace with applicatios or customer product desig. It is customer s sole resposibility to determie whether the NXP Semicoductors product is suitable ad fit for the customer s applicatios ad products plaed, as well as for the plaed applicatio ad use of customer s third party customer(s). Customers should provide appropriate desig ad operatig safeguards to miimize the risks associated with their applicatios ad products. does ot accept ay liability related to ay default, damage, costs or problem which is based o ay weakess or default i the customer s applicatios or products, or the applicatio or use by customer s third party customer(s). Customer is resposible for doig all ecessary testig for the customer s applicatios ad products usig NXP Semicoductors products i order to avoid a default of the applicatios ad the products or of the applicatio or use by customer s third party customer(s). NXP does ot accept ay liability i this respect. Export cotrol This documet as well as the item(s) described herei may be subject to export cotrol regulatios. Export might require a prior authorizatio from atioal authorities. 4.3 Trademarks Notice: All refereced brads, product ames, service ames ad trademarks are the property of their respective owers. All iformatio provided i this documet is subject to legal disclaimers. NXP B.V All rights reserved. Applicatio ote Rev September of 9

9 5. Cotets 1 Itroductio Efficietly coectig JESD204A DAC to Xilix FPGA Virtex5 FPGA Laes Frame clock Covertisseur Grade Vitesse (CGV) implemetatio Layout LVDS routig CML routig Refereces Legal iformatio Defiitios Disclaimers Trademarks Cotets Please be aware that importat otices cocerig this documet ad the product(s) described herei, have bee icluded i sectio Legal iformatio. NXP B.V All rights reserved. For more iformatio, please visit: For sales office addresses, please sed a to: salesaddresses@xp.com Date of release: 23 September 2010 Documet idetifier: