New MEGA POWER DUAL IGBT Module with Advanced 1200V CSTBT Chip

Transcription

1 New MEGA POWER DUAL IGBT Module with Advaced 1200V CSTBT Chip Juji Yamada*, Yoshiharu Yu*, Joh F. Dolo**, Eric R. Motto** * Power Device Divisio, Mitsubishi Electric Corporatio, Fukuoka, Japa ** Powerex Icorporated, Yougwood, Pesylvaia, USA Abstract - A ew 1400A/1200V MEGA POWER DUAL IGBT module has bee developed for high power idustrial applicatios. The ew module icorporates the latest advaces i chip techology to produce a device with the rugged safe operatig area ad low losses required i high power idustrial applicatios. The ew power chip is based o a optimized wide cell pitch Carrier Stored Trech Bipolar Trasistor (CSTBT). The module features a optimized high curret dual (half bridge) package with low parasitic iductace ad itegrated features desiged to allow simplified assembly of high power iverters. I. INTRODUCTION The use of IGBT modules i megawatt class idustrial iverters has required a rethikig of basic power structure desig. The desiger is faced with several fudametal challeges. The first is maitaiig the low iductace ecessary to cotrol trasiet voltages while the physical size ad legth of the mai bus itercoects icrease. The solutio to this problem usually ivolves a geeral shrikig of the power structure. This shrikig gives rise to a secod problem, which is how to remove thousads of watts of losses from a relatively small heat sik area. I additio, the weight ad itricacy of the lamiated buswork ad thermal system i these iverters ofte results i a complex assembly that is difficult ad expesive to maufacture. The MEGA POWER DUAL TM IGBT module preseted i this paper utilizes advaced chip techology combied with a ew package cocept to help alleviate these problems. II. NEW 1200V CSTBT CHIP Fig. 1 shows a equivalet circuit model for a ideal IGBT i its o state. This circuit shows that the ostate voltage (V CE(sat)) of a IGBT ca be thought of as the sum of the forward voltage of a PIN diode ad the R DS(ON) drop of a MOSFET. The R DS(ON) of the MOSFET portio of Fig. 1 ca be decreased by icreasig the total chael width per uit chip area. High-desity trech gate surface structures have bee developed to provide a substatial icrease i chael width [2][4]. At the same time the trech gate structure elimiates the parasitic JFET resistace associated with the MOSFET. As a result, the largest compoet of ostate voltage i state-of-the-art trech gate IGBT devices ca be liked to the forward voltage drop of the PIN diode portio of Fig. 1. Normally a PIN diode has a symmetrical excess carrier distributio i the regio as show by curve A i Fig. 2. Curve B shows that the excess carrier distributio i a covetioal trech gate IGBT deviates from the ideal case by steadily decreasig as it approaches the emitter side of the device. This oideal behavior becomes eve more proouced i devices with high blockig voltage ratigs. The decreased carrier cocetratio ear the emitter side effectively icreases the resistace of the PIN diode which results i a icrease i ostate voltage (V CE(sat)). To improve the carrier cocetratio at the emitter side a ew chip desig called Carrier Stored Trech Bipolar Trasistor (CSTBT) has Emitter E C MOSFET G PIN Diode Fig. 1 OState Model of IGBT B C A Icreasig Covetioal Trech IGBT CSTBT Ideal PIN Diode Fig. 2 Excess Carrier Distributio i the Layer

2 Emitter Emitter NPT New LPT PT(Epi) Buried metal Gate Oxide - SiO 2 Gate - Polysilico p + + Buried layer (Epi layer) p + + (Epi Layer) p + p p p Fig. 3a New CSTBT Chip Fig. 3b Covetioal Trech Gate IGBT Fig. 4 Compariso of IGBT Vertical Structure bee developed. The CSTBT is fabricated with a additioal type buried layer. The buried layer provides stored carriers to produce the modified carrier distributio show i curve C of Fig. 2. The resultig carrier distributio is closer to the ideal case ad produces icreased coductivity i the layer. The result is a substatial reductio i the ostate voltage of the device. Fig. 3a ad 3b show the cell structure of a covetioal high cell desity trech gate IGBT compared to the CSTBT. The key differece is the additio of the buried layer to provide icreased carrier cocetratio ear the emitter side of the device. I additio to the buried layer, the ew CSTBT chip utilizes a optimized vertical structure based o Mitsubishi s Light Puch-Through (LPT) techology. A schematic compariso of covetioal NPT, Epitaxial PT ad LPT chips is show i Fig. 4. The key to the LPT structure is a optimized drift regio that it is thi eough to provide low V CE(SAT) while maitaiig a robust switchig SOA. A buffer layer is utilized to secure a sufficietly high breakdow voltage ad low leakage curret i the presece of the optimally thi drift regio. The thickess of the drift layer is selected so that the depletio regio exteds to the collector whe rated voltage is applied i the off state. However, at ormal operatig voltages the depletio regio does ot reach the buffer layer givig a operatio characteristic similar to covetioal NPT desigs. Aother feature of the LPT structure is optimized buffer ad p collector layers that provide cotrolled carrier cocetratio i the regio durig coductio. The result is efficiet switchig characteristics without the eed for carrier lifetime Emitter p a. Covetioal Trech Gate IGBT SiO2 Gate p c. Wide Cell Pitch Trech Gate IGBT Emitter SiO2 p Gate p b. Narrow Cell Pitch CSTBT Fig. 5 IGBT Chip Structure Compariso d. Wide Cell Pitch CSTBT

3 VCE (V) Plugged Cells p Fig. 6 Plugged Cell Merged CSTBT Short Circuit Characteristic T C=125C New Plugged Cell Merged CSTBT Fig. 7 Short-Circuit Waveforms Emitter cotrol processig. The ew CSTBT chips are fabricated from low cost type sigle crystal (oepitaxial) wafer material. Fig. 5a shows a covetioal high cell desity trech gate IGBT. The high cell desity helps to reduce V CE(SAT) by makig the R DS(ON) of the MOSFET part of the device very low. Ufortuately, the MOSFET part of this structure also permits very high short-circuit currets which degrades the short-circuit withstadig capability of the device. Uder low impedace short-circuit coditios, the curret becomes very high before the device desaturates ad limits the curret. The self-limited curret of the IGBT is ofte called the shortcircuit saturatio curret. The short-circuit saturatio curret for the covetioal arrow pitch trech gate IGBT with V GE=15V is more tha fiftee times the omial rated curret of the device. This high short-circuit saturatio curret limits short-circuit withstadig capability of the chip aloe to about 5µs. To recover the short-circuit withstadig capability required for may idustrial applicatios, it is ecessary to add a additioal curret limitig circuit to reduce the gate voltage uder short-circuit coditios [2]. Ufortuately this icreases the complexity of the device. Obviously, it is desirable to have a chip with a lower shortcircuit saturatio curret so that this additioal curret limitig circuit would ot be required. SiO2 Gate JC (A/cm 2 ) The short-circuit saturatio curret of a IGBT is primarily cotrolled by the characteristics of the MOSFET part of the device. Oe effective way to reduce the short-circuit saturatio curret ad improve short-circuit ruggedess is to reduce the total chael width of the MOSFET part of the IGBT structure. This ca be accomplished by utilizig a wider cell pitch structure as show i Fig. 5c. Ufortuately, reducig the chael width of the covetioal trech gate IGBT icreases the R DS(ON) of the MOSFET portio of the device resultig i a icreased V CE(sat). The CSTBT chip structure described above ca be used to mitigate the udesirable icrease of ostate voltage caused by a wider cell pitch desig. The structure of the wide cell pitch CSTBT is show i Fig. 5d. By selectig appropriate trech spacig ad depth the series resistace ad performace of the MOS ad diode regios ca be optimized to provide low ostate voltage while maitaiig low shortcircuit saturatio curret [4]. The short-circuit saturatio curret ca be adjusted to provide short-circuit withstadig capability of 20µs elimiatig the eed for additioal limitig circuits. At the same time, usig the CSTBT structure icreases the coductivity i the drift regio to produce a low ostate voltage. Selectio of the optimal cell pitch allows the device to be tailored for the most desirable trade-off betwee short-circuit saturatio curret ad V CE(SAT). For applicatios that do ot require as much short-circuit withstadig capability, a arrow cell pitch ca be used to give a lower V CE(SAT). A wider cell pitch ca be useful for maitaiig short-circuit ruggedess i higher voltage devices. To provide process flexibility with a miimum umber of mask chages a ovel structure called Plugged Cell Merged (PCM) CSTBT was developed. This structure is illustrated i Fig. 6. With this structure the cell pitch is adjusted by pluggig some portio of the cells i a covetioal high cell desity device. This process allows the cell desity to be optimized by chagig oly two masks. Table 1 Compariso 100A, 1200V IGBT 3 rd Geeratio Geeratio New CSTBT Family Name H-Series F-Series NF-Series Base Wafer Material Epitaxial Epitaxial Float Zoe Surface 1µm Trech 3µm Plaar 1µm Trech Patter PCM Vertical Desig PT PT LPT V 2.5V 1.9V 1.9V I C(rated) SWSOA Over 300A Over 400A Over 400A C ies 9.6F 24.3F 12.8F Short-Circuit Curret 600A Short-Circuit Withstadig t W(crit) 20µs 4 th 1500A (Without RTC) 5µs (Without RTC) 500A 20µs

4 The polysilico i the plugged cell is coected to the emitter electrode. This coectio provides additioal drai to source capacitace that helps to stabilize the drai potetial uder short-circuit coditios. The result is stable oscillatio free short-circuit operatio eve uder high speed switchig coditios. The waveform i Fig. 7 shows the typical low impedace short-circuit behavior of the PCM CSTBT chip. A added advatage of the PCM structure is its reduced iput capacitace compared to covetioal high cell desity trech gate devices. Table 1 compares the key characteristics of the ew PCM CSTBT chip to previous geeratio devices. N-Bus (1.59mm Cu) N Isulator (0.38mm Nomex) P P-Bus (1.59mm Cu) III. MEGA POWER DUAL TM PACKAGE Most high power idustrial iverters are based o covetioal bridge cofiguratios i which pairs of IGBTs (legs) are coected across a DC bus. I large iverters miimizig the iductace of this DC bus is critical for cotrollig trasiet voltages durig switchig. To simplify the desig of this low iductace DC bus it is apparet that modules i a dual or half bridge cofiguratio are advatageous. This is especially true if the modules iteral iductace ca be miimized to allow a simple two-layer lamiated DC bus. Based o this cocept a ew high curret dual package was developed. The ew module called MEGA POWER DUAL TM has a iteral desig ad exteral cofiguratio optimized for large idustrial iverter applicatios. Fig. 8 is a photograph of the ew high curret dual IGBT module. The package show is desiged to provide omial collector curret ratigs of up to 1400A at 1200V ad 1000A 1700V. The target applicatios iclude large idustrial iverters for motor drive, UPS, ad utility iterface for alterate eergy. Three of these dual modules ca be used to provide about 0.5MW of output power. Multi-megawatt iverters ca the be costructed by usig either paralleled modules or iverter sub assemblies. The size ad weight of system compoets i these large iverters is ofte a cocer 36.4mm 34.5mm Figure 9 Offset step electrode structure durig assembly, shippig, ad istallatio. The MEGA POWER DUAL TM module has bee desiged specifically to help reduce the size, weight, ad cost of high power iverters. The superior performace of the ew CSTBT chip eables a very compact package desig with a footprit of oly 150mm x 134mm. This is approximately half the size of a equivalet half bridge utilizig third geeratio IGBT modules. To help simplify lamiated bus desig the module s P ad N termials have a step offset of 1.9mm as show i Fig. 9. The step allows simple plaar buswork to be used. A example cofiguratio for the bus plates ad isulatio material is also show i Fig. 9. To miimize the weight ad cost of the buswork it is desirable to utilize thier copper sheet material. Wide, relatively thi, bus plates are usually more tha capable of carryig the ecessary curret i high power iverters. However, thicker bus plates are ofte eeded due to the local resistace at the bolted coectios. To avoid this potetial problem the ew module utilizes large cotact area three bolt power termial Output Termials P Bus Termials N Bus Termials 150mm Two Layer Lamiated Bus 134mm Figure 8 MEGA DUAL Package Figure 10 Typical Power Bus Cofiguratio

5 OUTPUT P N Figure 13 Gate Charge Characteristic Figure 11 Iteral Structure of New Module Iteral Lamiated Bus coectios. The module s power termials have bee located o the package i a flow-through patter with the positive ad egative bus coectios o oe ed ad the output coectio o the opposite ed. This cofiguratio allows a simplified bus layout as show i Fig. 10. I this structure a simple two layer lamiated bus provides a low iductace coectio from the mai capacitor bak to the C1 ad E2 termials of the module. A importat advatage of the flow through desig is that it elimiates the eed for the bus to exted over the module. This allows free access to the gate coectios ad moutig bolts for simplified assembly ad maiteace. It also helps to miimize the size ad weight of the required buswork. Aother feature of the ew package is recessed positive lockig coectors for gate drive ad collector potetial sesig. These coectors allow the gate drive circuits to be easily istalled after all heavy assembly is completed. This helps to reduce the risk of damage to the delicate gate drive compoets durig assembly. To help maitai low iteral iductace the ew module utilizes a uique three layer iteral lamiated bus structure as show i Fig. 11. The lamiated bus provides low impedace, simplified assembly ad a symmetrical chip layout. A added advatage is that the chips are positioed i lie with ad close to the moutig bolts to provide superior heat trasfer. Low thermal impedace is achieved through the use of AlN DBC ceramic isolatio. Figure 12 Saturatio Voltage Characteristics Figure 14 Half bridge Switchig Characteristics

6 Figure 16 Trasiet Thermal Characteristic Figure 15 Switchig Loss Characteristics IV. MEGA POWER DUAL TM CHARACTERISTIC ANALYSIS Fig. 12 shows the ostate voltage characteristic (V CE(sat) ) of the ew 1400A, 1200V MEGA POWER DUAL TM IGBT module. The low ostate voltage is the result of the CSTBT s stored carrier effect ad its dramatic reductio of the PIN diode s resistace compared to a covetioal IGBT structure. The ostate voltage of the PCM CSTBT chip is approximately the same as the arrow cell pitch trech gate IGBT (F-Series), demostratig that the effect of the CSTBT structure overcomes the icrease of the MOS chael resistace caused by the wider cell pitch. A advatage of the wide cell pitch CSTBT is its positive coefficiet of saturatio voltage. Fig. 12 shows that the V CE(SAT) will icrease with icreasig temperature at most ormal operatig currets. This characteristic allows simplified parallel operatio ad miimizes the risk of thermal ru away coditios. A added advatage of the wide cell pitch CSTBT is a large reductio i gate Miller capacitace. As show i Table 1 the gate capacitace is about half of a equivaletly rated forth geeratio trech gate device (F-Series). Fig. 13 shows the gate charge characteristic for the ew 1400A, 1200V module. With +15V gate drive the total charge is about 7200C which is oly slightly more tha a 600A, 1200V F-Series module. Half bridge (iductive load) switchig time characteristics are show i Fig. 14. The fall ad rise times at rated curret are less tha 200s demostratig that the CSTBT is suitable for operatio frequecies i the 10kHz to 20kHz rage. Fig. 15 shows the switchig eergy characteristic. The low switchig losses are the result of optimized ad buffer layers i the CSTBT chip. Fig. 16 shows the trasiet thermal impedace characteristic of the ew module package. Low thermal impedace is achieved usig 130W/mK alumium itride ceramic isolatio material. This ceramic was selected because it offers more tha five times better performace tha the commoly used Alumia (Al 2 O 3 ) ceramic. The module also employs a 4mm thick copper base for good trasiet thermal performace ad lateral heat spreadig. V. CONCLUSION A ew high power dual IGBT module has bee preseted. The ew module has a uique package optimized for high power idustrial iverter applicatios. The module s mechaical cofiguratio is optimized to allow simplified low cost assembly of high curret power stages. The ew module utilizes a advaced PCM CSTBT chip to provide low losses ad rugged short-circuit performace. REFERENCES [1] H. Takahashi, et al. Carrier Stored Trech-Gate Bipolar Trasistor (CSTBT) - A Novel Power Device for High Voltage Applicatio The 8th Iteratioal Symposium o Power Semicoductor Devices ad ICs 1996 [2] E. Motto, et al. Characteristics of a 1200V PT IGBT With Trech Gate ad Local Life Time Cotrol, IEEE Idustry Applicatios Society 1998 [3] H. Iwamoto, et al. A New Puch Through IGBT Havig A New N-Buffer Layer IEEE Idustry Applicatios Society 1999 [4] H. Nakamura, et al. Wide cell pitch 1200V NPT CSTBTs With Short-Circuit Ruggedess Iteratioal Symposium o Power Semicoductor Devices ad ICs 2001