JC050A, JC075A, JC100A Power Modules: dc-dc Converters; 18 Vdc to 36 Vdc Input, 5 Vdc Output; 50 W to 100 W

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1 JC, JC7, JC1 Power Modules: dc-dc Coverters; 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W Features The JC, JC7, JC1 Power Modules use advaced, surface-mout techology ad deliver high-quality, efficiet, compact dc-dc coversio. pplicatios Distributed power architectures Workstatios EDP equipmet Telecommuicatios Small size: 1. mm x 7.9 mm x 1.7 mm (. i. x.8 i. x. i.) High power desity High efficiecy: 8% typical Low output oise Costat frequecy Idustry-stadard piout Metal baseplate :1 iput voltage rage Overtemperature protectio (1 W oly) Remote sese Remote o/off djustable output voltage Case groud pi UL * Recogized, CS Certified, VDE Licesed Optios Choice of remote o/off logic cofiguratio Heat sik available for exteded operatio * UL is a registered trademark of Uderwriters Laboratories, Ic. CS is a registered trademark of Caadia Stadards ss. Descriptio The JC, JC7, JC1 Power Modules are dc-dc coverters that operate over a iput voltage rage of 18 Vdc to 3 Vdc ad provide a precisely regulated dc output. The outputs are fully isolated from the iputs, allowig versatile polarity cofiguratios ad groudig coectios. The modules have maximum power ratigs from W to 1 W at typical full-load efficiecy of 8%. The sealed modules offer metal baseplate for excellet thermal performace. Threaded-through holes are provided to allow easy moutig or additio of a heat sik for high-temperature applicatios. The stadard feature set icludes remote sesig, output trim, ad remote o/off for coveiet flexibility i distributed power applicatios.

2 JC, JC7, JC1 Power Modules: dc-dc Coverters; 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W bsolute Maximum Ratigs Stresses i excess of the absolute maximum ratigs ca cause permaet damage to the device. These are absolute stress ratigs oly. Fuctioal operatio of the device is ot implied at these or ay other coditios i excess of those give i the operatios sectios of the data sheet. Exposure to absolute maximum ratigs for exteded periods ca adversely affect device reliability. Parameter Symbol Mi Max Uit Iput Voltage Cotiuous VI Vdc I/O Isolatio Voltage 1 Vdc Operatig Case Temperature TC 1 C (See Thermal Cosideratios sectio.) Storage Temperature Tstg 1 C Electrical Specificatios Uless otherwise idicated, specificatios apply over all operatig iput voltage, resistive load, ad temperature coditios. Table 1. Iput Specificatios Parameter Symbol Mi Typ Max Uit Operatig Iput Voltage VI Vdc Maximum Iput Curret (VI = V to 3 V; IO = IO, max): JC (See Figure 1) JC7 (See Figure ) JC1 (See Figure 3.) II, max II, max II, max Irush Trasiet i t 1. s Iput Reflected-ripple Curret, Peak-to-peak mp-p ( Hz to MHz, 1 µh source impedace; see Figure.) Iput Ripple Rejectio (1 Hz) db Fusig Cosideratios CUTION: This power module is ot iterally fused. iput lie fuse must always be used. This ecapsulated power module ca be used i a wide variety of applicatios, ragig from simple stad-aloe operatio to a itegrated part of a sophisticated power architecture. To preserve maximum flexibility, iteral fusig is ot icluded; however, to achieve maximum safety ad system protectio, always use a iput lie fuse. The safety agecies require a ormal-blow, dc fuse with a maximum ratig of (see Safety Cosideratios sectio). Based o the iformatio provided i this data sheet o irush eergy ad maximum dc iput curret, the same type of fuse with a lower ratig ca be used. Refer to the fuse maufacturer s data for further iformatio. Lieage Power

3 JC, JC7, JC1 Power Modules: dc-dc Coverters; 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W Electrical Specificatios (cotiued) Table. Output Specificatios Parameter Device Symbol Mi Typ Max Uit Output Voltage Set Poit ll VO, set.9..8 Vdc (VI = 8 V; IO = IO, max; TC = C) Output Voltage (Over all operatig iput voltage, resistive load, ad temperature coditios util ed of life; see Figure 1.) ll VO.8.1 Vdc Output Regulatio: Lie (VI = 18 V to 3 V) Load (IO = IO, mi to IO, max) Temperature (TC = C to +1 C) Output Ripple ad Noise Voltage (See Figure 1.): RMS Peak-to-peak ( Hz to MHz) Exteral Load Capacitace (electrolytic) ll 1, µf Output Curret (t IO < IO, mi, the module may exceed output ripple specificatios.) Output Curret-limit Iceptio (VO = 9% of VO, om) Table 3. Isolatio Specificatios ll ll ll ll ll JC JC7 JC1 JC JC7 JC1 IO IO IO IO, cli IO, cli IO, cli % % mv mvrms mvp-p Output Short-circuit Curret (VO = mv) ll 17 %IO, max Efficiecy (VI = 8 V; IO = IO, max; TC = 7 C) JC JC7 JC1 η η η % % % Switchig Frequecy ll khz Dyamic Respose (IO/t = 1 /1 µs, VI = 8 V, TC = C): Load Chage from IO = % to 7% of IO, max: Peak Deviatio Settlig Time (VO < 1% of peak deviatio) Load Chage from IO = % to % of IO, max: Peak Deviatio Settlig Time (VO < 1% of peak deviatio) ll ll ll ll 3 3 %VO, set µs %VO, set µs Parameter Mi Typ Max Uit Isolatio Capacitace pf Isolatio Resistace 1 MΩ Lieage Power 3

4 JC, JC7, JC1 Power Modules: dc-dc Coverters; 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W Geeral Specificatios Parameter Mi Typ Max Uit Calculated MTBF (IO = 8% of IO, max; TC = C),, hr. Weight 1 (3.) g (oz.) Feature Specificatios Uless otherwise idicated, specificatios apply over all operatig iput voltage, resistive load, ad temperature coditios. See Feature Descriptios for additioal iformatio. Parameter Symbol Mi Typ Max Uit Remote O/Off Sigal Iterface (VI = V to 3 V; ope collector or equivalet compatible; sigal refereced to VI( ) termial; see Figure 17 ad Feature Descriptios.): JCxxx1 Preferred Logic: Logic LowModule O Logic HighModule Off JCxxx Optioal Logic Logic LowModule Off Logic HighModule O Logic Low: t Io/off = 1. m t Vo/off =. V Logic High: t Io/off =. µ Leakage Curret Tur-o Time (See Figure 13) (IO = 8% of IO, max; VO withi ±1% of steady state) Output Voltage djustmet (See Feature Descriptios.): Output Voltage Remote-sese Rage Output Voltage Set-poit djustmet Rage (trim) Vo/off Io/off Vo/off Io/off V m V µ ms V %VO, om Output Overvoltage Clamp VO, clamp.9 7. V Overtemperature Shutdow Tc 1 C (1 W oly; see Feature Descriptios.) Lieage Power

5 JC, JC7, JC1 Power Modules: dc-dc Coverters; 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W Characteristic Curves The followig figures provide typical characteristics for the JC, JC7, JC1 power modules. The figures are idetical for both o/off cofiguratios INPUT CURRENT, II (V) IO = 1 IO = IO = INPUT CURRENT, II () 7 IO = IO = 1 3 IO = INPUT VOLTGE, VI () 8-18 (C) Figure 1. Typical JC Iput Characteristics at Room Temperature INPUT VOLTGE, VI (V) (C) Figure 3. Typical JC1 Iput Characteristics at Room Temperature INPUT CURRENT, II () 3 1 IO = 1 IO = 7. IO =.7 OUTPUT VOLTGE, VO (V) 3 1 VI = 3 V VI = 7 V VI = 18 V INPUT VOLTGE, VI (V) (C) Figure. Typical JC7 Iput Characteristics at Room Temperature OUTPUT CURRENT, IO () 8-19 (C) Figure. Typical JC Output Characteristics at Room Temperature Lieage Power

6 JC, JC7, JC1 Power Modules: dc-dc Coverters; 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W Characteristic Curves (cotiued) VOLTGE, VO (V) OUTPUT 3 1 VIN = 18 V VIN = 8 V VIN = 3 V OUTPUT CURRENT, I O () (C) Figure. Typical JC7 Output Characteristics at Room Temperature. EFFICIENCY, η (%) VI = 18 V VI = 7 V VI = 3 V OUTPUT CURRENT, I O () 8-1 (C) Figure 7. Typical JC Coverter Efficiecy vs. Output Curret at Room Temperature OUTPUT VOLTGE, VO (V) 3 1 VIN = 18 V VIN = 8 V VIN = 3 V EFFICIENCY, η (%) VI = 3 V VI = 8 V VI = 18 V 1 1 OUTPUT CURRENT, I O () (C) Figure. Typical JC1 Output Characteristics at Room Temperature OUTPUT CURRENT, I O () 8-11 (C) Figure 8. Typical JC7 Coverter Efficiecy vs. Output Curret at Room Temperature Lieage Power

7 JC, JC7, JC1 Power Modules: dc-dc Coverters; 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W Characteristic Curves (cotiued) EFFICIENCY, η (%) VI = 18 V VI = 8 V VI = 3 V OUTPUT CURRENT, I O () 8-1 (C) Figure 9. Typical JC1 Coverter Efficiecy vs. Output Curret at Room Temperature OUTPUT VOLTGE, VO (V) (1 mv/div) CURRENT, IO () ( /div) OUTPUT TIME, t ( µs/div) (C) Figure 11.Typical JC1 Trasiet Respose to Step Decrease i Load from % to % of Full Load at Room Temperature ad 8 V Iput (Waveform veraged to Elimiate Ripple Compoet.) OUTPUT VOLTGE, VO (V) ( mv/div) 18 V 8 V 3 V OUTPUT VOLTGE, VO (V) (1 mv/div) CURRENT, IO () ( /div) OUTPUT TIME, t μs/div) ( (C) Figure 1.Typical JC1 Output Ripple Voltage at Room Temperature ad Output TIME, t ( µs/div) (C) Figure 1.Typical JC1 Trasiet Respose to Step Icrease i Load from % to 7% of Full Load at Room Temperature ad 8 V Iput (Waveform veraged to Elimiate Ripple Compoet.) Lieage Power 7

8 JC, JC7, JC1 Power Modules: dc-dc Coverters; 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W Characteristic Curves (cotiued) COPPER STRIP VO(+) REMOTE ON/OFF VOLTGE, V ON/OFF (V) OUTPUT VOLTGE, Vo (V) (1 V/div) TIME, t ( ms/div) Figure 13.Typical Start-Up from Remote O/Off JC11; IO = Full Load 8-13 (C) VO( ) 8-13 (C).d Note: Use a 1. µf ceramic capacitor ad a 1 µf alumium or tatalum capacitor. Scope measuremet should be made usig a BNC socket. Positio the load betwee 1 mm ad 7 mm ( i. ad 3 i.) from the module. Figure 1. Peak-to-Peak Output Noise Measuremet Test Setup SUPPLY I I 1. µf VI(+) 1 µf SENSE(+) VO(+) SCOPE RESISTIVE LOD CONTCT ND DISTRIBUTION LOSSES I O LOD Test Cofiguratios CONTCT RESISTNCE VI( ) VO( ) SENSE( ) TO OSCILLOSCOPE LTEST 1 µh CURRENT PROBE VI(+) 8-79 (C) Note: ll measuremets are take at the module termials. Whe socketig, place Kelvi coectios at module termials to avoid measuremet errors due to socket cotact resistace. BTTERY CS µf ESR <.1 C, 1 khz 33 µf ESR <.7 1 khz VI( ) 8-3 (C).l Note: Measure iput reflected-ripple curret with a simulated source iductace (LTEST) of 1 µh. Capacitor CS offsets possible battery impedace. Measure curret as show above. Figure 1. Iput Reflected-Ripple Test Setup [Vo(+) Vo(-)]Io η = [Vi(+) Vi(-)]Ii Figure 1. Output Voltage ad Efficiecy Measuremet Test Setup 8 Lieage Power

9 JC, JC7, JC1 Power Modules: dc-dc Coverters; 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W Desig Cosideratios Iput Source Impedace Feature Descriptios Remote O/Off The power module should be coected to a low ac-impedace iput source. Highly iductive source impedaces ca affect the stability of the power module. For the test cofiguratio i Figure 1, a 33 µf electrolytic capacitor (ESR <.7 Ω at 1 khz) mouted close to the power module helps esure stability of the uit. For other highly iductive source impedaces, cosult the factory for further applicatio guidelies. Safety Cosideratios For safety-agecy approval of the system i which the power module is used, the power module must be istalled i compliace with the spacig ad separatio requiremets of the ed-use safety agecy stadard, i.e., UL-19, CS.-9, ad EN9. For the coverter output to be cosidered meetig the requiremets of safety extra-low voltage (SELV), the iput must meet SELV requiremets. If the iput meets extra-low voltage (ELV) requiremets, the the coverter s output is cosidered ELV. The iput to these uits is to be provided with a maximum ormal-blow fuse i the ugrouded lead. Electrical Descriptios Curret Limit To provide protectio i a fault (output overload) coditio, the uit is equipped with iteral curret-limitig circuitry ad ca edure curret limitig for a ulimited duratio. t the poit of curret-limit iceptio, the uit shifts from voltage cotrol to curret cotrol. If the coutput voltage is pulled very low durig a severe fault, the curret-limit circuit ca exhibit either foldback or tailout characteristics (output curret decrease or icrease). The uit operates ormally oce the output curret is brought back ito its specified rage. Two remote o/off optios are available. Positive logic remote o/off turs the module o durig a logic-high voltage o the ON/OFF pi, ad off durig a logic low. Negative logic remote o/off turs the module off durig a logic high ad o durig a logic low. Negative logic (code suffix 1 ) is the factory-preferred cofiguratio. To tur the power module o ad off, the user must supply a switch to cotrol the voltage betwee the o/ off termial ad the VI(-) termial (Vo/off). The switch ca be a ope collector or equivalet (see Figure 17). logic low is Vo/off = V to 1. V. The maximum Io/off durig a logic low is 1 m. The switch should maitai a logic-low voltage while sikig 1 m. Durig a logic high, the maximum Vo/off geerated by the power module is 1 V. The maximum allowable leakage curret of the switch at Vo/off = 1 V is μ. If ot usig the remote o/off feature, do oe of the followig: For egative logic, short ON/OFF pi to VI(-) For positive logic, leave ON/OFF pi ope. Io/off + Vo/off Figure 17. Remote O/Off Implemetatio Remote Sese ON/OFF VI(+) VI( ) SENSE(+) VO(+) VO( ) SENSE( ) LOD 8-7 (C).c Remote sese miimizes the effects of distributio losses by regulatig the voltage at the remote-sese coectios. The voltage betwee the remote-sese pis ad the output termials must ot exceed the output voltage sese rage give i the Feature Specificatios table, i.e.: [VO(+) VO( )] [SENSE(+) SENSE( )]. V Lieage Power 9

10 JC, JC7, JC1 Power Modules: dc-dc Coverters; 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W Feature Descriptios (cotiued) Remote Sese (cotiued) The voltage betwee the VO(+) ad VO( ) termials must ot exceed.9 V. This limit icludes ay icrease i voltage due to remote-sese compesatio ad output voltage set-poit adjustmet (trim), see Figure 18. If ot usig the remote-sese feature to regulate the output at the poit of load, the coect SENSE(+) to VO(+) ad SENSE(-) to VO(-) at the module. Figure 18. SUPPLY II CONTCT RESISTNCE VI(+) VI( ) SENSE(+) SENSE( ) VO(+) VO( ) IO LOD CONTCT ND DISTRIBUTION LOSSES 8-1 (C).h Effective Circuit Cofiguratio for Sigle-Module Remote-Sese Operatio The test results for this cofiguratio are displayed i Figure. The voltage betwee the VO(+) ad VO( ) termials must ot exceed.9 V. This limit icludes ay icrease i voltage due to remote-sese compesatio ad output voltage set-poit adjustmet (trim). See Figure 18. If ot usig the trim feature, leave the TRIM pi ope. VI(+) ON/OFF CSE VI( ) VO(+) SENSE(+) TRIM SENSE( ) VO( ) Radj-dow RLOD Figure 19. Circuit Cofiguratio to Decrease Output Voltage 8-78 (C).c Output Voltage Set-Poit djustmet (Trim) Output voltage trim allows the user to icrease or decrease the output voltage set poit of a module. This is accomplished by coectig a exteral resistor betwee the TRIM pi ad either the SENSE(+) or SENSE( ) pis. With a exteral resistor betwee the TRIM ad SENSE( ) pis (Radj-dow), the output voltage set poit (Vo, adj) decreases (see Figure 19). The followig equatio determies the required exteral-resistor value to obtai a percetage output voltage chage of Δ%. 1 Radj-dow = kω Δ% The test results for this cofiguratio are displayed i Figure. This figure applies to all output voltages. With a exteral resistor coected betwee the TRIM ad SENSE(+) pis (Radj-up), the output voltage set poit (VO, adj) icreases (see Figure 1). The followig equatio determies the required exteral-resistor value to obtai a percetage output voltage chage of Δ%. Radj-up VO( 1 + Δ% ) ( 1 + Δ% ) = kω 1.Δ% Δ% DJUSTMENT RESISTOR VLUE (Ω) 1M 1k 1k 1k % CHNGE IN OUTPUT VOLTGE (Δ%) Figure. Resistor Selectio for Decreased Output Voltage (C) 1 Lieage Power

11 JC, JC7, JC1 Power Modules: dc-dc Coverters; 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W Feature Descriptios (cotiued) Overtermperature Protectio (Shutdow) Output Voltage Set-Poit djustmet (Trim) (cotiued) VI(+) ON/OFF CSE VI( ) Figure 1. Circuit Cofiguratio to Icrease Output Voltage 1M VO(+) SENSE(+) TRIM SENSE( ) VO( ) Radj-up RLOD 8-71 (C).d The 1 W module features a overtemperature protectio circuit to safeguard agaist thermal damage. The circuit shuts dow the module whe the maximum case temperature is exceeded. The module restarts automatically after coolig. Thermal Cosideratios Itroductio The power modules operate i a variety of thermal eviromets; however, sufficiet coolig should be provided to help esure reliable operatio of the uit. Heat-dissipatig compoets iside the uit are thermally coupled to the case. Heat is removed by coductio, covectio,a d radiatio to the surroudig eviromet. Proper coolig ca be verified by measurig the case temperature. Peak temperature (Tc) occurs at the positio idicated i Figure 3. DJUSTMENT RESISTOR VLUE (Ω) 1M 1k 7. (.3) 38. (1.) MESURE CSE TEMPERTURE HERE VI(+) VO(+) ON/OFF + SEN TRIM CSE SEN 1k 8 1 % CHNGE IN OUTPUT VOLTGE (Δ%) 8-88a Figure. Resistor Selectio for Icreased Output Voltage Output Overvoltage Clamp The ouput overvoltage clamp cosists of cotrol circuitry, idepedet of the primary regulatio loop, that moitors the voltage o the output termials. The cotrol loop of the clamp has a higher voltage set poit tha the primary loop (see Feature specificatios table). this provides a redudat voltage cotrol that reduces the risk of output overvoltage. VI( ) VO( ) Note: Top view, pi locatios are for referece. Measuremets show i millimeters ad (iches). Figure 3. Case Temperature Measuremet Locatio 8-71 (C).f The temperature at this locatio should ot exceed 1 C. The output power of the module should ot exceed the rated power for the module as listed i the Orderig Iformatio table. lthough the maximum case temperature of the power modules is 1 C, you ca limit this temperature to a lower value for extremely high reliability. For additioal iformatio o these modules, refer to the Thermal Maagemet JC-, JFC-, JW-, ad JFW-Series W to 1 W Board-Mouted Power Modules Techical Note (TN97-8EPS). Lieage Power 11

12 JC, JC7, JC1 Power Modules: dc-dc Coverters; 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W Thermal cosideratios (cotiued) Heat Trasfer Without Heat Siks Icreasig airflow over the module ehaces the heat trasfer via covectio. Figure shows the maximum power that ca be dissipated by the module without exceedig the maximum case temperature versus local ambiet temperature (T) for atural covectio through m/s (8 ft./mi.). Note that the atural covectio coditio was measured at. m/s to.1 m/s (1 ft./mi. to ft./mi.); however, systems i which these power modules may be used typically geerate atural covectio airflow rates of.3 m/s ( ft./mi.) due to other heat dissipatig compoets i the system. The use of Figure is show i the followig example. POWER DISSIPTION, PD (W) VI = 3 V VI = 7 V VI = 18 V OUTPUT CURRENT, IO () Figure. JC Power Dissipatio vs. Output Curret 1 8- Example What is the miimum airflow ecessary for a JC1 operatig at omial lie, a output curret of, ad a maximum ambiet temperature of C? Solutio Give: VI = 8 V IO = T = C Determie PD (Use Figure 7.): PD =.8 W Determie airflow (v) (Use Figure.): v =.7 m/s ( ft./mi.) POWER DISSIPTION, PD (W) m/s(8 ft./mi 3. m/s(7 ft./mi 3. m/s( ft./mi. m/s ( ft./mi. m/s ( ft./mi 1. m/s(3 ft./mi 1. m/s( ft./mi. m/s(1 ft./mi.1 m/s (NT. CONV.) ( ft./mi.) LOCL MBIENT TEMPERTURE, T ( C) 8-11 (C).a Figure. Forced Covectio Power Deratig with No Heat Sik; Either Orietatio POWER DISSIPTION, PD (W) VI = 18 V VI = 8 V VI = 3 V OUTPUT CURRENT, I O () Figure. JC7 Power Dissipatio vs. Output Curret POWER DISSIPTION, PD (W) VI = 3 V VI = 8 V VI = 18 V OUTPUT CURRENT, I O () Figure 7. JC1 Power Dissipatio vs. Output Curret Lieage Power

13 JC, JC7, JC1 Power Modules: dc-dc Coverters; 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W Thermal Cosideratios (cotiued) Heat Trasfer with Heat Siks The power modules have through-threaded, M3 x. moutig holes, which eable heat siks or cold plates to attach to the module. The moutig torque must ot exceed. N m ( i. lb.). For a screw attachmet from the pi side, the recommeded hole size o the customer s PWB aroud the moutig holes is.13 ±. iches. If a larger hole is used, the moutig torque from the pi side must ot exceed. N m (. i. lb.). Thermal deratig with heat siks is expressed by usig the overall thermal resistace of the module. Total module thermal resistace (θca) is defied as the maximum case temperature rise (ΔTC, max) divided by the module power dissipatio (PD): ΔTC, max ( TC T) θca = = PD PD The locatio to measure case temperature (TC) is show i Figure 3. Case-to-ambiet thermal resistace vs. airflow is show, for various heat sik cofiguratios ad heights, i Figure 8. These curves were obtaied by experimetal testig of heat siks, which are offered i the product catalog. thermal-coductive dry pad betwee the case ad the heat sik to miimize cotact resistace. The use of Figure 8 is show i the followig example Example If a 8 C case temperature is desired, what is the miimum airflow ecessary? ssume the JC1 module is operatig at omial lie ad a output curret of, maximum ambiet air temperature of C, ad the heat sik is. i. Solutio Give: VI = 8 V IO = T = C TC = 8 C Heat sik =. i. Determie PD by usig Figure 7: PD =.8 W The solve the followig equatio: θca θca = = ( TC T) PD ( 8 ) CSE-TO-MBIENT THERML RESISTNCE, RC ( C/W) / IN HET SINK 1 IN HET SINK 1/ IN HET SINK 1/ IN HET SINK NO HET SINK θca = 1.97 C/W Use Figure 8 to determie air velocity for the. ich heat sik. The miimum airflow ecessary for the JC1 module is. m/s ( ft./mi.).. (1) 1. () 1. (3). (). () 3. () IR VELOCITY MESURED IN m/s (ft./mi.) Figure 8. Case-to-mbiet Thermal Resistace Curves; Either Orietatio These measured resistaces are from heat trasfer from the sides ad bottom of the module as well as the top side with the attached heat sik; therefore, the case-to-ambiet thermal resistaces show are geerally lower tha the resistace of the heat sik by itself. The module used to collect the data i Figure 8 had a Lieage Power 13

14 JC, JC7, JC1 Power Modules: dc-dc Coverters; 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W Thermal Cosideratios (cotiued) Custom Heat Siks more detailed model ca be used to determie the required thermal resistace of a heat sik to provide ecessary coolig. The total module resistace ca be separated ito a resistace from case-to-sik (θcs) ad sik-to-ambiet (θsa) show below (Figure 9). PD TC TS T θcs θsa Figure 9. Resistace from Case-to-Sik ad Sik-to-mbiet 8-13 For a maaged iterface usig thermal grease or foils, a value of θcs =.1 C/W to.3 C/W is typical. The solutio for heat sik resistace is: θsa = ( TC T) PD θcs This equatio assumes that all dissipated power must be shed by the heat sik. Depedig o the userdefied applicatio eviromet, a more accurate model, icludig heat trasfer from the sides ad bottom of the module, ca be used. This equatio provides a coservative estimate for such istaces. Layout Cosideratios Copper paths must ot be routed beeath the power module moutig iserts. 1 Lieage Power

15 JC, JC7, JC1 Power Modules: dc-dc Coverters; 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W Outlie Diagram Dimesios are i millimeters ad (iches). Toleraces: x.x mm ±. mm (x.xx i. ±. i.) x.xx mm ±. mm (x.xxx i. ±.1 i.) Top View 7.9 (.8) MX 1. (.) MX Side View SIDE LBEL* 1.7 ±. (. ±.).1 (.) MIN 1. (.) DI SOLDER-PLTED BRSS, 7 PLCS. (.81) DI SOLDER-PLTED BRSS, PLCES (OUTPUT ND +OUTPUT) Bottom View.1 (.) 1.7 (.) MOUNTING INSERTS M3 x. THROUGH, PLCES.8 (.) 3. (1.) 1.1 (.). (1.) VI ( ) VO ( ) CSE SEN TRIM ON/OFF +SEN 1.1 (.) (.7). (1.) 3. (1.) VI (+) 8. (1.9) VO (+).8 (.19) 8.3 (1.9) * Side labels iclude Lieage ame, product desigatio, safety agecy markigs, iput/output voltage ad curret ratigs, ad bar code Lieage Power

16 JC, JC7, JC1 Power Modules: dc-dc Coverters 18 Vdc to 3 Vdc Iput, Vdc Output; W to 1 W Recommeded Hole Patter Compoet-side footprit. Dimesios are i millimeters ad (iches)..8 (.19) 7.9 (.8) MX 8.3 (1.9) 8. VI (+) (1.9) VO (+) 3. (1.) ON/OFF +SEN 3. (1.).8 (.). (1.) 1.1 (.) CSE VI ( ) TRIM SEN VO ( ) 1.1 (.). (1.) (.7) 1. (.) MX.1 (.) 1.7 (.) MODULE OUTLINE MOUNTING INSERTS 3.3 ±.1 (.13 ±.) 8-19 Orderig Iformatio Iput Voltage Output Voltage Output Power Remote O/ Off Logic Device Code Comcode 8 V. V W egative JC V. V 7 W egative JC V. V 1 W egative JC V. V W positive JC V. V 7 W positive JC V. V 1 W positive JC sia-pacific Headquarters Tel: World Wide Headquarters Lieage Power Corporatio 3 Skylie Drive, Mesquite, TX 719, US (Outsid e U.S..: ) e-m ail: techsupport1@liea gepower.com Europe, Middle-East ad frica Headquarters Tel: Idia Headquarters Tel: Lieage Power reserves the right to make chages to the product(s) or iformatio cotaied herei without otice. No liability is assumed as a result of their use or applicatio. No rights uder ay patet accompay the sale of ay such product(s) or iformatio. 8 Lieage Power Corporatio, (Mesquite, Texas) ll Iteratioal Rights Reserved. DS97-1EPS