Design of Double Gate Vertical MOSFET using Silicon On Insulator (SOI) Technology

Transcription

1 Iteratioal Joural of Nao Devices, Sesors ad Systems (IJ-Nao) Volume 1, No. 1, May 2012, pp Desig of Double Gate Vertical MOSFET usig lico O Isulator () Techology Jatmiko E. Suseo 1,2* ad Razali Ismail 2 ARTICLE INFO Article history: Received April 27, 2012 Revised May 14, 2012 Accepted May 26, 2012 Keyword: Double gate,, parasitic capacitace, vertical MOSFETs ABSTRACT Applicatio of symmetric double gate vertical metal oxide semicoductor field effect trasistors (MOSFETs) is hidered by the parasitic overlap capacitace associated with their layout, which is cosiderably larger tha for a lateral MOSFET o the same techology ode. A simple process simulatio has bee developed to reduce the parasitic overlap capacitace i the double gate vertical MOSFETs by usig (lico o Isulator) i bottom plaar surfaces side. The result shows that while chael legth decreases, the threshold voltage goes lower, the DIBL rises ad subthreshold swig teds to decrease, for both structures. It is oted that the DG VMOSFET structure geerally have better performace i SCE cotrol compared to bulk vertical MOSFET. The presece of buried oxide is believed to icrease the performace of vertical MOSFET, essetially i cotrollig the depletio i subthreshold voltage Isitute of Advaced Egieeerig ad Sciece. All rights reserved. Affiliatio 1 Physics Departmet, Dipoegoro Uiversity, Semarag, 50271, Idoesia 2 Faculty of Electrical Egieerig, Uiversiti Tekologi Malaysia Skudai, Johor, Malaysia *Correspodig author, address: jatmikoedro@yahoo.com 1. INTRODUCTION Dimesios of MOSFET are cotiually scaled to be smaller to improve performace ad package desity. This dowscalig makes the structure of MOSFET requires modificatio. O the other had, several isues arise, icludig problems i the lithography to achieve reproducibly fie dimesios. Moreover, source ad drai egieerig is eeded to reduce device parasitic, as well as chael egieerig to cotrol shortchael effects. Vertical MOSFETs are structures with promisig performace to replace maistream lateral devices. A vertical trasistor techology would raise the package desity, could avoid the lithography problem for the gate layer, ad ope ew ways for optimizig the dopig profile usig epitaxial layers deposited with atomic layer thickess cotrol ad various dopig cocetratios. Oe variat of vertical MOSFET structures is a double gate vertical MOSFET that has a simpler process [1]. There are some advatages of vertical MOSFETs. First, the chael legth defiitio of the vertical MOS trasistor is ot depedet o the use of lithography. Secod, vertical MOS trasistors are easily made with both frot ad back gates aliged. Third advatage of the vertical MOSFET is the possibility to prevet short chael effects from domiatig the trasistor by addig processes, such as a to reduce parasitic bipolar effects or a dielectric pocket to reduce drai iduced barrier lowerig (DIBL). [2-5] The reductio of Joural homepage: ISSN:

2 JE. Suseo ad R. Ismail, Desig of DG Vertical MOSFET usig Techology 35 overlap capacitace of the gate with drai, source ad body regios is a recurrig theme i recet research. However, several approaches have bee proposed to reduce overlap capacitace i vertical MOS devices, icludig selective epitaxy [6], replacemet gate [7] ad fillet local oxidatio (FILOX) [8]. I this paper, a double gate vertical trasistor usig lico o Isulator () formatio will be proposed. With additio of, this structure tries to reduce the high parasitic capacitace that emerges especially for the gate to bottom electrode capacitace i io implated vertical MOSFETs. 2. DEVICE STRUCTURES AND SIMULATION For compariso ad performace evaluatio, two trasistor structures have bee desiged: Double Gate Vertical MOSFET without (Fig. 1a.) ad with (Fig. 1b.). Figure 1a. represets a double gate vertical trasistor with a simpler process that has bee itroduced i [1]. This device defies source ad drai by io implatatio. The layout of trasistor is highly compatible with plaar devices. Such a device is especially attractive as the cell trasistor i a memory, because the chael ca be made log for good off characteristics without cosumig too much area [9,10]. Moreover a bulk cotact is available which prevets floatig body effects. Like plaar trasistors the devices achieve high trascoductace values due to the sub lithographic defiitio of the chael legth. However, this device have oe importat disadvatage, which is higher overlap capacitaces tha covetioal lateral devices, which has made them less competitive compared with their lateral couterpart. Overlap capacitaces are determied o trasistors ad gates fabricated with the formatio process ad compared with values o comparable without the formatio trasistors. It is show that a vertical, with architecture gives a lower gate/source overlap capacitace tha obtaied i comparable device without. Figure 1b. shows the double gate vertical trasistor desig icludig the cocepts which device structures ad simulatio of the proposed symmetric NMOSFET are as follows. DRAIN GATE t ox=2m Lg t = 4 m SOURCE p-substrate a. b. Fig. 1. A Double Gate (DG) Vertical MOSFET structures layout (a) Without (b) With A double gate vertical MOSFET with process were simulated usig the Atlas lvaco TCAD simulator. The process uses silico-o isulator wafer cofiguratio. Boro-doped ( cm 3 ) wafers (100) served as the startig material. The process flow for the fabricatio of the devices is preseted i Fig. 2. The first step, after the field isolatio a 20-m thick Nitride layer is deposited, usig a lithography mask to defie the vertical islad by aisotropic dry etchig with deep cotrol etchig to create 20 m silico thickess (t si ) outside the silico pillar area, as show i fig. 2a. The heights of pillar (133 to 160 m) were chose to provide fial chael legths i the rage of 50 m to 125 m. Next, itride mask is removed (Fig. 2b), after that gate oxide is grow o the vertical sidewall. The thickess of the fial gate oxide is 2 m (950 C, 1 mi, dry O 2 ). The, a 40 m thick poly- film is deposited ad pattered by a plasma etchig techology to form the gate electrode (Fig. 2c). Later, the source ad drai areas were implated with arseic at a dose of cm -3 ad eergy of 35keV, the device is as show i figure 2d. The ext step is to create the smart cotact betwee the source ad the body. To begi with, a passivatio layer is deposited. Usig lithography, we the etch the source/body ad source/drai cotacts. Oce metallizatio is applied, the double gate vertical MOSFET with is complete.

3 Drai Curret (ma) 36 IJ-NANO Vol. 1, No.1, May 2012, pp mulatio of the double gate vertical MOSFET were proposed with its advatages such as cotrol juctio leakage ad thereby suppress SCEs. Therefore the advatage of the proposed a double gate vertical MOSFET is outlied ad associated with fabricatio process. 3N4 a. b. drai source gate p d. c. Fig. 2. Process flow for the double gate vertical MOSFET: (a) Trech Etchig, (b) Nitride Mask Removig, (c). Gate Oxide Growth & Gate Depositio, ad (d) Gate Patterig & S/D Implatatio. 3. RESULTS AND DISCUSSION By the compariso of Double Gate Vertical (DGV) MOSFET with ad without, figure 3-6 show differet result for both structures. The output characteristics of the examied structures are show i Fig. 3. I this graph illustrates the output characteristic of the device values of gate voltage ad demostrates the expected behaviour. Device with has a higher saturatio curret tha device without Vg=3.3V 2.0 With Vg=2.2V 0.5 Without Vg=1.1V Drai Voltage (V) Fig. 3. Id Vd Characteristics Graph with Lg=75 m

4 DIBL Threshold Voltage (V) JE. Suseo ad R. Ismail, Desig of DG Vertical MOSFET usig Techology Chael Legth (m) Fig. 4. Threshold Voltage (Vth) Graph of device with Vd=0.1 V Chael Legth (m) Fig. 5. DIBL Graph For similar cocetratio ad other parameters of both structures, Fig. 4 shows that device with has a slightly larger threshold voltage. Moreover, Fig. 5 also reveals a slightly higher DIBL compared to device without structure. The buried oxide () of device will be less charge sharig withi the regio cotrolled by the source ad it also implies that the depletio regio cotrolled by the gate will be larger. This pheomeo is especially sigificat i short chael devices, where it is foud to improve the threshold roll-off of the DGVMOS i compariso to the DGVMOS without. The threshold voltage of DGVMOS is smaller tha DGVMOS without. It is suppose that the great threshold voltage degradatio is caused by couplig betwee source ad gate makes device much more sesitive to charge trappig so that cotribute to V th reductio. The DIBL of device without is lower because at device with, suppressig SCEs by regio that cofied betwee gate oxide ad therefore reducig the ecroachmet of the drai s electric field. If chael legth of device is small (for 50 m ad 75 m), DIBL of device with is smaller tha device without although both device are very close. Thus the process allows to fabricate double gate vertical MOSFETs with overlap capacitace values much lower tha the traditioal vertical devices ad similar to the lateral techology. 4. CONCLUSION The simulatios ad experimetal results preseted here illustrate the successful implemetatio of a techique for a double gate vertical MOSFET with. The study has suggested that the vertical MOSFETs with provide better SCEs compared to the juctio leakage cotrol devices. It uses double gate gate cofiguratio, drai-o-top structure fabricated o wafer with substrate thickess of 20 m

5 38 IJ-NANO Vol. 1, No.1, May 2012, pp over buried oxide. The source juctio depth reached all substrate thickess. This structure was compared with bulk vertical MOSFET, both of which were implated with arseic of cm -2, 35 kev, while the substrate cocetratio was cm -3, boro-doped. Some chael legths from m were compared ad aalyzed. The result shows that while chael legth decreases, the threshold voltage goes lower, ad the DIBL rises, for both structures. It is oted that the double gate vertical MOSFET structure geerally have better performace i SCE cotrol compared to bulk vertical MOSFET. The presece of buried oxide is believed to icrease the performace of vertical MOSFET, essetially i cotrollig the depletio i juctio regio. REFERENCES [1] T. Schulz, W. Röser, L. Risch, A. Korbel, ad U.Lagma, Short-Chael Vertical dewall MOSFETs, IEEE Trasactios o Electro Devices, vol. 48, o. 8 (2001). [2] Risch L., Krautscheider W.H., Hofma F., Schäfer H., Aeugle T., Röser W., Vertical MOS trasistors with 70 m chael legth, IEEE Tras. Electro Devices, vol 43, p1495 (1996) [3] Choi Y-K, Kig T-J, Hu C., Naoscale CMOS spacer FINFET for the terabit era, IEEE Electro Device Letters, vol 23; p (2002). [4] Gili E., Kuz V.D., de Groot C.H., Uchio T., Ashbur P. et al., gle double ad surroud gate vertical MOSFETs with reduced parasitic capacitace, Solid State Electroics, vol 48, p (2004) [5] P. Ashbur, D. Groot, Vertical MOSFET's, ac.uk/research/projects/116 [6] Moers J., Toesma A., Klaes D., Vesca L., VD. Hart A., Vertical silico MOSFETs based o selective epitaxial growth, Third It. Euro. Cof. O Adv. Semi. Devices ad Microsystems, p (2000) [7] Hergerother J.M., Moroe D., Klemes F.P. Korblit A. Weber G.R., The vertical replacemet-gate (VRG) MOSFET: a 50m vertical MOSFET with lithography-idepedet gate legth, IED, p (1999) [8] Kuz V.D., Uchio T., de Groot C.H., Ashbum P. et al., Reductio pf Parasitic Capacitace i Vertical MOSFETs by Spacer Oxidatio, IEEE Tras Electro Devices, 50(6); p (2003) [10] H. Takato et al., "High Performace CMOS Surroudig Gate Trasistor (SGT) for Ultra High Desity LSIs", IEDM Tech. Digest, pp (1988) [11] E. Bertagolli et al., "ROS: A Extremely High Desity Mask ROM Techology Based O Vertical Trasistor Cells.", Symp. o VLSI Tech. Digest, pp (1996)