PROCEED: A Pareto Optimization-based Circuit-level Evaluator for Emerging Devices

Transcription

1 PROCEED: A Pareto Optimizatio-based Circuit-level Evaluator for Emergig Devices Shaodi Wag, Adrew Pa, Chi O Chui, ad Pueet Gupta Departmet of Electrical Egieerig Uiversity of Califoria, Los Ageles Los Ageles, CA shaodiwag@g.ucla.edu Abstract Evaluatio of ovel devices i a circuit cotext is crucial to idetifyig ad maximizig their value. We propose a ew framework, PROCEED, ad metrics for accurate device-circuit co-evaluatio through proper optimizatio of digital circuit bechmarks. PROCEED assesses techology suitability over a wide operatig regio (MHz to GHz) by leveragig available circuit kobs (V t assigmet, power maagemet, sizig, etc.) ad improves accuracy by 3 to 5 compared to existig methods while offerig orders of magitude improvemets i rutime over full physical desig implemetatio flows. o illustrate PROCEED s capabilities, we deploy it to assess ovel tuelig trasistors (FEs) compared to covetioal CMOS. Idex erms uelig trasistor (FE), silico-o-isulator (SOI), circuit-level device evaluatio, Pareto optimizatio, simulatio-based optimizatio. I. INRODUCION As traditioal silico devices approach their fudametal limits, it is importat to explore additios or alteratives to CMOS. o do so, it is essetial to systematically compare emergig devices i the cotext of the circuits they would be used to build. May techology bechmarkig methods have bee proposed to meet this eed []-[9]; ufortuately, as summarized i able I, all those methods are iadequate due to eglect of various essetial circuit features, ay oe of which ca dramatically alter the bechmarkig coclusios. Because of the variety ad complexity of moder circuits, devices ad circuit desigs must be carefully chose to complemet each other before assessig viability; this requires a level of flexibility i the bechmarkig process that has ot existed util ow. Device/circuit assessmets must cosider several factors to draw realistic coclusios. For istace, effective evaluatios should examie the power-delay (PD) tradeoff over several orders of magitude sice moder circuits performaces spa a wide rage from KHz to GHz frequecies. For a particular circuit to be properly used, crucial tuig kobs such as logic gate sizig or supply voltage (V dd ) or threshold voltage (V t ) selectio must be optimized. I additio, sice circuit performace depeds critically o the chose device operatig poit, bechmarks should cosider the full device I-V characteristics rather tha oly simple device metrics like saturatio curret or off-state leakage I off. A give device may ot be suitable for all circuit architectures because of variatios i logic depth histogram (LDH) patters ad logical or physical structure. Such adaptivity ad circuit topology must be cosidered i ay assessmet. Meawhile, as techologies scale dow, device variability from ambiet process fluctuatios becomes ever more importat ad impacts circuit viability. Such complexities might seem to require a complete circuit desig flow, but that is impractically time-cosumig. hus, alterative evaluatio method must be used which accouts for the above factors with reasoable computatioal ru time. o meet these eeds, we propose a ew device evaluatio framework, PROCEED (PaReto Optimizatio-based Circuit-level Evaluator for Emergig Devices), for fully circuit-aware bechmarkig. It icorporates typical circuit desig flow flexibilities ad tues physically adjustable device ad circuit parameters to geerate realistic coclusios about the combied device-circuit performace. PROCEED remedies the flaws eumerated above i several ways: () We use Pareto curves to aalyze PD tradeoff over a realistically wide rage of power ad performace. () he rage ad umber of V t as well as rage of logic gate sizes are iputs to PROCEED, ad the evaluatio circuit bechmarks ca use oe or several V dd supply voltages, i accord with realistic desigs. able COMPARISON OF VARIABLES CONSIDERED IN BENCHMARK MEHODOLOGIES IN HE LIERAURE Methodologies: Ref. [] Ref. [,] Ref. [3-] Ref. [5] Ref. [6] Ref. [7] Ref. [8] Ref. [9] PROCEED Metrics Bechmark Circuit CV/I, CV, /I off Latch, Iverter Chai PD Pareto Curves, /I off PD Pareto Curves Clock SS, Eergy, Clock P P P Device Iverter Chai CV/I, CV, Model Power, Delay Small Logic Elemets CPI P PD Pareto Curves Arbitrary Circuit (P here) Power maagemet V DD, V t V DD oly Optimizatio Kobs Circuit Coditios Size Multiple V DD, V t Itercoect LDH* Activity Device Curret, I half, I half CAD Model Model R o, R off Compact Model Model Capacitace Fixed Fixed Full C-V Fixed N/A Fixed Full C-V - Full C-V *LDH: Logic depth histogram (Usig slack histogram to estimate)

2 Logic Depth Bi 5 6 Bi Bi 3 8 Bi Short paths Bi... Sigle stage Log paths (a) S 5... S 5 S... S S 3... S 3 S... S S... S Fa-out Gate Iverter Sigal i stage... stage Simulatio block Sigal out Fig.. Overview of PROCEED framework. (3) o properly accout for device operatio at each bias, we utilize compact or lookup table-based full device models. () o assess circuit topology, the full chip characteristics are cosidered icludig LDH, itercoect loads, activity factor (i.e. average gate toggle rate) ad average fa-out. (5) We aalyze the circuit impact of device variability due to factors like radom dopat fluctuatio (RDF) ad parasitic voltage drops by calculatig delay for logic gates evaluated at differet variatio corers. (6) For computatioal efficiecy, we adopt scalable Pareto optimizatio techiques. (7) Power gatig ad dyamic voltage ad frequecy scalig (DVFS) are modeled to assess power maagemet ad scalig. I this paper, we describe the PROCEED framework ad, as a case study, deploy it to compare a traditioal techology, silico-o-isulator (SOI), with the ovel tuelig FE (FE). he FE is a ew device cocept curretly drawig itese iterest because of its potetial for highly eergy efficiet operatio due to its steep subthreshold switchig []. However, comprehesive assessmets of its system-level performace are still lackig; therefore we perform a microprocessor-level study of the SOI bechmark techologies ad elucidate their respective stregths ad disadvatages. We outlie the methodology behid PROCEED i sectio II, ad explai details of the Pareto optimizatio procedure i sectio III. We preset results of our PROCEED study o FE ad SOI devices i sectio IV ad summarize our coclusios i sectio V. II. OVERVIEW OF PROCEED FRAMEWORK As show i Fig., typical iputs to PROCEED iclude itercoect iformatio (icludig average wire resistace ad capacitace (RC) ad chip size), bechmark desig (i.e. desig LDH ad average fa-out), variability (through supply voltage Fig. ypical logic path depth distributio ad logic path delay extracted from a sythesized CortexM. Itercoect (b) Fig. 3 Circuit schematic for simulatio ad optimizatio. drops, threshold voltage shifts, etc.), a full device model, operatig activity, ad optioal costraits o V dd, V t, chip area, ad ratio of average to peak throughput. With iput ad feedback from the Pareto optimizer (through tuig parameters like V dd, V t, ad gate sizes), the eeded simulatio blocks with itercoect loads are created i the caoical circuit costructio process. Optimized results are geerated i the form of the PD Pareto curve. Fially, power maagemet aalysis icludig DVFS ad power gatig is performed based o this Pareto curve. As presetly implemeted, PROCEED is capable of evaluatig a arbitrary device cadidate as log as it does ot cause a dramatic chage i circuit topology. For istace, multistate logic devices fall outside PROCEED s preset scope of use because of the ucovetioal circuit architectures withi which they must operate. A. Caoical Circuit Costructio S i i stages Full, exact optimizatio is a impossible job for large digital circuits. Sice the goal of our approach is to predict the best performace ad power tradeoffs for emergig devices, detailed circuit desig is thus ot our target ad cotributes little to evaluatio. We utilize therefore oly essetial desig iformatio to maximize performace ad determie the optimal V dd, V t, ad gate sizes at a give power. A typical circuit desig cotais both log ad short logic paths ad the path delay is usually proportioal to the logic depth, as show i Fig.. Hece we derive the LDH by extractig edpoit slacks from bechmark desigs ad estimatig logic paths. I Fig. 3, we show a example of the simulatio blocks used to costruct a specific circuit. For simplicity, we first divide logic paths ito bis based o logic depth; i Fig. 3(a), for istace, = 5. More bis improve accuracy at the expese of computatio time. Each bi is modeled by the correspodig simulatio blocks S i (S -S 5 i Fig. 3(a)), which are i tur made of i gate stages. We use the gate desig for S i to costruct logic paths belogig to a give bi i. he LDH is divided such that the logest path i each bi has the same delay if all these blocks have the same delay. Fig. 3 shows a example of this, with five evely spaced bis for logic paths from oe to twety stages such that the first bi cotais oe to four stage paths, the secod holds paths with five to eight stages, ad so forth. he delay weight W D is the umber of copies of S i eeded to costruct the logest path i bi i (W D is i Fig. 3). he logic gate ad itercoect used for a sigle stage i the simulatio blocks is show i Fig. 3(b). he gate ca be NAND, NOR, or a more complicated gate like NOR, depedig o the average umber of trasistors per gate i a give bechmark. he gate choice ca also differ from bi to bi, though i this paper s examples we will

3 Relative itercoect load (a.u.) Delay (ps) 3 Cell area (m ) 8 6 Cell area vs. trasistor width NAND from DRE [9] INV from DRE [9] Model for NAND Model for INV 3 5 rasistor width (m) (a) use NAND gates for all bis. A iverter or buffer is iserted after the gate to drive the fa-out (which is a replica of the chose gate sized to average fa-out) as well as wires represeted by itercoect RC elemets. We have verified the reliability of the PROCEED results through compariso with commercial sythesis tools, as discussed i Sectio IV.A. B. Process Variatio ad Voltage Drop As devices scale to ever smaller techology odes, device variatios due to process ad ambiet variatios are becomig more importat ad should ot be eglected i PD evaluatio. I circuit desig, slow corer devices are commoly used to estimate the upper boud o delay ad create a safe desig with sufficiet delay margi. We defie the slow corer as a device with reduced effective V dd ad icreased V t due to variability ad parasitic effects; these voltage shifts are iputs to PROCEED. Separate models for other variability effects may be icorporated as eeded. Durig circuit optimizatio, delay is calculated usig the slow corer device while power is simulated with the ormal device to model the worst-case sceario. C. Itercoect Load We model itercoect loads usig a series RC circuit. o costruct load as a fuctio of gate width, we use UCLADRE [] to fid a relatio betwee cell area ad gate width, ad the fit liear models to each cell used i PROCEED. he model accuracy is demostrated i Fig. (a). We assume R ad C are liear with itercoect legth ad chip area is liear to cell area, so the load will be proportioal to the square root of the average cell area [], ad ca be dyamically chaged based o average gate width. Show i Fig. (b) is a example of itercoect load as a fuctio of trasistor width, usig a combied NAND ad INV cell to estimate the cell area. he average RC ad extracted gate width are the fed ito PROCEED. D. Pareto-Based Optimizatio Followig logic caoical circuit costructio, all logic paths are replaced by simulatio blocks (S i ) which will be optimized. However, these blocks caot be optimized separately because they usually share a commo V dd ad V t, complicatig the procedure. o perform the optimizatio we use a modified form of a geeral simulatio-based Pareto techique [3] which is discussed i more detail i Sectio III. he simulatio target is regarded as a black box with two optimizatio objectives: desig power P ad critical delay D (or miimum workig clock period). E. Power Maagemet Modelig Curret techologies usually allow circuits to operate i at least three modes: ormal, power savig, ad sleep mode. Previous evaluatio works oly cosidered the ormal mode whe devices Freely available for dowload at Model for itercoect legth. 3 5 rasistor width (m) Fig.. (a) Cell area ad (b) itercoect load as a fuctio of trasistor width. I (b), trasistor width is the same i Iverter ad NAND gate. (b) V DD (V) Fig. 5. Model fittig for simulatio block s delay ad power as a fuctio of V dd. cotiuously work at peak performace. PROCEED allows devices to also operate at a secod, lower supply V dd (DVFS) as well as i the off state (power gatig). his allows us to evaluate device PD scalability as a fuctio of V dd, a importat feature which, to the best of our kowledge, has bee igored i all previous evaluatios. he ratio of average to peak throughput is aother iput for PROCEED. o study power maagemet, we choose all desigs from the geerated Pareto poits which achieve the lowest power ad peak throughput. From this, the optimizer selects the best choice for the secod power rail ad divides the time spet operatig at high V dd (the origial supply) ad the ew lower V dd. his is doe as follows. Startig from the optimized desig (with maximized peak throughput), we carry out circuit simulatios by sweepig voltages lower tha the origial V dd. he origial desig may eve have multiple supply voltages, i which case differet blocks ca use differet V dd values. Delay ad power models for every simulatio block S i as fuctios of V dd are costructed usig polyomial fuctios, as i Fig. 5: 5 5 i i Si i, j, Si i, j () j j D V a V P V b V We have tested ad foud this model to be sufficietly accurate; for istace, i our experimets the relative error of the polyomial fittigs is less tha %. We the optimize for the weighted power sum f P + f P, subject to D W D V, P W P V i,,..., D Si i Pi Si i i f / D f / D, f f Ave Here D, ad P, are the delay ad power usig V dd,, W D ad W P are the delay ad power weight mappig from simulatio blocks to the desig, ad f ad f are the fractios of time spet operatig with V dd ad V dd with ay remaiig time assumed to be spet i the off state. ypically this step is ot a feasible covex optimizatio problem; however, by usig the fitted model of Eq. (), a eumeratio approach ca solve this problem very efficietly with acceptable accuracy. F. Activity Factor Model fit for delay ad power Symbols: Power ad delay data from simulatios Lies: Fittig models Activity varies widely with applicatio: i embedded sesig, for istace, factors below % are observed i car-park maagemet [], while those for systems like VigilNet exceed 5% [5]. Activity factor ca therefore dramatically chage evaluatio results ad is icluded as a iput to PROCEED. I circuit simulatios, the dyamic ad leakage power are separately extracted ad the total power is their weighted sum. From this the circuit ca be optimized for a kow activity factor. 5 5 Power (W) ()

4 Power Existig Poit New Poit D-P slope 3(b) Gradiet descet G. Multiple V dd ad V t I moder circuit desigs, multiple V dd ad V t values are used. I our scheme, trasistors i each simulatio block S i must be assiged the same voltages, so to optimize a desig with iteger m differet V dd or V t biases, the umber of simulatio blocks must be greater tha m. I additio, our optimizatio is a iterative process whereby Pareto poits are updated ad improved based o previous iteratios. herefore, if the same V dd or V t is shared by multiple simulatio blocks, this assigmet caot be chaged durig the optimizatio. A full optimizatio for multiple V dd ad V t is implemeted by cosiderig desigs with all sets of reasoable voltage assigmets i parallel. For example, if we have five simulatio blocks S -S 5 ad two available threshold voltages, the for i from to, blocks S to S i use the high V t ad S i+ to S 5 use the low V t. his comprises the set of useful voltage assigmets, sice simulatio blocks with loger logic paths require higher performace (lower V t ). III. PAREO OPIMIZAION Fig. 6 presets a overview of our Pareto optimizatio process. PROCEED treats circuit simulatios as a black box ad uses models to optimize tuig parameters based o the simulatio results. Gradiet descet is utilized to fid miimal objectives i the trust regio. Fial simulatios are performed o desigs outputted by the model-based optimizatio. he vector of tuig parameters for optimizatio is represeted as: x, x,..., xm,,..., dd, i t, i i i i,i y y y y V, V, W, W,..., W, i,... i (b) rust regio (a)buildig models: Start poit Simulate startig poit Buildig models (a) ad trust regio (b) Weighted sum 3(a) ad gradiet descet. 3(b) Simulate to evaluate ew poits ad update Pareto poits. D-P slope Existig Poit 3(a) Adaptive Weight is Pi PVDD,..., VDDk, V,..., Vl, W,..., Wp determied by slope of Di DVDD,..., VDDk, V,..., Vl, W,..., Wp existig Pareto Frots Delay Fig. 6 Optimizer overview. Adaptive weight is chose by slope of existig frots. Based o startig poit, meta-modelig is built ad gradiet descet is used to fid potetial poits. Simulate potetial poits to get ew Pareto poits. where V dd,i ad V t,i are the supply ad threshold voltages for simulatio block S i, W ij are sizes for gates ad iverters i S i, x j are the variables of, ad y i are vectors of the tuig parameter variables for S i. he optimizatio etails the followig steps: () Pickig a startig poit: each iteratio of the optimizatio process uses a startig set of variables aroud which to explore. For the first iteratio, ay reasoable may be iputted. he choice of the iitial poit may affect rutime but ot fial accuracy, sice bad poits will gradually be elimiated by the optimizatio process ad coverge to the true aswer. Subsequetly is determied from already existig Pareto poits by computig the Euclidea distace betwee all eighborig poits i delay/power coordiates, as show i Fig. 6. he poit with the (3) largest total distace from its two eighbors is chose as sice it lies i the sparse regio, which is usually suboptimal. () Buildig a local model aroud : o accelerate the optimizatio process, secod-order delay ad power models are costructed based o simulatio results. he delay ad power models D Si ad P Si for each block S i are calculated separately ad the combied to reduce the umber of simulatios, as determied by the size of the Hessia matrix (proportioal to the umber of variables squared). D Si ad P Si are represeted by the gradiet vector G Di ad Hessia matrix H D as DSi y i, + Δy i = DSi, + GDi Δyi Δyi H Di Δyi () PSi y i, + Δy i = PSi, + GPi Δyi Δyi H Pi Δyi his secod-order model is a local estimatio ear the startig poit. o guaratee validity, a adaptive trust regio is applied as show i Fig. 6, limitig the model rage iside the regio - λ( r) < < + λ( r) (5) where r is the radius of this trust regio ad λ is the rage of the tuig parameters ad is a liear fuctio of r. (3) Model-based optimizatio: I this step, four metrics are used i optimizatio: D, P, W dl D+W pl P, ad W dr D+W pr P. Miimizatio of D ad P yields the fastest ad lowest power desigs i the local regio, while the weighted sums of delay ad power are used to populate the phase space by fidig two Pareto poits betwee the startig poit ad its eighbors. Sice the problem may ot be covex, gradiet descet with the logarithmic barrier method [6] is used to fid these optimal poits. he model s regio of validity lies i the itersectio of the trust regio ad the iputted bouds for the tuig parameters. he objective fuctio is performed as follows: MiimizeW D W P t x x x x D( ) D P( ) P G G H H m m log, log, D P j j u j j l j j D D P P (6) where x j,l ad x j,u are the upper ad lower bouds for variable x j, ad D ad P are delay ad power for the etire desig, respectively. he weights for delay ad power are defied as follows: / / W P P P P D D dl ( r) l( r) l( r) l( r) W D D P P D D pl ( r) l( r) l( r) l( r) where (D, P ) is the startig poit ad (D l, P l ) ad (D r, P r ) are the left ad right eighbor poits, respectively. he solid poits i Fig. 6 are examples of such poits. he directio vectors (W dl, W pl ) ad (W dr, W pr ) of the weighted sum of objectives are calculated so as to be perpedicular to the coectig lies betwee the startig poit ad its eighbors, as illustrated by the dashed lie i Fig. 6. D ad P are give by D W max D y, D y,..., D y, P W P (8) D S S S i Si i where W D is the delay weight discussed i Sectio II.A ad W i is the umber of S i used i the caoical circuit costructio. Because the maximizig fuctio does ot have a cotiuous derivative, we use higher order orms to estimate the maximum, so the elemets of gradiet vector ad Hessia matrix for delay are derived as follows: D, D S y,,..., K S y S y D D D K, Η D D D D D GD, j x x x x x x K D, jk j j j k j k (7) (9)

5 Power (W) 5.8 % Activity % Activity 5m SOI CortexM Clock period (ps) Fig. 7. Compariso betwee commercial sythesis tool, Model [], ad PROCEED. V dd ad V t are costats ad oly size is a variable. where K is the order of the orm. Higher K results i more accurate results (we use K = i our simulatios). Similarly, the elemets of the gradiet vector ad Hessia matrix for power are give as P PSi i P PSi i GP, j Wi y, P, jk Wi y () x x x x x x j i j j k i j k () Additio of ew Pareto poits: o correct for model errors, circuit simulatios are performed to evaluate D ad P for all remaiig potetial Pareto poits foud by the optimizatio. I Fig. 6, this process is illustrated by the shift of the hatched poit to the dotted circle. Fially, poits ot o the Pareto frotier (such that at least oe other poit with both lower delay ad power exists) are filtered out. (5) Iteratio termiatio: For each iteratio, whe choosig the startig poit for each step, the radius of trust regio aroud this poit is decreased by a factor of p (p > ).wo termiatio coditios are applied: ) existece of a sufficiet Pareto poit desity i the regio of iterest, defied by the largest gap betwee ay two eighborig poits beig smaller tha a give criterio. his coditio is usually used for devices with large operatig regios (i.e. suitable for both high speed ad low power applicatios). ) Reductio of the radius of trust below a give criteria. his usually occurs due to limitatios o the device operatig regio or device model discotiuities. he PROCEED rutime is of order O(r m )+O(r), where r is the resolutio costrait (umber of poits i a uit Pareto curve), m is the total umber of tuig parameters, O(r m ) is the complexity of the simulatios for gradiet ad Hessia matrix calculatio, ad O(r) is the complexity of simulatig potetial Pareto poits. I our experimets, rutimes are maily domiated by the resolutio costrait; however, for large m, the O(r m ) term will domiate. he average PROCEED rutime to geerate a full Pareto curve over three orders of magitude i performace is about hours o a sigle CPU. We use MALAB i the optimizatio process ad HSPICE for circuit simulatios. IV. EPERIMEN RESULS Activity = % (PROCEED) Activity = % (RL Compiler) Activity = % (Model [8]) Activity = % (PROCEED w/o ldh) Activity = % (PROCEED) Activity = % (RL Compiler) Activity = % (Model [8]) Activity = % (PROCEED w/o ldh) o illustrate PROCEED s capabilities, we compare it with existig evaluatio methods ad use it to assess SOI ad silico FE devices at the 5 m ode. Because of their use of iterbad tuelig, FEs are capable of very low leakage ad extremely steep subthreshold swig, makig them well-suited for low voltage operatio [8]. Curretly, however, oidealities i experimetal devices ad low o-curret limit their performace. We examie the viability of curretly achievable FEs usig a device compact model [7]-[8] calibrated agaist CAD simulatios ad experimetal SOI devices [9]. While this does ot represet the best possible FE, which may require a differet chael material or device structure, it have the advatages of beig experimetally validated ad structurally comparable to covetioal SOI devices ad represets a realistic lower boud. 5 m SOI MOSFEs are modeled usig commercial characteristics ad compact model. Uless otherwise specified, all circuit results are geerated with oe V dd ad two V t. o easily compare devices, we will refer to the Pareto crossover, defied as the delay above which the optimized ovel device (here, the FE) cosumes less power tha the established techology (SOI); lower Pareto crossover meas the ovel device is more promisig for a give case. A. Framework Evaluatio o validate our PROCEED framework, we use the widely employed evaluatio model of Ref. [] (hereafter Model []), ad a commercial sythesis tool to evaluate the PD Pareto curve for a CortexM microprocessor with a commercial 5 m SOI library ad model. he iformatio eeded for PROCEED ad Model [] (LDH, average fa-out ad itercoect load) is extracted from a sythesized, placed, ad routed etlist at a clock period of 933 ps. Oly oe costat V dd ad oe costat V t are used, as Model [] does ot support multiple voltages ad the commercial library has oly costat supply ad threshold voltages. As show i Fig. 7, the PROCEED predictios are i much better agreemet with the comprehesive optimized results from the RL compiler compared to Model [], which is frequetly used for device evaluatio []-[3]. he operatig rage for compariso is chose by the sythesis results with the commercial library with oe V dd ad V t. We ote that usig the compiler for evaluatio purposes is completely impracticable, sice geeratig a Pareto curve from khz to GHz speeds ecessitates libraries with V dd ad V t varyig from.5v to.v ad.v to.5v respectively. However, the geeratio ad optimizatio of these libraries would cosume moths of rutime, whereas we completed the same study i hours usig PROCEED. Meawhile, the computatioally simple Model [] takes secods to complete such Pareto curves but grossly overestimates power for two reasos: the eglect of LDH i assumig all gates have the same (large) size used for the critical path, ad the use of aalytical PD models rather tha circuit simulatios usig full device characteristics. he dotted lie is the Pareto curve geerated by PROCEED while eglectig LDH, illustratig the accuracy improvemet cotributed by the two foregoig poits. We further ote that Model [] caot accout for adaptivity, variability, or multiple V dd ad V t effects. By bechmarkig to the RL results i Fig. 7, we observe PROCEED improves accuracy by 3 to 5 compared to the curret stadard Model []. B. Impact of Multiple V dd, V t, ad Gate Sizig More tuig parameters create a larger phase space for desig optimizatio, as illustrated i Fig. 8 for a 5 m SOI CortexM topology. As more LDH bi divisios are itroduced, power is icreasigly optimized because of a greater rage of gate sizes with which to costruct the desig. Similarly, the itroductio of additioal supplies ad threshold voltages substatially improves performace. he result does ot accout for the overhead cosumed by the voltage shifter used i multiple V dd desig. Overall, however, we observe that the evaluated optimal power at a give delay may chage by over 5% as gate size tuig ad multiple V dd ad V t are itroduced, demostratig the ecessity of icludig these effects i ay quatitative compariso.

6 Logic depth Logic depth 6 C. Impact of Bechmarks o Evaluatio SOI vs. FE Power (W) PROCEED with Multiple V dd, V t, ad gate sizig 5m SOI CortexM Activity=% o show the impact of bechmark selectio, we compare the performace of two microprocessors, CortexM ad MIPS, usig SOI ad FE devices ad two supply rails ad two threshold voltages. We choose these bechmarks because, as show i Fig. 9(a), they have a similar umber of critical path stages (56 i CortexM vs. 6 i MIPS) ad total gates (899 vs. 98), but the CortexM has a more evely distributed LDH. he power cosumptio i MIPS is domiated by short paths, which meas it will be more accommodatig of slow devices compared to the CortexM. Accordigly, i Fig. 9(b), both SOI ad FE achieve better power efficiecy i MIPS desigs because the secod V dd ad V t ca be optimized to save power alog the short paths. he crossover poits where the Pareto curves for differet devices itersect defie their advatageous operatig regios; a device chages from beig less power efficiet o oe side of the crossover to beig more efficiet o the other side. If multiple crossovers are foud, the the Pareto curve ca be divided ito several regios (high performace, low power, etc.) such that i each oe, there is oly a sigle crossover poit. his allows us to demarcate the (possibly multiple) favorable operatig rages for each device. he Pareto crossover occurs at 73 s ad 6 s for MIPS ad CortexM, respectively, showig that FEs are more acceptable for applicatios like MIPS which tolerate slower devices. However, FE drive currets must be icreased if they are to be usable at higher clock rates. Previous evaluatios, like those i able, which igore LDH, are ot able to distiguish betwee bechmarks i this way. hese results show how the choice of circuit topology strogly impacts the suitability of emergig devices. D. Impact of Activity Factor SOI vs. FE We ext examie how activity factor affects SOI- ad FE-based CortexM processors i Fig.. As activity reduces MIPS CortexM (a) 73s (MIPS) Activity=% Vdd ad Vt V dd, V t, bi V dd, V t, bis V dd, V t, 3bis V dd, V t, 3bis V dd, V t, 3bis 6 8 Clock Period (s) Fig. 8. 5m SOI CortexM power-clock period as tuig parameters are icreased. Bechmark impact o 5m P SOI CortexM SOI MIPS FE CortexM FE MIPS 6s (CortexM) 5 5 Clock period (s) (b) Fig. 9. (a) LDH of MIPS ad CortexM. (b) Power ad delay curves for MIPS ad CortexM desiged with FE ad SOI respectively. Activity is % ad two V dd ad two V t are applied. Power (W) Power (W) from % to %, FE circuit power scales i lockstep by 97.6 due to low device leakage. However, the correspodig SOI desigs oly see power reductio of 9. because of its higher off-curret. We see that FEs chage from beig completely impracticable at % activity to beig superior to SOI beyod the 96 s delay poit at % activity; thus activity factor, ad hece system use cotexts, ca drastically alter the device evaluatio ad must be cosidered. E. Power Maagemet Modelig he results of the previous subsectios make clear that there is o paacea device ad that device-circuit evaluatio must be doe with specific applicatios ad operatig widows i mid. DVFS ad power gatig are crucial igrediets for such usage-midful evaluatio. I Fig., we show PROCEED- geerated Pareto curves at differet ratios of average to peak throughputs for SOI ad FE CortexM usig DVFS ad power gatig. Power is reduced by operatig at the lower supply rail or tured off by power gatig; the achievable power reductio differs with device ad operatig regio. he peak throughput crossover poit for FEs shifts from.9m to.5m operatios per secod as the ratio of average to peak throughput reduces from % to %; the relative performace of FEs effectively doubles as throughput requiremets become less aggressive, emphasizig the importace of icorporatig power maagemet ito device bechmarkig. F. Variatio-Aware Evaluatio o illustrate how variability might impact coclusios draw usig omial devices, we show i Fig. how the SOI ad FE Pareto curves are chaged whe slow corer devices are used. We defie the slow corer as a device with % effective voltage Power (W).. Impact of activity o 5m CortexM Activity=% 96s Clock period (s) 5m CortexM with DVFS Activity=%.9M.6M 9. 6.M Ave. P/Peak P = %, 5%. %. %.5M 97.5 FE activity=% FE activity=% SOI activity=% SOI activity=% Activity=% Fig.. Activity impact o 5m Si SOI ad Si FE power-clock period. FE Ave P/Peak P SOI Peak throughput (M ops/s) Fig.. 5m SOI ad FE CortexM microprocessors with power maagemet. he ratio of average to peak throughputs are %, %, 5% ad %. Curves with ratios of % are desigs outputted from Pareto optimizer.

7 7 Power (W) Impact of variatio o 5m CortexM 96s 3s Clock period (s) Fig.. Variatio-aware evaluatios of 5m techologies. Assumed voltage drop is 9% ad V t shift is 5mV. reductio ad 5 mv V t shift; total power is simulated usig the omial device, while delay is evaluated with the slow corer. We observe that the FE is more sesitive to variability effects tha SOI, as the Pareto crossover shifts from 96 s to 3 s. his is due to the FE s steep subthreshold swig aroud the crossover, leadig a high sesitivity of drive curret to voltage []-[] his suggests that FEs eed to show substatial omial device advatages i order to buffer this sesitivity ad demostrates that eve a simple cosideratio of variability is importat i device evaluatio ad selectio. V. CONCLUSION he proposed circuit-device co-evaluatio framework accouts for circuit topology, adaptivity, variability ad use cotext usig efficiet Pareto optimizatio heuristic. Previous device evaluatio frameworks igore oe or more crucial factors like multiple supply ad threshold voltages, power maagemet, logic depth, variability, etc., which ca easily lead to misleadig results. For istace, we fid that icludig power maagemet i our evaluatio ca effectively double the usable operatig rage for FEs, ad that choice of activity factor ca dictate whether FEs are acceptable at all i a give applicatio. hese observatios are made possible by PROCEED s scope ad computatioal efficiecy i studyig several orders of magitude i possible device/circuit performace, ad demostrate the power ad flexibility of our ew methodology. VI. ACKNOWLEDGEMEN FE w/o variatio SOI w/o variatio FE w/ variatio SOI w/ variatio We would like to ackowledge the geerous support of IMPAC UC Discovery Grat ( i accomplishig this work. [5] D. Sylvester ad K. Keutzer, System-Level Performace Modelig with BACPAC Berkeley Advaced Chip Performace Calculator, Proc. SLIP, pp. 9-, 999. [6] M. Luisier, M. Ludstrom, D. A. Atoiadis, ad J. Bokor, Ultimate device scalig: Itrisic performace comparisos of carbo-based, IGaAs, ad Si field-effect trasistors for 5 m gate legth, Proc. IEDM, pp...-,. [7] H. Kam,.-J. Kig-Liu, E. Alo, ad M. Horowitz, Circuit-level requiremets for MOSFE-replacemet devices, Proc. IEDM, pp , 8. [8] C. Augustie, A. Raychowdhury, Y. Gao, M. Ludstrom, ad K. Roy, PEE: A device/circuit aalysis framework for evaluatio ad compariso of charge based emergig devices, Proc. ISQED, pp.8-85, 9. [9] C. Pa ad A. Naeemi, System-Level Optimizatio ad Bechmarkig of Graphee PN Juctio Logic System Based o Empirical CPI Model, IEEE Proc. Itl. Cof. IC Desig & echology, May.. [] A. M. Ioescu ad H. Reil, uel field-effect trasistors as eergy-efficiet electroic switches, Nature, vol. 79, o pp ,. [] R. S. Ghaida ad P. Gupta, DRE: a Framework for Early Co-Evaluatio of Desig Rules, echology Choices, ad Layout Methodologies, IEEE ras. CAD, vol. 3, o. 9, pp , Sep.. [] J. A. Davis, V. K. De, ad J. D. Meidl, A Stochastic Wire-Legth Distributio for Gigascale Itegratio (GSI) Part II: Applicatios to Clock, Power Dissipatio, ad Chip Size Estimatio, IEEE ED, vol. 5, o. 3, pp , Mar [3] J.-H. Ryu, S. Kim, ad H. Wa, Pareto frot approximatio with adaptive weighted sum method i multiobjective simulatio optimizatio, Proc. Witer Simulatio Coferece (WSC), pp , 9. [] J. P. Beso et al., Car-park maagemet usig wireless sesor etworks. Proc. Cof. Local Computer Networks, pp , 6. [5]. He et al., Achievig Real-time arget rackig Usig Wireless Sesor Networks, Proc. RAS Symp., pp. 37-8, 6. [6] S. P. Boyd ad L. Vadeberghe, Covex Optimizatio. Cambridge,. [7] A. Pa ad C. O. Chui, A Quasi-Aalytical Model for Double-Gate uelig Field-Effect rasistors, IEEE EDL, vol. 33, o., pp. 68-7, Oct.. [8] A. Pa, S. Che, ad C. O. Chui, Electrostatic Modelig ad Isights Regardig Multigate Lateral uelig rasistors, IEEE ED, vol. 6, o. 9, pp. 7-7, Sept. 3. [9] K. Jeo et al., Si uel rasistors with a Novel Silicided Source ad 6 mv/dec Swig, VLSI Symp., p. -,. [] G. Leug ad C. O. Chui, "Stochastic Variability i Silico Double-Gate Lateral uel Field-Effect rasistors," IEEE ras. Electro Devices, vol. 6, o., pp. 8-9, 3. [] G. Leug ad C. O. Chui, "Iteractios betwee Lie Edge Roughess ad Radom Dopat Fluctuatio i No-Plaar Field-Effect rasistor Variability," IEEE ras. Electro Devices, vol. 6, o., pp , 3. REFERENCES [] L. Wei, S. Oh, ad H.-S. P. Wog, Performace bechmarks for Si, III V, FE, ad carbo aotube FE-re-thikig the techology assessmet methodology for complemetary logic applicatios, Proc. IEDM, pp.6..-,. [] L. Wei ad D. A. Atoiadis, CMOS device desig ad optimizatio from a perspective of circuit-level eergy-delay optimizatio, Proc. IEDM, pp.5.3.-,. [3] P. M. Solomo, D. J. Frak, ad S. O. Koswatta, Compact model ad performace estimatio for tuelig aowire FE, Proc. DRC, pp.97-98,. [] D. J. Frak, W. Haesch, G. Shahidi, ad O. H. Dokumaci, Optimizig CMOS techology for maximum performace, IBM J. Research ad Dev., vol. 5, o. /5, pp.9-3, Jul.-Sep. 6. PROCEED will be made publicly available as ope-source software.