28.3. Kaushik Roy Dept. of ECE, Purdue University W. Lafayette, IN 47907, U. S. A.

Transcription

1 8.3 Novel Sizig Algorithm for Yield Improvemet uder Process Variatio i Naometer Techology Seug Hoo Choi Itel Corporatio Hillsboro, OR 974, U. S. A. seug.h.choi@itel.com Bipul C. Paul Dept. of ECE, Purdue Uiversity W. Lafayette, IN 4797, U. S. A. paulb@ec.purdue.edu Kaushik Roy Dept. of ECE, Purdue Uiversity W. Lafayette, IN 4797, U. S. A. kaushik@ec.purdue.edu ABSTRACT Due to process parameter variatios, a large variability i circuit delay occurs i scaled techologies affectig the yield. I this paper, we propose a sizig algorithm to esure the speed of a circuit uder process variatio with a certai degree of cofidece while maitaiig the area ad power budget withi a limit. This algorithm estimates the variatio i circuit delay usig statistical timig aalysis cosiderig both iterad itra-die process variatio ad resizes the circuit to achieve a desired yield. Experimetal results o several bechmark circuits show that oe ca achieve up to 9% savigs i area (power) usig our algorithm compared to the worst-case desig. Categories ad Subject Descriptors B.8.[Performace ad Reliability]:Performace Aalysis ad Desig Aids Geeral Terms: Algorithms, Performace, Desig, Reliability.. INTRODUCTION As silico idustry is movig towards the ed of the roadmap, the device parameters (such as chael legth, oxide thickess, threshold voltage, radom placemet of dopats i chael, etc) are expected to have large variatios. Cosequetly, a large variability i performace amog differet chips is expected. The process variatios ca be classified as systematic or radom. While systematic variatios are determiistic i ature ad are caused by the structure of a particular gate ad its topological eviromet, radom variatios are upredictable i ature. Radom variatios iclude variatios i the effective chael legth of devices, dopig profiles, oxide thickess ad trasistor width. Variatios i dopig profile are very importat i advaced techologies because it may lead to potetially large chage i threshold voltage []. Furthermore, itrisic fluctuatios are idepedet of trasistor locatio o a chip. The process parameter fluctuatios caot be elimiated by exteral cotrol of the maufacturig process ad hece, a statistical desig methodology is required cosiderig the radomess of the process parameter variatio. Various aspects of the process parameter variatio icludig methodology, aalysis, sythesis ad modelig are addressed i []. Covetioal sizig tools size the gates to optimize area ad power cosumptio while meetig the desired delay costrait [3], [4]. Usually these tools fid the critical poits of the circuit through static timig aalysis, which affect the critical path delay. The tool the sizes the trasistor widths to meet the desired delay costrait while keepig the This research was supported by DARPA MARCO Gigascale Silico Research Ceter (SA373JB), SRC (78.) ad Itel Corporatio. Permissio to make digital or hard copies of all or part of this work for persoal or classroom use is grated without fee provided that copies are ot made or distributed for profit or commercial advatage ad that copies bear this otice ad the full citatio o the first page. To copy otherwise, or republish, to post o servers or to redistribute to lists, requires prior specific permissio ad/or a fee. DAC 4, Jue 7-, 4, Sa Diego, CA, USA. Copyright 4 ACM /4/6 $5.. power cosumptio ad area withi a limit. However, due to radom process parameter variatio, a large umber of chips may ot meet the required delay. Cosider a example pdf (probability desity fuctio) of delay show i Figure due to process variatio. I this example, the distributio is assumed to be ormal [5]. This figure shows that 5% of the total umber of dies will ot meet the desired delay costrait, which will affect the fial yield drastically. Oe way to couter this effect is to set the target delay cosiderig worst case process variatio. For example, oe ca choose the 6σ poit i Figure as the target delay for desigig uder worst case process variatio. Cosequetly, while the yield is expected to improve sigificatly, the area ad power overhead to meet the worst case delay costrait may ot be acceptable. This is because, oly a very few dies will have the worst case delay due to process variatio, ad settig the target delay based o those dies will result i uacceptable power cosumptio i most of the dies. Hece, beyod a certai poit the improvemet i yield will be masked by the icrease i the area ad the power overhead. Furthermore, resizig the gate also chages the delay spectrum of the circuit (i.e. σ also chages alog with the mea of delay distributio). This is because the variatio i the trasistor threshold voltage (hece, the variatio i delay) is a strog fuctio of trasistor width due to the radom placemet of dopats i very short-chael devices [6]. A proper desig techique is therefore, ecessary to achieve optimum yield with miimum icrease i the area ad power overhead. Several attempts have bee made to model the effect of process variatio o delay usig statistical timig aalysis [7],[8],[9]. These aalyses cosidered iter- ad itra-die process variatio ad i some cases also modeled spatial correlatios betwee trasistors [8]. However, attempts have rarely bee made to size the gates cosiderig the statistical ature of process variatio. I [], the gate sizig cosiderig a statistical delay model was proposed usig o-liear programmig. However, the use of o-liear programmig makes it less practical i real circuits. I this paper, we propose a statistical desig techique cosiderig both iter- ad itra-die variatio of process parameters. The idea is to resize the trasistor widths with miimal icrease i area ad power cosumptio while improvig the cofidece that the circuit meets the delay costrait uder process variatio. We have developed a sizig Normalized umber of dies Desiged delay Delay (ps) Figure. pdf of delay due to process variatio: a example. 454

2 tool usig Lagragia relaxatio algorithm [] for global optimizatio of trasistor widths. The algorithm first estimates the expected delay variatio at the primary output of a give circuit based o statistical static timig aalysis. Usig the delay distributio obtaied at the primary output ad the desired yield, the algorithm optimizes the area by icreasig the size of trasistors to achieve desired delay while reducig the trasistor sizes i the off critical paths. The cotributio of this work is to provide a sizig algorithm to esure the speed of a circuit uder process variatios with a certai degree of cofidece while keepig the area ad power budget withi a limit. We cosider the variatios ot oly i chael legth, width, oxide thickess, threshold voltage of the trasistor but the effect of radom placemet of dopats as the domiat parameters for process variatio. While the variatios i chael legth, width ad oxide thickess are expected to have spatial correlatio betwee adjacet trasistors [8], radom placemet of dopats make every trasistor i the circuit idepedet. We model these variatios i our aalysis ad icorporate them ito the sizig tool. We also cosider iter- ad itra-die variatio of process parameters to achieve more realistic desig. We used the proposed sizig tool to sythesize several ISCAS bechmark circuits ad compare the estimated yield with the circuit sythesized by covetioal sizig tool. The rest of the paper is orgaized as follows. I sectio, we discuss the statistical timig aalysis of a circuit cosiderig both iter- ad itra-die variatios. Sectio 3 describes the sizig algorithm based o Lagragia relaxatio i detail. I sectio 4, we discuss the experimetal results o ISCAS bechmark circuits. Sectio 5 draws the coclusio.. STATISTICAL TIMING ANALYSIS Statistical static timig aalysis is performed to estimate the variability i circuit delay uder process variatio. Process variatios ca be categorized as iter-die ad itra-die variatios. Due to iter-die variatios, the same device o a chip ca have differet characteristics across differet dies (i.e., dies from oe wafer, from wafer to wafer, ad from wafer lot to wafer lot). Itra-die variatios, o the other had, are the variatios of trasistor characteristics withi a sigle chip. Both iter- ad itra-die variatios are expected to be truly radom i ature i future techologies. While itra-die variatios i terms of trasistor legth, trasistor width ad oxide thickess, are expected to exhibit spatial correlatios amog devices located close to each other, radom placemet of dopats i sub-5 aometer trasistors is expected to make every trasistor i a die idepedet i terms of threshold voltage. We icorporate both iter- ad itra-die variatios i our timig aalysis. The most accurate way of icorporatig the process variatio effects ito timig aalysis is to perform a full-scale trasistor-level Mote- Carlo simulatio of a circuit, which requires large computatioal overhead. Hece, i our aalysis the effect of process parameter variatios o the gate delay is pre-characterized ad accessed o the fly durig statistical timig aalysis. The pre-characterizatio table cotais statistical iformatio o the delay of a gate cosiderig process variatio. It is assumed that iter- ad itra-die process variatios are statistically idepedet [8]. This reduces the complexity of statistical timig aalysis because the effects of iter- ad itra-die process parameter variatio o delay ca be aalyzed i isolatio. For example, we model the variatio i trasistor legth L total as the sum of iter-die variatio (L iter ) ad itra-die variatio ( L itra ) as follows. σ = σ + σ Ltotal Liter Litra where σ is the stadard deviatio. Accordigly, the effect of the variatio i trasistor legth o the delay ca be simplified to [8]: σ delay, total = σ delay, iter + σ delay, itra The effects of variatio i the threshold voltage, oxide thickess, ad trasistor width o delay are also icorporated i a similar way. As explaied above, iter- ad itra-die variatios are aalyzed i isolatio. That is, σ delay,iter ad σ delay,itra are idepedetly calculated ad combied to obtai the overall distributio of delay. Durig statistical timig aalysis, the sigal arrival time is calculated at each gate by propagatig the delay from the primary iput i the circuit. Uder process variatio, the sigal arrival time is also a distributio which is propagated durig the timig aalysis. The variatio i the arrival time is obtaied from the statistical iformatio stored i the precharacterizatio table. We maitai two tables - oe for iter-die variatio ad the other for itra-die variatio. I the followig subsectios, we explai how to propagate the effect of process variatio durig statistical timig aalysis cosiderig both iter- ad itra-die variatio.. Iter-die variatio Cosiderig that trasistor parameters remai costat withi a sigle die, evaluatio of the effect of iter-die variatio o circuit delay is straightforward. For example, due to iter-die variatio, if the device legth i a die becomes 'L+ L', this will remai the same for all trasistors i that die. Hece, uder iter-die process variatios, all idetical gates i a die will have the same delay. It is therefore, easy to pre-characterize the delay of gates for all possible combiatio of process parameters. We geerate the pre-characterizatio table through Mote-Carlo simulatio usig SPICE cosiderig the iter-die variatios i threshold voltage, oxide thickess, trasistor width ad trasistor legth. We assume ormal distributio [5] for all iter-die process parameter variatios. It is also assumed that the correspodig gate delay variatio ca be modeled as ormal distributio. Figure (a) shows oe example of delay variatio for a iverter obtaied usig Normalized umber of dies Normalized umber of dies SPICE results Normal approx Delay (ps) (a) Delay variatio of a gate. Delay variatio.8 Normal approx Delay (ps) (b) Delay variatio of a die Figure. Normal approximatio of iter-die delay variatio 455

3 N(µ S,σ S ) S N(µ A,σ A ) A I I I S S I A A σ Ao = f( σ A, σ A, µ A, µ A, σ S, σ S, S, S ) σ So = g ( σ A, σ A, µ A, µ A, σ S, σ S, S, S ) Figure 3. -iput NAND gate example of calculatig itra-die delay variatio SPICE Mote-Carlo simulatio for BPTM 7m techology [] uder iter-die variatio. It ca be observed from the figure that the above assumptio is reasoable. Each poit i the delay distributio represets the delay of a gate i a die for a correspodig process corer. The circuit delay is calculated for all process corers ad the overall delay distributio for the circuit uder iter-die process variatio is obtaied. Figure (b) shows the delay distributio at the primary output of a example circuit (ISCAS c43) uder iter-die variatio. It ca be see from the figure that the distributio ca also be approximated as ormal distributio.. Itra-die variatio Ulike iter-die variatio, trasistors withi a die are expected to have differet process parameters uder itra-die variatio. I static timig aalysis, sigal arrival time at the output of a gate is calculated by addig the gate delay to the sigal arrival time at the iput. Cosiderig itra-die process variatio, both gate delay ad iput sigal arrival time are to be cosidered as radom variables. For example, i a two-iput gate, the radom variable A o, which represets the worst-case arrival time at the output, ca be expressed as A o = max( A + D, A + D ) () where A ad A are the radom variables which represet iput arrival times, respectively. Radom variables D ad D represet the correspodig pi-to-pi delays. The f Ao (x), the probability desity fuctio for A o, ca be calculated as below. f Ao( x) = f A D ( x) FA D ( x) FA D ( x) f A D ( x) F A (x) represets the probability that A x. Although we assume that A ad D (A ad D ) have ormal distributios, this does ot guaratee that A o ca also be modeled by ormal distributio. However, authors i [3] showed that the error i assumig ormal distributio for A o is egligible. Therefore, i our aalysis, A o is assumed to have ormal distributio. The relatioship show i eq. () imposes additioal costraits o the pre-characterizatio of multiple iput gates uder itra-die variatio. Ulike the switchig uder iter-die variatio (where both iput arrival time ad slope are cosidered to be a sigle value i a die), both iput arrival time ad slope are ow represeted by a distributio. Let us cosider the switchig of a two-iput NAND gate show i Figure 3. The arrival time at the output, A, depeds o the iput sigals, I ad I, ad the gate delay. Iput sigals cosist of sigal arrival time (A, A ) ad the slope (S, S ). I our aalysis, both sigal arrival time ad slope are cosidered as ormal distributios. Therefore, the statistical property (σ Ao, σ So ) of the sigal at the output of the gate is a fuctio of iput arrival times, slopes ad temporal correlatios betwee them. Cosiderig this, we geerate the pre-characterizatio table for σ (itradie variatio), while the mea of the arrival time ad slope at the output S A Out N(µ S,σ S ) N(µ A,σ A ) Out S o A o are calculated o the fly usig Sakurai s delay model [5]. For the ease of aalysis, the temporal proximity of two latest-arrivig iputs is cosidered for multiple iput gates..3 Radom placemet of dopats I scaled CMOS devices, there exists a statistical fluctuatio i the umber of dopats, which ca be traslated ito a threshold-voltage variatio [6]. This discrete dopat effect o threshold voltage variatio is icorporated by employig the followig equatio [6] ito the simulator while geeratig the pre-characterizatio table for both iterad itra-die variatio. σ Vth = q Cox NaWdm 3LW σ Vth represets the stadard deviatio of threshold variatio due to radom placemet of dopats, q is electro charge, C ox is the oxide capacitace, N a is the substrate dopig cocetratio, ad W dm represets the maximum depletio layer width. L ad W are the chael legth ad width of the trasistor, respectively. 3. SIZING ALGORITHM FOR YIELD IMPROVEMENT I this sectio, a gate-sizig algorithm is proposed to improve the yield of a circuit uder process variatio. The algorithm proposed here is based o a well-kow techique to a oliear optimizatio problem: Lagragia relaxatio (LR) []. First, we explai the sizig algorithm based o LR ad the describe our proposed algorithm for sizig cosiderig process variatio. 3. Lagragia relaxatio Che et. al [4] proposed the use of LR for simultaeous sizig of gate ad itercoects of a combiatioal circuit to optimize the total area while maitaiig a delay costrait. The covergece of the algorithm was prove ad the optimality was verified. I our experimets, it is assumed that there are o itercoect compoets i the circuit. However, this algorithm ca be exteded to icorporate the itercoect sizig as well, as explaied i [4]. Figure 4 shows a example circuit represetatio for LR. The circuit cosists of gates, which are to be resized, ad s primary iputs. Logic gates ad primary iputs are called compoets. I additio, we add two virtual compoets, oe coectig all primary iputs (compoet 9 i Figure 4) ad the other coectig primary outputs (compoet ). Therefore, for a circuit with gates ad s iputs, there are +s+ compoets. Edge umbers follow their driver gates, i.e., the output of gate i is deoted as edge i. Compoets ad edges are umbered i reverse topological order. Our objective is to miimize the total area (or equivaletly the power cosumptio) which ca be represeted by Σα i x i,,..., where x i is the gate size ad α i is a arbitrary costat multiplier for gate i, which ca vary depedig o the objective of optimizatio. Covetioally, the gates are sized (i.e., all trasistors i a particular gate are sized by the = 5 (gates), s = 3 (primary iputs) compoets & 9: virtual compoets Figure 4. Circuit represetatio for Lagragia relaxatio 456

4 same factor) to achieve miimum area of the circuit while meetig a give delay costrait. I our aalysis, i additio to the delay costrait at the primary output, A, we also have the yield costrait, γ Hece, the sizig problem is formulated as follows. Miimize αi xi Subject to Di A i p Li xi Ui Yield γ γ p P i =,..., L i ad U i represet the lower boud ad upper boud of the size of gate i, respectively. P is the set of possible paths i a circuit. D i represets the delay of gate i i a path p. Compared to the origial problem formulated i [4], we added a extra costrait for yield. Note that the complexity of the problem is expoetially depedet o the umber of compoets i the circuit (O(e )). To reduce the complexity to a liear oe, the delay costraits o all the paths are trasformed ito the delay costraits o each gate i the circuit. Therefore, the sizig problem (which is called the primal problem; PP) is redefied as follows. PP: Sizig for yield Miimize αixi Subject to a j A j iput() /* outputs * / () a j + D j ai i =,..., j iput() i Di ai i = +,..., + s /* iputs / Li xi Ui i =,..., Yield γ γ a i represets the sigal arrival time at edge i ad D i is the delay associated with gate i. Note that the path-based problem is trasformed to a global problem where A is ow the costrait o the circuit delay, ot o ay specific path i a circuit. I solvig this problem, PP is first traslated ito a mathematical equatio itroducig a Lagragia multiplier λ [] for each costrait o arrival time as follows. Miimize : Lλ ( x, a) = αi xi + λ j ( a j A ) j iput( ) (3) + s + λ ji ( a j + Di ai ) + λmi ( Di ai ) j iput() i + λ ji correspods to the iput edge j ad output edge i of gate i. m i λ mi is equal to +s+ (virtual iput ode). Miimizig L λ usig LR cosists of iteratig the followig two steps: ) calculatig the optimal size of the circuit for the curret λ values ad ) updatig λ to the directio of the optimal solutio. Calculatio of the optimal size ivolves the sizig of each gate i such a way that L λ is 84.% µ A σ A Normal Figure 5 Calculatig A i sizig algorithm Delay costrait A Yield γ Iitialize λ Calculate optimal size x i,opt for λ Perform statistical timig aalysis - Iter-die variatio - Itra-die variatio Calculate A from A ad delay variatio Modify λ based o A Σαx - Q(λ) < error boud? yes optimal sizig Figure 6. Sizig algorithm for yield improvemet locally miimized. Sice D i i L λ is a fuctio of gate size x i, the optimal size of a gate ca be obtaied by solvig dl λ /dx i =. I [4], Elmore delay model was used for D i, however, we use Sakurai's delay model [5] for better accuracy i our aalysis. While updatig λ i step ), arrival-time iformatio at each gate iput/output of a circuit is utilized. That is, λ for the ext iteratio is determied by the curret status of delay costraits imposed o each gate after calculatig the optimal size (step )) [4]. Miimizig L λ provides the miimum size of a circuit while satisfyig the delay costrait, A at the primary output. A more detailed explaatio icludig mathematical proofs o sizig algorithm based o LR ca be foud i [4]. 3. Sizig cosiderig process variatio I this subsectio, we explai the proposed algorithm for resizig cosiderig process variatio. Covetioal sizig method based o LR algorithm explaied above cosiders the delay costrait A ad also the circuit delay as costat values. However, i our aalysis delay at the primary output is represeted by a probability desity fuctio (pdf) cosiderig the process variatio. The is obtaied usig statistical timig aalysis as explaied i sectio. Also ote that ulike covetioal sizig method, we have itroduced a additioal costrait for yield as show i eq. (). We icorporate this by modifyig the delay costrait based o the at the primary output. Figure 5 shows a example o how the yield costrait is itroduced ito the sizig algorithm. Assumig a ormal distributio of delay at the primary output, the modified delay costrait, A should be equal to A - σ i order to achieve, for example, 84.% yield uder process variatio, where σ is the stadard deviatio of the pdf. Similarly, for ay differet type of delay distributio ad yield costrait, the delay costrait ca be modified accordigly. Figure 6 shows the flow diagram of the proposed sizig algorithm with yield cosideratio. It starts with a give delay costrait A ad yield costrait γ. The the iitial λ values are chose so that λ i Ω λ, where Ω λ represets the set of λ values that satisfies the optimality coditio [4]: λ ki = λ jk for k + s i output( k ) j iput( k ) o 457

5 The algorithm the calculates the optimal size of gates for λ ad subsequetly statistical timig aalysis is performed to obtai the delay pdf at the primary output. Note that the chages after each iteratio because the variatio i the threshold voltage (hece, the variatio i delay) is a strog fuctio of trasistor width [6]. Based o the give yield costrait γ ad the, A is modified to a ew costrait A ' as illustrated above. Ulike covetioal sizig methodology, the delay costrait is modified after each iteratio durig the miimizatio of L λ i eq. (3). λ is the updated based o the delay costrait A ' ad the timig iformatio i the circuit. This is repeated util L λ is miimized, i.e., Σαx Q(λ) is less tha a user-defied error boud, where Q(λ) is the optimal solutio for L λ at each iteratio. The modificatio of delay costrait A ' after each iteratio as explaied i our algorithm is however, ot straightforward i a circuit with multiple primary outputs. For example, let us assume that there are two primary outputs i a circuit; gate i ad gate j. Also assume that statistical timig aalysis after k th iteratio shows that µ i < µ j, where µ i ad µ j represet the mea delays at the output of the gate i ad gate j, respectively. Uder the assumptio of ormal ad the target yield of 84.%, there ca be two cases depedig o the value of σ (it is also assumed that the delay distributios at differet primary output gates are correlated):. µ i + σ i < µ j + σ j (Figure 7 (a)) New delay costrait A ' is equal to A - σ j based o the delay variatio at the output of gate j.. µ i + σ i > µ j + σ j (Figure 7 (b)) I this case, the calculatio of A ' should be differet. Note that although gate i is cosidered to produce the worst-case delay uder process variatio, covetioally gate j provides the worst delay without cosiderig the process variatio (µ i < µ j ). Hece, the ew delay costrait, A ' for (k+) th iteratio is equal to A - σ i + (µ j - µ i ). O the other had, if we modify the delay costrait as explaied i case ), the algorithm will size the gates to meet the delay costrait A - σ i at the output of gate j resultig i larger area. It is mathematically prove i [4] that sizig algorithm usig LR always coverges to a optimal solutio. Cosiderig process variatio, we modify the delay costrait i each iteratio based o the delay distributio at the primary output (A ' = A - σ). Hece, the covergece with A ' is guarateed as log as the chage i σ is small. It is observed that the chage i σ due to the chage i circuit size from iteratio to iteratio is cosiderably small, which esures the covergece of the algorithm. I the followig sectio, we discuss the experimetal results o several ISCAS bechmark circuits implemeted usig our proposed sizig algorithm. 4. EXPERIMENTAL RESULTS Our proposed sizig algorithm was used to resize several ISCAS bechmark circuits cosiderig the process parameter variatios. All the circuits were sythesized with BPTM 7m techology []. We assumed 5% (3σ) variatio i all the process parameters such as the width, legth ad the oxide thickess i our aalysis for both iter- ad itra-die variatios. The variatio i the trasistor threshold voltage was govered by the effect of the radom placemet of dopats as metioed i sectio.3. Cosiderig that our sizig algorithm resizes the circuit to meet a certai delay costrait, it is importat to kow the possible rage of the delay that ca be achieved for a circuit ad the desired delay costrait. For example, cosider the area-vs.-delay curve (Figure 8) for ISCAS bechmark circuit c43' obtaied usig LR sizig algorithm. The area σ i µ i σ j A A (a) µ i + σ i < µ j + σ j at gate i at gate j µ j -µ i (the sum of trasistor width) i the plot represets the miimum circuit size for the correspodig delay. I the plot, mi delay represets the miimum delay that ca be achieved by resizig the circuit ad max delay is the circuit delay with all gates havig miimum size. The differece betwee the mi delay ad the max delay is deoted as slack del. Also show i the figure is the stadard deviatio (σ) for the delay variatio due to iter- ad itra-die variatio, which is obtaied from statistical timig aalysis. Let us first assume that our delay costrait correspods to the 5% of slack del. The by usig the proposed algorithm, the circuit ca be resized to meet, for example, 84.% yield for the miimum icrease i the area ( area ). Compared to this area, the icrease i area i the case of delay costrait equal to 9% of slack del is much smaller as show i the figure. Therefore, the effectiveess of our sizig algorithm i terms of miimum icrease i area is depedet o target delay costrait. The differeces i area for the bechmark circuits are summarized i Table. The secod colum shows the slack del of differet circuits i terms of σ (whe the circuit delay is miimum, i.e., mi delay). It varies from.99 to 6.59 for differet circuits. The third ad fourth colums represet the percetage icrease i area for 84.% yield with delay costraits equal to 5% ad 9% of slack del, respectively. As expected, i the case of smaller target delay (5% of slack del ), the icrease i area is larger for the same yield improvemet uder process variatio. We also compared our algorithm with the worst-case desig methodology. For this purpose, we assume the target delay as the 9% of slack del for all bechmark circuits. The compariso results are show i Table. I our experimet, circuits are first sized without cosiderig process parameter variatio. This correspods to the sizig of the circuit for desiged delay show i Figure. The area for the Nomial' desig (without the variability take ito accout, i.e., 5% yield) is show i the third colum of the table which represets the sum of trasistor widths. The fourth colum shows the area after resizig the circuits usig our algorithm cosiderig process variatio. It ca be see that with small icrease i area the yield ca be improved to 84.% (correspodig to σ) uder process variatio. The sixth colum shows σ i σ j A A at gate i at gate j (b) µ i + σ i > µ j + σ j Figure 7. Calculatio of A for differet scearios Total trasistor width (um) mi delay area slack del 5% slack del 9% slackdel σ max delay Circuit delay (ps) Figure 8. Circuit size vs. delay for c43 σ 458

6 Table. The depedece of area o delay costrait slack del / σ area (%) whe target delay is.5 slack del.9 slack del c c c c c c c c c c74l the optimum area for 99.9% yield usig our algorithm. We assume that the target delay is reduced by 3σ (99.9% yield) from the omial desig while resizig uder process variatio. I this case, while the yield improves, the icrease i area is larger tha the previous case. Hece, oe ca make a trade off betwee the yield ad the area (power) budget. Furthermore, i some circuits (c98, c688, c748), it is ot possible to achieve 99.9% yield by resizig the gate. This is because for ay circuit, there is a miimum delay that ca be achieved by resizig the gate. The eighth colum i the table (labeled as Worst desig area') shows the circuit area for the worst-case desig. For worst-case desig, the circuit is sized assumig the worst process corer, i.e., all trasistors will have worst parameter variatios. For example, the trasistor legth is assumed to be 'L + L', where L represets the worst-case variatio i L. Other process parameters are also cosidered i a similar way. It should be oted that while the yield uder process variatio is expected to improve i the worst-case desig, the icrease i area is large. It ca be see that the savig i area is as large as 9% (c74l85) usig our proposed sizig algorithm compared to the worst-case desig. Furthermore, i may cases (deoted as * i the table), it is impossible to size the circuit to achieve the desired delay usig the worst-case desig methodology. Colums ad show the ratio of σ to mea delay with 84.% yield for iter- ad itra-die variatio, respectively. It is observed while the ratio remais almost same for iter-die variatio, the ratio for itra-die variatio varies depedig o the depth of the circuit. It should also be oted that the overall variatio i delay is domiated by iter-die variatio. The last colum shows the rutime of our sizig algorithm for 84.% yield. As explaied i sectio, both iter- ad itra-die process variatios are cosidered through statistical timig aalysis. It is observed i the experimets that the majority of the program rutime is attributed to the aalysis of iter-die variatio. I each iteratio, the circuit was simulated for, differet process corers to icorporate the iter-die variatio as explaied i sectio. The rutime ca be reduced by decreasig the umber of this simulatio while maitaiig the accuracy by usig itelliget samplig techiques as explaied i [6]. 5. SUMMARY We proposed a algorithm to size a circuit for statistical desig cosiderig both iter- ad itra-die variatio. This algorithm estimates the variatio i circuit delay based o statistical timig aalysis ad sizes the circuit to achieve a desired yield with miimum icrease i the area ad power cosumptio. Experimetal results o several bechmark circuits show that the savigs i area (hece the power) ca be as large as 9% usig our algorithm tha the worst-case desig. It was also show that it is ot possible to achieve the desired delay i may circuits usig the worst-case desig methodology. REFERENCES [] X. Tag, V. De, ad J. D. Meidl, Itrisic MOSFET parameter fluctuatios due to radom dopat placemet, IEEE Tras. VLSI Systems, pp , 997. [] C. Visweswariah, Death, taxes ad failig chips, Proc. DAC, pp , 3. [3] J. P. fishbur ad A. E. Dulop, TILOS: A posyomial programmig approach to trasistor sizig, IEEE Tras. CAD, pp , 985. [4] S. Sapatekar, V. B. Rao, P. M. Vaidya, ad S. M. Kag, A exact solutio of the trasistor sizig problem for CMOS circuits usig covex optimizatio, IEEE Tras. CAD, pp , 993. [5] A. Papoulis, Probability, Radom Variables, ad Stochastic Processes, McGraw-Hill, 3 rd editio, 99. [6] Y. Taur ad T. H. Nig, Fudametals of Moder VLSI Devices, Cambridge Uiversity Press, 998. [7] H. F. Jyu, S. Malik, S. Devadas, ad K. W. Keutzer, Statistical timig aalysis of combiatioal logic circuits, IEEE Tras. VLSI Systems, pp. 6-37, 993. [8] A. Agarwal, D. Blaauw, V. Zolotov, S. Sudareswara, M. Zhao, K. Gala, ad R. Pada, Path-based statistical timig aalysis cosiderig iter- ad itra-die correlatios, TAU,. [9] A. Agarwal, D. Blaauw, V. Zolotov, S. Vrudhula, Computatio ad refiemet of statistical bouds o circuit delay, Proc. DAC, pp , 3 [] E. T. A. F. Jacobs, M. R. C. M. Berkelaar, Gate sizig usig a statistical delay model, Proc. DATE, pp. 7-3,. [] M. S. Bazaraa, H. D. Sherali, ad C. M. Shetty, Noliear Programmig: Theory ad Algorithms, Wiley, d editio, 993. [] BPTM, [3] M. R. C. M. Berkelaar, Statistical delay calculatio, a liear time method, TAU, 997. [4] C. P. Che, C.C.N.Chu, ad D.F.Wog, Fast ad exact simultaeous gate ad wire sizig by Lagragia relaxatio, IEEE Tras. CAD, pp.4-5, 999. [5] T. Sakurai ad R. Newto, Delay aalysis of series-coected MOSFET circuits, IEEE JSSC, pp. -3, 99. [6] R. Y. Rubistei, Simulatio ad Mote Carlo method, Joh Wiley ad Sos, 98. Table. Experimetal results of applyig the sizig algorithm to ISCAS bechmark circuits No. of Normal (5% yield) 84.% yield % icrease 99.9% yield % icrease Worst desig % icrease σ iter /µ delay σ itra /µ delay Ru time TR Area (um) area (um) i area area (um) i area area (um) i area (%) (%) (sec) c c * * c * * * * c * * c * * c * * * * c * * * * c c c74l (* sizig failed for the correspodig scheme) 459