Power-Aware Modulo Scheduling for High-Performance VLIW Processors

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1 Power-Aware Modulo Schedulig for High-Performace VLIW Processors Ha-Saem Yu School of Computer Sciece ad Egieerig Seoul Natioal Uiversity Jihog Kim School of Computer Sciece ad Egieerig Seoul Natioal Uiversity ABSTRACT For high-performace processors, the step power ad peak power, which are closely related to the chip reliability, are importat desig costraits, ofte more tha the average power. I VLIW processors where a sigle istructio may cotai a variable umber of operatios, the step power ad peak power vary sigificatly depedig o the parallel schedule geerated by a parallelizig compiler. I this paper, we propose a power-aware modulo schedulig algorithm for high-performace VLIW processors. The proposed algorithm reduces both the step power ad peak power by producig a more balaced parallel schedule while ot compromisig performace. Experimetal results show that the proposed schedulig techique sigificatly improves the power characteristics of highperformace processors over a existig power-uaware modulo schedulig techique. 1. INTRODUCTION Power dissipatio has become a importat desig costrait for high-performace processors such as moder superscalar processors ad VLIW processors. Although performace is still the most importat requiremet for high-performace processors, icreasig power dissipatio is becomig a major obstacle to performace improvemets i future microprocessors. I particular, the step power ad peak power, which are closely related to the chip reliability, are importat desig issues, ofte more tha the average power cosumptio, i high-performace processors. 1.1 Step Power ad Peak Power The step power [16], which is defied as the differece i the average power betwee cosecutive clock cycles, represets the iductive oise Ldt di at the microarchitectural level. Iductive oise, also kow as groud boucig, is a voltage glitch iduced at power/groud buses due to switchig currets passig through the wire iductace associated with power or groud rails. A large voltage surge due to the iductive oise may cause timig ad logic This work was supported i part by Korea Research Foudatio Grat (KRF-2-41-E287). Permissio to make digital or hard copies of all or part of this work for persoal or classroom use is grated without fee provided that copies are ot made or distributed for profit or commercial advatage ad that copies bear this otice ad the full citatio o the first page. To copy otherwise, to republish, to post o servers or to redistribute to lists, requires prior specific permissio ad/or a fee. ISLPED 1, August 6-7, 21, Hutigto Beach, Califoria, USA. Copyright 21 ACM /1/8...$5.. errors, thus may reduce the chip reliability. For high-performace processors, the iductive oise problem is becomig more serious because the icreasig clock frequecy, the growig umber of gates, ad the wider datapath result i larger surge curret to charge/discharge the power/groud buses i a shorter time leadig to larger iductive oise. Eve worse, with the growig usage of aggressive clock gatig for reducig the average power cosumptio, the cycle-by-cycle curret swig is gettig larger. The peak power, the maximum power dissipatio durig the executio of a give program, is closely related to the chip temperature [2], to which the chip reliability ad sub-threshold leakage power are expoetially related [5]. Higher peak power leads to the device degradatio, reducig the chip lifetime. As a result, complex coolig systems (which add sigificatly to the maufacturig cost) are used to avoid overheatig ad to esure system reliability. 1.2 Related Work Most previous work has bee focused o hardware mechaisms to cotrol the step power ad peak power. Pat et al. [9, 1] proposed a improved versio of clock gatig to reduce the spike curret by slowly turig o ad off clock gated uits at a modest cost i additioal hardware ad performace. Tag el al. [16] further ehaced this mechaism to reduce the performace loss. The work by Brooks et al. [2] cotrols the peak power i the cotext of dyamic thermal maagemet. There has bee little published work that approached the problems of step-power reductio ad peak-power reductio from the software perspective. The work by Tobure et al. [18] cotrols the peak power dissipatio i VLIW processors by modifyig the istructio schedulig algorithm of a optimizig compiler. Their power-aware scheduler places as may istructios as possible i a give VLIW istructio util the give power threshold is reached. However, their work is based o traditioal list schedulig, which is ot effective i explorig the high istructio-level parallelism available from moder multiple-issue processors such as VLIW processors. Therefore, their work is ot applicable to most highperformace VLIW processors. 1.3 Cotributio I this paper, we propose a power-aware modulo schedulig algorithm for high-performace VLIW processors. I VLIW processors where a parallel istructio cosists of several operatios, the step power ad peak power cosumptio varies sigificatly depedig o how the parallel schedule is geerated by a parallelizig compiler. The proposed algorithm reduces both the step power ad peak power by costructig a more balaced parallel schedule while ot compromisig performace. As will be show later i the paper, the proposed algorithm is

2 quite effective i reducig the step power ad peak power cosumptio i VLIW processors. This is because a parallelizig compiler ca fully cotrol the usage of all the fuctioal uits i a VLIW processor. O the other had, the hardware-assisted techiques such as [9, 16] are ofte limited to the power reductio i a specific fuctioal uit oly without cosiderig the processorwide effect. The rest of the paper is orgaized as follows. I Sectio 2, we describe our target VLIW machie model ad its power model. We briefly review modulo schedulig i Sectio 3. The proposed power-aware algorithm is explaied i Sectio 4 while experimetal results are preseted i Sectio 5. We coclude with a summary ad future work i Sectio TARGET VLIW MACHINE MODEL AND ITS POWER ESTIMATION METHOD VLIW machies use log istructio words to execute multiple operatios simultaeously. I this paper, we assume a VLIW machie model with a MIPS-like iteger pipelie ad a UltraARClike floatig-poit (FP) uit pipelie. For a 8-issue VLIW model, we assume that there are oe iteger ALU (icludig a brach uit), two load/store uits, oe iteger MPY/DIV, two FP ALUs ad two FP MPY/DIVs. For a 16-issue VLIW model, we assume that the umber of each fuctioal uit is doubled over that of the 8-issue model. I a target VLIW model, each operatio takes differet cycles to execute. For example, load operatios require oe cycle i the executio stage while FP DIV operatios sped 1 cycles i the executio stage. For a give VLIW machie, we estimate the power cosumptio at the cycle level, takig the pipelied executios ito accout. For each operatio op, we associate a power cost p op i that represets the power cosumed by operatio op at the i-th pipelie stage (1 i s ) where s deotes the umber of pipelie stages. I this paper, we assume that p op i values were give. They ca be obtaied from actual measuremets of a target processor (e.g., [3]) or simulatios of a detailed processor model. For experimets, we used p op i values extrapolated from iformatio available i [14] ad [17]. Give a program executio trace T, let T i represet the set of operatios i the VLIW istructio executed at the i-th cycle of T. The power dissipatio P i at the i-th cycle is estimated as follows: P i s p op j (1) j 1 op T i j 1 Sice our mai goal is ot to develop a cycle-accurate power model of VLIW processors, but to devise a power-aware schedulig algorithm for VLIW processors, admittedly, our power estimatio method is rather simple ad has may weakesses. For example, i computig P i, we do ot cosider iter-istructio effect or iter-operatio effect as doe i [18]. That is, we assume that each operatio (istructio) cotributes to the total power cosumptio, idepedetly of other operatios (istructios). However, the proposed algorithm ca be easily exteded to work with more accurate power estimatio models, because the proposed algorithm does ot deped o a particular power estimatio techique. 3. MODULO SCHEDULING OVERVIEW Software pipeliig is a aggressive loop schedulig techique for VLIW processors. It trasforms a sequetial loop so that ew iteratios ca start before precedig oes fiish, thus overlappig the executio of multiple iteratios i a pipelied fashio. Modulo schedulig [6, 13] is oe of the schedulig algorithms for implemetig software pipeliig. 1 Sice a large umber of loops cotai o coditioals, we cocetrate o loops with o cotrol flows i this paper. For loops with cotrol flows, we assume a hardware mechaism that supports predicated executio. If-coversio [1, 11] ca be performed to elimiate coditioals i loops with cotrol flows uder this hardware mechaism. A loop is modeled as a double-weighted directed graph G V E δ d, called a data depedece graph (DDG) 2, where V is the set of operatios i the loop, δ is a fuctio from V to the positive itegers represetig the latecy of each operatio, E is the edge set of G ad d is a fuctio from E to o-egative itegers. E ad d specify depedeces amog operatios. A edge e v v E with a weight d e states that for every iteratio i d e of the loop, operatio v depeds o the outcome of operatio v i iteratio i d e ad caot be iitiated util the completio of v. Figure 1(b) shows the DDG of a example loop i Figure 1(a). Give a loop with the form of a DDG G ad a specific resource costrait, the problem of software pipeliig is defied as fidig the miimal iitiatio iterval (II) ad costructig a schedule σ that is a fuctio from V N to N such that the followig costraits are met (σ v i deotes the executio cycle i which the istace of operatio v i iteratio i is iitiated): Periodicity costrait: σ should be represeted as a periodic form such that v V i N σ v i σ v II i Depedece costrait: For every v ad v such that e v v E, the istace of operatio v i iteratio i! d e " should ot be iitiated util the completio of the istace of operatio v i iteratio i. e v v#$% E i N σ v#$ i d e& ' σ v i δ v Resource costrait: Let Rk represet the umber of available R k fuctioal uits ad let τ v represet the fuctioal uit i which v is executed. For each fuctioal uit R k, o more tha Rk operatios are iitiated i the same cycle: 3 R k t N )( *+ v i,( τ v.- R k / σ v i t+(21 Rk From the periodicity costrait, it is sufficiet to fid II ad σ v for v V, called a flat schedule. The depedece costrait ad resource costrait are traslated as follows uder the flat schedule: e v v#3 E σ v#$ ' σ v δ v+4 II d e R k 1 t 5 II ( *+ v,( τ v - R k / σ v - t mod II67(21 Rk Figure 1(c) shows a flat schedule with the iitiatio iterval of 3 cycles for the DDG of Figure 1(b). It is well-kow that the problem of determiig if a flat schedule exists for a give II is NP-hard ad several heuristic approaches have bee developed to fid the miimal II ad the flat schedule. The miimum iitiatio iterval (MII) is a lower boud o the II 1 Software pipeliig is essetially equivalet to the retimig techique which is widely used i VLSI high level sythesis [4] ad logic level sythesis [8]. 2 Such a graph is called a data flow graph (DFG) i the cotext of sychroous VLSI circuits. 3 For simplicity, we assume that the fuctioal uits are fully pipelied. Complex resource costraits ca be hadled by resource reservatio table [13].

3 U a a (1) r1 = op1(r3) (2) r2 = op2(r1,r5) (3) r3 = op3(r2) (4) r4 = op4(r3) (5) r5 = op5(r2) (6) r6 = op6(r6) (a) 1 (1) (2) (3) 1 1 (b) (5) (4) (6) For such a, the peak power is equal to P8 F idealh ad the step power is zero for the whole executio trace T8. 4 I order to reduce the step power ad peak power, our basic approach is to schedule operatios i such a way that the resultig P8 9 i fuctio becomes as flat as possible. As a figure of merit for the flatess of, we use the followig fuctio RS T : V IIW 1 2 K P; < i 4 P; I idealj N i (4) (1) (2) (3) (4) -1 (5) -1 (c) (6) (1) (2) (3) (4) -1 (d) (5) (6) Figure 1: A example power-aware schedule: (a) A example loop, (b) its data depedece graph with d e values (assumig operatio latecy = 1), (c) a performace-drive schedule, ad (d) a power-aware schedule. for which a flat schedule exists. The MII is obtaied by separately cosiderig the depedece costrait ad the resource costrait, ad takig the larger value betwee two [6]. The cadidate II is iitially set to the MII ad icreased util a legal modulo schedule is foud. 4. POWER-AWARE MODULO SCHEDUL- ING ALGORITHM I this sectio, we preset a power-aware modulo schedulig algorithm that reduces both the step power ad peak power. Our mai requiremet i desigig such algorithms is that performace must ot be sacrificed for the reduced power cosumptio. 4.1 Problem Formulatio Usig the periodicity costrait, we ca formulate the power cosumptio at each time slot of the software pipelied loop of a sequetial loop as follows. (The superscript is used to distiguish the software pipelied loop from the origial sequetial loop.) Let O8 9 i be the set of operatios (icludig s) scheduled at the time slot i for i : II. The the power cosumed at time slot i, writte by P8 9 i, is estimated by P; < i s j 1 p op j (2) op O= > t where t?a@ i j 1B mod II If we cosider the ifiite executio of, which is represeted by the executio trace T8, the peak power is equal to max ic P8 9 i D i : IIE ad the step power at the cycle i is D P8 9 i mod II P8 9 F ig 1H mod II D. A software pipelied loop has the miimum peak power ad miimum step power whe all the P8 9 i values ( i : II) are equal to P8 F idealh. P8 F idealh is give by as follows: P; I idealj LK op 2M II 1 k? O= > k s p op jonqp II (3) j 1 Our goal i power-aware modulo schedulig is to fid opt such that RS T opt X YRS Z k for all k, where k represets the k-th software pipelied loop schedule of the sequetial loop. For such a opt, P8 9 opt i is as balaced as possible. Cosider a example loop show i Figure 1, which has the MII of 3 cycles. Both schedules i Figures 1(c) ad 1(d) are optimal i terms of performace achievig their IIs equal to the MII value. However, i terms of the step power ad the peak power, the latter is better tha the former. (The superscript i the operatio umber idicates the -th loop iteratio.) For example, if we assume equal p op j values, the schedule i Figure 1(c) has the twice bigger peak power over the schedule i Figure 1(d). Similarly, for the step power, the schedule i Figure 1(d) has o power differece while the schedule i Figure 1(c) has the largest value betwee the first ad secod istructios. This example clearly demostrates that there exist large differeces i power characteristics amog the schedules with the equal executio times. Our goal is to fid the power-efficiet schedules amog such performace-drive schedules without compromisig performace. 4.2 The Base Algorithm : Iterative Modulo Schedulig () We start with Rau s iterative modulo schedulig ( for short) as the base algorithm [13]. It outperforms the best-kow modulo schedulig algorithm by Lam [6]. Figure 2 describes a simplified versio of the algorithm. (Rau s origial algorithm icludes a sophisticated backtrackig procedure. For brevity, we do ot iclude it i Figure 2.) calls FINDFLATSCHEDULE with successively larger values of II, startig with a iitial value equal to the MII util the legal schedule is foud. FINDFLATSCHEDULE repeats pickig the highest priority operatio ad the selectig the best desirable time slot i which the operatio is to be scheduled. Rau used the priority fuctio based o the legth of the critical depedece cycle. Before selectig the best desirable time slot, COMPUTESLACK is called to compute the rage of time slots (i.e., slack) where the operatio may be placed without violatig depedece costraits with the operatios already scheduled. Give a path p v 1 [ v 2 []\,\,\^[ v k, let δ p ad d p represet kg i_ 1 1 δ v i ad kg i_ 1 1 d " v i v i` 1,, respectively. Assume that v has bee already scheduled ad v is about to be scheduled. Addig depedece costraits alog v p 1 p v ad v 2 v yields: σ v δ p 1 +4 II d p 1 %1 σ v# %1 σ v+4 δ p 2 II d p 2 Thus, the slack iterval, [MiTime,MaxTime], of v is computed 4 Of course, a ideal 8 geerally does ot exist because of the depedece costrait ad resource costrait.

4 c as: MiTime max v s K σ v s δ v s b v# +4 II d v s b v# ZN MaxTime max v s K σ v s +4 δ v# b v s II d v# b v s ZN where v s is ay scheduled operatio. From the computed slack, FINDTIMESLOT picks the best desirable time slot. Rau s origial algorithm selects the earliest time slot i which resource coflict is ot icurred. If o coflict-free slot is foud, the operatio caot be scheduled uless some operatios i the partial schedule are uscheduled. (The detailed descriptio of uschedulig procedure ca be foud i [13].) procedure II := MII(); /* iitialize the cadidate II to MII */ while (FINDFLATSCHEDULE(II)!= SUCCESS) II := II + 1; ed procedure fuctio FINDFLATSCHEDULE(II) /* compute the priority of each operatios */ COMPUTEPRIORITY(); /* repeat pickig the highest priority operatio ad selectig the best desirable time slot at which the operatio is to be scheduled util all operatios have bee scheduled */ while (some operatio is ot scheduled) /* pick the highest priority operatio */ CurrOper := HIGHESTPRIORITYOPERATION(); /* compute the time bouds i which the selected operatio ca be scheduled satisfyig the depedece costrait */ (MiTime, MaxTime) := COMPUTESLACK(CurrOper); /* select the best desirable time slot */ TimeSlot := FINDTIMESLOT( CurrOper, MiTime, MaxTime); /* schedule the operatio at TimeSlot. */ SCHEDULEOPERATION(CurrOper, TimeSlot); ed while if (all operatios are scheduled) retur SUCCESS; else retur FAIL; ed fuctio Figure 2: Origial algorithm. 4.3 Balaced () for Reduced Peak Power ad Step Power Cosumptio As explaied i Sectio 4.1, our goal is to fid schedule(s) with the most balaced power dissipatio distributio while ot sacrificig the performace that ca be obtaied from the origial. always places a operatio as early as possible (ASAP) withi the partial schedule costructed so far, resultig i a skewed schedule with a ubalaced power dissipatio distributio. This ASAP policy has bee widely used by software pipeliig researchers but is somewhat a legacy from a over-reliace o the ituitio uderlyig acyclic list schedulig. I cotrast, our algorithm tries to build balaced schedules usig a heuristic guided by the R) Z cost fuctio which idicates how much a power dissipatio distributio is balaced over the etire program executio. I order to make the origial algorithm to be power-aware, we make the followig two modificatios: c Priority Fuctio Modificatio Istead of the legth of the critical depedece cycle, we use the reciprocal of the slack width as the priority fuctio for a uscheduled operatio. Therefore, we eed to recompute the priority values at each iteratio of the while loop i FINDFLATSCHEDULE. With the modified priority fuctio, operatios with smaller slack widths are scheduled early so that performace is ot sacrificed. If these operatios are scheduled later, it is more likely that, for the curret II value, o legal schedule ca be foud. Although the re-computatio of the priority at each iteratio of the while loop may icur additioal compilatio time, we believe that the dyamic priority adjustmet provides more accurate critical-path iformatio, thus guarateeig that the resultig schedule does ot suffer ay performace loss. Time Slot Selectio Modificatio Whe selectig the best desirable time slot for the curret operatio to be scheduled, the balacig cost fuctio is used so that the partial schedule is costructed as balaced as possible. That is, the operatio is positioed ito the time slot at which icurs the least icrease of the flatess measure RS Z amog all the coflict-free time slots i the slack. Whe P8 F idealh is computed, oly the operatios i the partial schedule are cosidered. Ties are broke by the ASAP policy as i the origial to assist the critical-path cosideratio. I short, two major decisios are modified so that both performace ad power dissipatio distributio are simultaeously cosidered. 5. EXPERIMENTAL RESULTS I order to evaluate the power reductio effect of the algorithm over the origial algorithm, we implemeted the algorithm as well as the origial algorithm o a ARC-based VLIW testbed eviromet [12]. We icorporated our power model ito the schedulig modules as well as the simulator, so that the detailed istructio-level power statistics are collected. We experimeted with two machie cofiguratios, a 8-issue VLIW machie ad 16-issue VLIW machie, as described i Sectio 2. As test programs, EC95 FP bechmark programs were used. Sice the performace of parallel schedules produced by the algorithm should be as good as that of the schedules by the algorithm, we first compared the executio cycles of the schedules from two algorithms. I all the bechmark programs, there was egligible performace impact (: d 5%), which was due to the code differeces i prolog ad epilog code sectios, which are outside software-pipelied loop bodies. We also evaluated the performace of the schedules by the algorithm. If the performace is close to optimum, it implies that the schedule is tight ad there is ot much freedom i schedulig each operatio, resultig i small exploratio space for the. The quality of the was evaluated by comparig the actual II values with the theoretical MII values. 99.2% of the loops tested achieved their IIs equal to the MII values, idicatig that the algorithm fids high-quality schedules i terms of the performace. Eve uder this restrictive search space for power-aware schedules, the algorithm is quite effective i reducig the peak power ad step power cosumptio as show i the ext subsectios.

5 5.1 Impact o Peak Power Cosumptio 5.2 Impact o Step Power Cosumptio % 12 18% 16% 14% 12% 1 8% 6% -CDF % 12% 1 8% 6% -CDF % 2% 2 4% 2% ormalized power ormalized step power Figure 3: Normalized power distributio for a 8-issue VLIW machie. Figure 5: Normalized step power distributio for a 8-issue VLIW machie. 25% % 1 -CDF % 16% 14% 12% 1 8% 6% -CDF % 2 4% 2 2% ormalized power ormalized step power Figure 4: Normalized power distributio for a 16-issue VLIW machie. Figures 3 ad 4 show the impact o the peak power cosumptio of the proposed for the 8-issue ad 16-issue VLIW machie cofiguratios, respectively. The x axis of the graphs shows the ormalized power cosumptio values, 1 beig the maximum power dissipated uder the give machie cofiguratio. The y axis idicates the relative ratio (i percetage) of the cycles that cosumed the correspodig ormalized power durig the bechmark executios. The curves i the graphs represet the cumulative distributio fuctios (CDFs) of the ormalized power cosumptio. As show i Figures 3 ad 4, the average power of the schedules geerated from the algorithm are clustered aroud.57. O the other had, uder the, the bechmark executios sped the large umber of cycles at high power cosumptio levels. For example, for the 8-issue VLIW machie, the -geerated schedules sped 58.9% of their executio cycles cosumig more tha 7 of the maximum power. However, uder the, oly 8.8% of program executios were spet cosumig more tha 7 of the maximum power. Figures 3 ad 4 also illustrate the balacig effect of the algorithm o the P8 9 i distributio. For example, i Figure 3, the stadard deviatio of the ormalized power distributio uder the is.31 while it is reduced to.8 for the. As the umber of resources icreases, the search space to fid alterative schedules becomes bigger, thus the algorithm fids better schedules for machie cofiguratios with loger istructio words. Figure 6: Normalized step power distributio for a 16-issue VLIW machie. Figures 5 ad 6 illustrate the impact o the step power cosumptio of the for the 8-issue ad 16-issue VLIW machie cofiguratios, respectively. The x axis of the graphs shows the ormalized step power cosumptio values, 1 beig the maximum step power value uder the give machie cofiguratio. As with the peak power experimet, the schedules from the algorithm has smaller step power values over oes from the algorithm. For example, for the 16-issue VLIW machie, the geometric mea of step power values whe the is used is.41 while it is reduced to.24 whe the is used. 6. CONCLUSION AND FUTURE WORK We have described a power-aware modulo schedulig algorithm, Balaced (), for high-performace VLIW processors. The algorithm reduces the step power ad peak power cosumptio (which affect the processor reliability) from performacecritical loop bodies. The mai characteristics of the schedules from the algorithm is that their power cosumptio distributios are better balaced over power-uaware modulo schedulig algorithms. Experimetal results usig EC95 FP bechmark programs show that the proposed algorithm is effective i reducig both the step power ad peak power; I the case of step power cosumptio, the reduces o average 37.1% over the origial algorithm.

6 e The curret versio of the algorithm ca be further ehaced i several directios. For example, the algorithm ca be itegrated with post-pass low-power schedulig techiques such as [15, 7]. Although post-pass techiques work idepedetly of the algorithm, it will be iterestig to evaluate quatitatively the combied effect o the power cosumptio. We also pla to ivestigate how the affects the eergy efficiecy of aggressively clock-gated processors. Sice the tries to spread the operatio distributio evely while clock gatig prefers skewed executios, it will be a iterestig future work to exted the algorithm for such processors. 7. REFERENCES [1] J. R. Alle, K. Keedy, C. Porterfield, ad J. Warre. Coversio of Cotrol Depedece to Data Depedece. I Proc. of the 1983 Symposium o Priciples of Programmig Laguages, pages , [2] D. Brooks ad M. Martoosi. Dyamic Thermal Maagemet for High-Performace Microprocessors. I Proc. of the 7th Iteratioal Symposium o High-Performace Computer Architecture (HPCA-7), 21. [3] N. Chag, K. Kim, ad H. Lee. Cycle-Accurate Eergy Cosumptio Measuremet ad Aalysis: Case Study of ARM7TDMI. I Proc. of Iteratioal Symposium O Low Power Electroics ad Desig, pages , 2. [4] L.-F. Chao ad E. Sha. Schedulig Data-Flow Graphs via Retimig ad Ufoldig. IEEE Trasactios o Parallel ad Distributed Systems, 8(12): , [5] A. Dhodapkar, C. H. Lim, ad G. Cai. TEM2P2EST : A Thermal Eabled Multi-Model Power/Performace ESTimator. I Proc. of Workshop o Power-Aware Computer Systems, 2. [6] M. Lam. Software Pipeliig: A Effective Schedulig Techique for VLIW Machies. I Proc. of the SIGPLAN 1988 Coferece o Programmig Laguage Desig ad Implemetatio, pages , [7] C. Lee, J. K. Lee, T. Hwag, ad S.-C. Tsai. Compiler Optimizatio o Istructio Schedulig for Low Power. I Proc. of the 13th Iteratioal Symposium o System Sythesis, pages 55 6, 2. [8] C. E. Leiserso ad J. B. Saxe. Retimig Sychroous Circuitry. Algorithmica, 6:5 35, [9] M. Pat, P. Pat, D. Wills, ad V. Tiwari. A Architectural Solutio for the Iductive Noise Problem Due to Clock-gatig. I Proc. of Iteratioal Symposium O Low Power Electroics ad Desig, pages , [1] M. Pat, P. Pat, D. Wills, ad V. Tiwari. Iductive Noise Reductio at the Architectural Level. I Proc. of Iteratioal Coferece o VLSI Desig, pages , 2. [11] J. C. H. Park ad M. S. Schlasker. O Predicated Executio. Techical Report HPL-91-58, Hewlett Packard Laboratories, [12] S. Park, S. Shim, ad S.-M. Moo. Evaluatio of Schedulig Techiques o a ARC-Based VLIW Testbed. I Proc. of the 3th Aual Iteratioal Symposium o Microarchitecture (Micro-3), pages , [13] B. R. Rau. Iterative Modulo Schedulig: A Algorithm for Software Pipeliig Loops. I Proc. of the 27th Aual Iteratioal Symposium o Microarchitecture (Micro-27), pages 63 74, [14] M. Sami, D. Sciuto, C. Silvao, ad V. Zaccaria. Istructio-Level Power Estimatio for Embedded VLIW Cores. I Proc. of the 8th Iteratioal Workshop o Hardware/Software Codesig (CODES2), pages 34 38, 2. [15] D. Shi ad J. Kim. A Operatio Rearragemet Techique for Low Power VLIW Istructio Fetch. I Proc. of Workshop o Complexity-Effective Desig, 2. [16] Z. Tag, N. Chag, S. Li, W. Xie, S. Nakagawa, ad L. He. Ramp Up/Dow Floatig Poit Uit to Reduce Iductive Noise. I Proc. of Workshop o Power Aware Computer Systems, 2. [17] V. Tiwari, S. Malik, ad A. Wolfe. Power Aalysis of Embedded Software: A First Step Towards Software Power Miimizatio. IEEE Trasactios o VLSI Systems, 2(4): , [18] M. C. Tobure, T. Cote, ad M. Reilly. Istructio Schedulig for Low Power Dissipatio i High Performace Microprocessors. I Proc. of the Power Drive Microarchitecture Workshop, 1998.