Concurrent Fault Detection in Random Combinational Logic

Transcription

1 Cocurret Fault Detectio i Radom Combiatioal Logic Petros Drieas ad Yiorgos Makris Departmets of Computer Sciece ad Electrical Egieerig Yale Uiversity Abstract We discuss a o-itrusive methodology for cocurret fault detectio i radom combiatioal logic The proposed method is similar to duplicatio, wherei a replica of the circuit acts as a predictor that immediately detects potetial faults by compariso to the origial circuit However, istead of duplicatig the circuit, the proposed method selects a small umber of predictio logic fuctios which oly partially replicate it Selectio is guided by the objective of miimizig the icurred hardware overhead at the cost of itroducig fault detectio latecy To achieve this, the proposed method replicates oly a reduced width output fuctio for every iput combiatio, yet without compromisig the ability to detect all faults I cotrast to cocurret error detectio schemes which presume the ability to re-sythesize the circuit, the proposed method does ot iterfere with the implemetatio of the origial desig As compared to previous approaches, the proposed method achieves sigificat hardware overhead reductio, while detectig all faults with very low average fault detectio latecy 1 Itroductio Cocurret test provides circuits with the ability to selfexamie their operatioal health durig ormal fuctioality ad idicate potetial malfuctios While such a idicatio is highly desirable, desigig cocurretly self-testable circuits which also coform to the rest of the specificatios is ot trivial Issues to be addressed iclude the hardware cost ad desig effort icurred, performace degradatio due to iteractio betwee the circuit ad the self-test logic, as well as the level of assurace required I this paper, we devise a o-itrusive cocurret test methodology for radom combiatioal logic No-itrusiveess implies that hardware is oly added i parallel to the origial circuit, which is assumed to be optimized ad may ot be modified The additioal logic detects all faults i the circuit, therefore rederig a self-testable desig Moreover, self-test is performed cocurretly ad does ot degrade ormal fuctioality Cocurret test is based o the additio of hardware that moitors the iputs ad geerates a a priori kow property that should hold for the outputs A property verifier is utilized to idicate ay violatio of the property, thus detectig circuit malfuctios The simplest approach is to duplicate the circuit, imposig a idetity property betwee the origial output ad the replica output, which may be simply examied by a comparator With the exceptio of commomode failures [1], duplicatio will immediately detect all errors However, it also icurs sigificat hardware overhead that exceeds 100% of the cost of the origial circuit Sice electroic circuits are employed i a wide rage of applicatios, cocurret test methods of various cost ad efficiecy are required Towards this ed, we devise a cocurret fault detectio method for radom combiatioal logic that reduces hardware overhead at the cost of itroducig fault detectio latecy The method is based o Reduced Observatio Width Replicatio (ROWR) of the circuit, sufficiet to detect all structural faults, as opposed to duplicatio which detects all fuctioal errors After reviewig related work i sectio 2, the proposed method is preseted ad aalyzed i sectio 3 Experimetal results regardig hardware overhead, fault coverage, ad fault detectio latecy of the proposed method are provided i sectio 4 2 Related Work Almost all previous efforts i cocurret test share the objective of beig able to detect all faults What typically distiguishes them, however, is their positio withi the tradeoff space betwee hardware overhead ad fault detectio latecy Most approaches fall i oe of two eds of this space Towards the low ed, low cost self-test approaches have bee proposed for combiatioal circuits C-BIST [2] employs iput moitorig ad existig off-lie Built-I Self- Test hardware, such as LFSRs ad MISRs, to perform cocurret self-test While hardware overhead is very low, the method relies o a ordered appearace of all possible iput vectors before a sigature idicatig circuit correctess ca be calculated, resultig i very log fault detectio latecy This problem is alleviated i the R-CBIST method described i [3], where the requiremet for a uiquely ordered appearace of all iput combiatios is relaxed at the cost of a small RAM Nevertheless, all iput combiatios still eed to appear before ay idicatio of circuit correctess is provided Towards the high ed, we fid expesive cocurret error detectio methods for sequetial circuits that check the circuit fuctioality at every clock cycle, therefore guarateeig zero error detectio latecy However, reducig the area overhead below the cost of duplicatio typically requires redesig of the origial circuit, thus leadig to itrusive schemes Oe of the first attempts is described i [4], where resythesis is employed to ecode the states of the circuit, icorporatig parity ad employig totally selfcheckig (TSC) checkers [5] Limitatios such as structural /03 $ IEEE

2 ATPG TEST VECTORS SYNTHESIS IN CIRCUIT TEST VECTOR REPLICA OUT INEQUALITY COMPARATOR IS INPUT A TEST VECTOR? TEST OUTPUT I 1 I 0 O 0 No-Redudat Fault List {F 1,,F 10 Faults Detected At Each Output Bit: V V V V ,F 2,F 3 O 0 :{F 7,F 9,F 10,F 3 O 0 :{F 4,F 5,F 6,F 8 O 0 :{F 4,F 5,F 2 O 0 :{F 4,F 9,F 10 Figure 1 Test Vector Logic Replicatio (TVLR) costraits requirig a iverter-free desig, are alleviated i [6], where partitioig is employed to reduce the icurred hardware overhead Utilizatio of multiple parity bits is examied i [7] While these methods reder TSC circuits ad guaratee error detectio with zero latecy, they are itrusive ad oly provide savigs of up to 15% over duplicatio Amog the few approaches i betwee the two eds, a method that exploits properties of o-liear adaptive filters is proposed i [8] A similar techique itroducig latecy is proposed i [9], where the frequecy respose of liear filters is used as ivariace Additioally, a approach exploitig trasparecy of RT-Level compoets is described i [10] Fially, a cocurret fault detectio method for combiatioal logic is described i [11] This method, which we will refer to as Test Vector Logic Replicatio (TVLR), is depicted i Figure (1) Sice TVLR is similar to the method proposed herei, we describe it briefly to provide a basis for compariso ATPG is employed to geerate a complete set of test vectors, capable of detectig all o-redudat faults i the circuit This set is subsequetly sythesized to form the predictio logic, which is ow capable of geeratig the correct circuit respose oly for the complete set of test vectors Sice the objective is to miimize the hardware cost of the predictio logic, the remaiig iput combiatios are used as do t cares durig sythesis; therefore, the predictio logic will ot geerate correctly the circuit output for these combiatios To avoid false alarms, a additioal fuctio is used to idicate whether the iput combiatio is a test vector, ad cosequetly, whether the output of the comparator should be cosidered or discarded through the additioal AND gate TVLR is o-itrusive ad assumig that ATPG yields a complete set of test vectors, it is capable of detectig all faults However, it itroduces latecy i the detectio of a activated fault, which will remai udetected util a correspodig test vector appears at the circuit iputs 3 Reduced Observatio Width Replicatio While TVLR delivers hardware reductio over duplicatio at the cost of itroducig fault detectio latecy, it is oly oe possible solutio from a wide array of choices I a effort to explore the solutio space, we observe that for every iput combiatio, each output bit has the ability to detect a subset of all faults i the circuit, as show i Figure (2) Guarateeig detectio of all o-redudat faults requires that the predictio logic be capable of geeratig a adequate set of output bits, such that the uio of detected Figure 2 Reduced Observatio Width Example faults yields the complete o-redudat fault list TVLR selects such a set subject to the costrait that whe a output bit is icluded for a give iput combiatio, all output bits for this iput combiatio are icluded Subsequetly, the optimizatio objective is to miimize the umber of selected iput combiatios (test vectors), which is achieved through the Test Compactio phase of ATPG The uderlyig assumptio is that the output width of the predictio logic has to be equal to the output width of the circuit As a example, the miimal test set for the simple logic of Figure (2) comprises test vectors V 0,V 1,V 2 ad therefore the predictio logic has to be able to geerate a 2-bit fuctio for each of the 3 vectors, i total six bits Notice, however, that oly four of these bits are sufficiet to detect all faults, while the remaiig two are a additioal overhead imposed by the costrait of the method metioed above More specifically, bits ad O 0 for vector V 0, bit O 0 for vector V 1 ad bit for vector V 2 suffice to detect all faults Furthermore, otice that there exists a set of output bits capable of detectig all faults that requires replicatio of oly oe circuit output for every iput combiatio More specifically, bit for vectors V 0 ad V 2, ad bit O 0 for vectors V 1 ad V 3 suffice to detect all faults It is, therefore, possible that a less expesive predictio logic, geeratig a 1-bit fuctio for all 4 iput combiatios, as opposed to a 2-bit fuctio for 3 of the 4 iput combiatios, will suffice for detectig all faults This observatio is the basis for ROWR, the proposed method 31 Descriptio The optimizatio objective of ROWR is to miimize the output width of the predictio logic Based o the observatio that a subset of output bits per iput combiatio is typically sufficiet to detect all faults, the method aims at idetifyig a miimal such set More specifically, the predictio logic ow geerates oly k out of the circuit output bits, where k is the miimum umber of predicted bits per vector that detects all faults Hardware savigs are aticipated due to the reduced output width of the predicted fuctio The proposed scheme is depicted i Figure (3) For every m-bit iput combiatio, the predictio logic geerates k outputs that match a subset of k out of the output bits of the circuit Cosequetly, a Selectio Logic chooses which of the circuit outputs to drive to the comparator for each m- bit iput combiatio Two key issues eed to be addressed; amely, idetificatio of the output bits to be geerated by the predictio logic ad cost-effective selectio of the circuit outputs to which they should be compared /03 $ IEEE

3 IN m CIRCUIT OUT to 1 1 m SELECTION k MUXers log k to 1 1 k PREDICTION k INEQUALITY COMPARATOR TEST OUTPUT log m 1 ADDRESS Figure 3 Reduced Observatio Width Replicatio Regardig the first issue, a ATPG tool capable of geeratig all test vectors ad reportig both the good circuit ad the faulty circuit output for every fault is required This iformatio idicates the faults that ca be detected at each output bit for each iput combiatio ad may be used to costruct a table similar to the oe show i Figure (4) Ituitively, it may seem that the optimal solutio should comprise a set of colums that covers all faults, such that the maximum umber of output bits to be observed for ay iput vector is miimized This is ot true, however, sice the exact selectio of colums has a direct ad sigificat impact o the cost of the Selectio Logic, brigig us to the secod issue metioed above More specifically, sice the predictio logic oly geerates a k-bit fuctio, additioal logic is ecessary to select k amog the circuit outputs to which the predicted k bits will be compared As show i Figure (3), this ca be viewed as k-to-1 multiplexers, each of which requires log address bits Therefore, if we allow all possible subsets of size k for every m-bit iput combiatio, the Address Logic will comprise k log m-iput fuctios As compared to duplicatio, the predictio logic would implemet k fewer m-iput fuctios, at the cost of implemetig k log m-iput fuctios ad k-to-1 multiplexers for the Selectio logic Obviously, this is ot a wiig strategy if k>/(log +1), i which case k log > k Furthermore, the cost of the Selectio Logic is hard to estimate as k icreases, reducig to a zero-cost idetity fuctio i the extreme case of k = Therefore, restrictios eed to be imposed o the complexity permitted for the Address Logic ad, by extesio, to the acceptable sets of colums to cover the faults i the table of Figure (4) I the proposed methodology we elimiate the Address Logic all together, therefore allowig that the log select iputs of each multiplexer may oly be drive directly by ay log out of the m iputs bits VECTOR 0 OUT 0 OUT -1 Fault 1 1 Fault 2 Fault M VECTOR 2 m -1 OUT 0 OUT Figure 4 Fault Detectio Table We ow formally state the problem, assumig that we are give the table (say A) described above The first step partitios the 2 m iput combiatios i O() disjoit subsets, by selectig O(log ) iput bits (out of m) I each subset, we iclude all iputs (0 2 m ) that have the same value i the O(log ) selected bits I the secod step, for each subset, a set of k (1 k ) output bits is selected We emphasize that k is fixed for all subsets Thus, k 2 m colums of A are selected (out of 2 m ) We seek a algorithm to select k bits for each subset so that all faults are covered ad k is miimized The problem is NP-complete; we outlie a radomized algorithm to approximate it We solve the problem for a fixed k; fidig the miimum k is trivial usig biary search ad repeatig the followig algorithm log times We assume that the iputs are split i M subsets, deoted by S 1 S M ad, for each S i, we seek to idetify a set R i of k output bits Step 1: For each S i, fid all faults F i covered by exactly oe colum of A Iclude the bit correspodig to that colum i R i Remove all faults (rows of A) covered by this bit ad a vector i S i Repeat util all remaiig faults are covered by two or more colums of A Step 2: For each S i, fid all faults F i that are covered by vectors oly i S i Iclude i R i the miimum umber of bits required to cover all these faults (this is doe by exhaustive eumeratio i our experimets; elaborate approximatio algorithms exist [12]) Remove all faults (rows of A) covered by these bits ad a vector i S i Repeat util all remaiig faults are covered by two or more vectors i differet subsets Step 3: If ay R i k report failure Otherwise, radomly pick values for the k R i remaiig bits (i =1M) We repeat this step K times; if o combiatio coverig all faults is foud, we report failure We actually use a adaptive scheme for the radom samplig of values Similarly to TVLR, ROWR is o-itrusive ad guaratees 100% fault coverage Furthermore, sice ROWR predicts ad compares the appropriate portio of the circuit output for every iput combiatio, o false alarm is possible ROWR also itroduces latecy i the detectio of a activated fault, which will remai udetected util a appropriate vector appears at the circuit iputs We stress, however, that ROWR checks for faults for every iput combiatio, ulike TVLR which checks more ifrequetly Sice most stuck-at faults are detected by may iput vectors, we expect the average latecy of ROWR to be less tha that of TVLR /03 $ IEEE

4 CIRCUIT DUPLICATION TVLR ROWR COST COMPARISON COST VECTORS COST BITS COST TVLR vs DUPL ROWR vs DUPL 4_ / / % 5853 % 5_ / / % 4803 % 6_ / / % 5284 % 7_ / / % 4984% 8_ / / % 4324 % 9_ / / % 5209 % Figure 5 Hardware Overhead Compariso 4 Experimetal Results I this sectio, we compare TVLR ad ROWR to duplicatio, i terms of hardware overhead, fault coverage, ad fault detectio latecy We experimeted with ad report results for radom logic, sythesized usig SIS [13], ad mapped to a stadard cell library ATPG is performed usig ATALANTA [14] The test vector set is sythesized, rederig the predictio logic for TVLR The predictio for o-vectors is do t care, allowig SIS [13] to miimize the required hardware ATALANTA [14] is used to geerate all possible vectors detectig each fault, ad HOPE [15] is employed to provide the good machie ad the bad machie resposes for every (vector, fault) pair, revealig the output bits at which each fault may be detected for every vector This iformatio is used to costruct the table ad idetify the predictio fuctio ecessary for ROWR, which is also sythesized usig SIS [13] The cocurretly testable circuits are, the, costructed as described i sectios 2 ad 31 for TVLR ad ROWR respectively Compariso of the three alterative methods, Duplicatio, TVLR, ad ROWR is ow possible 41 Hardware Overhead Results are summarized i the table of Figure (5) for six differet sizes X Y of radom circuits, where X is the umber of iputs ad Y is the umber of outputs The umber of TVLR test vectors ad the width of the predicted ROWR fuctio are also reported ROWR achieves sigificatly better savigs tha TVLR, over duplicatio Eve for the smallest circuit, ROWR icurs 5853% overhead, while TVLR costs more that duplicatio For the above circuits, TVLR saves o average aroud 16% over duplicatio, while ROWR saves o average aroud 50% 42 Fault Coverage Both TVLR ad ROWR detect all o-redudat faults i the origial circuit To demostrate this, we costruct the complete cocurretly testable circuits as described i sectios 2 ad 31 for TVLR ad ROWR respectively Oly the test output is made observable, ad ATALANTA [14] is used to geerate test vectors for all o-redudat faults i the origial circuit The results are summarized i the table of Figure (6), where as expected, all faults are detectable by both the TVLR ad the ROWR method Also by costructio, both methods are expected to detect all o-redudat faults i the predictio logic circuit For these faults, the origial circuit acts as a duplicate, thus detectig them through the comparator To demostrate this, we performed ATPG for all faults i the complete circuit usig ATALANTA [14], observig both the test output ad the primary outputs of the circuit, thus obtaiig the list of all o-redudat faults i the circuit A fial ATPG ru for these faults, observig oly the test output, shows that all o-redudat faults i the circuit are detectable both by TVLR ad by ROWR 43 Fault Detectio Latecy Although the exact latecy itroduced by TVLR ad ROWR may ot be predicted, a experimetally obtaied idicatio is ecessary for their evaluatio Similarly to [2, 3, 11], we assume a uiform distributio at the circuit iputs ad employ fault simulatio of radomly geerated iput sequeces More specifically, for each method we use HOPE [15] to perform two fault simulatios of the same sequece of radomly geerated iputs, oce observig both the test output ad the circuit outputs, ad a secod time observig oly the test output The time step at which a fault is detected durig the first fault simulatio is the Fault Activatio time, while the time step at which a fault is detected durig the secod fault simulatio is the Fault Detectio time Fault Detectio Latecy is defied as the time differece betwee Fault Activatio ad Fault Detectio, therefore we ca easily calculate the Fault Detectio Latecy for each fault, as well as the average Fault Detectio Latecy Results are summarized i the table of Figure (7) for both TVLR ad ROWR We fault simulate a total of 5000 radom patters ad sapshots of the results are show after 10, 50, 100, 500, 1000, ad fially all 5000 patters have bee applied For each sapshot, we provide the umber of faults remaiig o-activated, the umber of faults activated ad detected, ad the umber of faults activated but ot yet detected We also provide the maximum ad the average fault detectio latecy for the faults that are both activated ad detected Based o the results, we observe the followig: TVLR ROWR CIRCUIT ORIGINAL ALL ORIGINAL ALL FAULTS FAULTS FAULTS FAULTS 4_4 60 / / / / 150 5_5 181 / / / / 348 6_6 387 / / / / 676 7_7 819 / / / / _ / / / / _ / / / / 5781 Figure 6 Fault Coverage by TVLR ad ROWR /03 $ IEEE

5 4_4 0 5_ _ _ _ _ CIRCUIT TESTABLE FAULTS REMAINING DETECTED MISSED MAX LAT AVG LAT REMAINING DETECTED MISSED MAX LAT AVG LAT REMAINING DETECTED MISSED MAX LAT AVG LAT REMAINING DETECTED MISSED MAX LAT AVG LAT REMAINING DETECTED MISSED MAX LAT AVG LAT REMAINING DETECTED MISSED MAX LAT AVG LAT TVLR ROWR TVLR ROWR TVLR ROWR TVLR ROWR TVLR ROWR TVLR ROWR STATISTIC Figure 7 Fault Detectio Latecy for TVLR ad ROWR Detected faults Average latecy Activated Detected (ROWR) Detected (TVLR) 500 Number of radom iputs Figure 8 Faults vs Number of Patters for ROWR TVLR 0 Number of radom iputs Figure 10 Latecy vs Number of Patters for Detected faults Average latecy Activated Detected (ROWR) Detected (TVLR) 500 Number of radom iputs Figure 9 Faults vs Number of Patters for ROWR TVLR 0 Number of radom iputs Figure 11 Latecy vs Number of Patters for /03 $ IEEE

6 While the MAX latecy is O(N log N) vectors, the AVG latecy rages oly up to 68 vectors for TVLR ad up to 24 vectors for ROWR For example, oce all faults are detected i the 9 9 circuit, where N log N=4608, the MAX latecy is 2075 vectors for TVLR ad 1738 vectors for ROWR However, the AVG latecy is 6767 vectors for TVLR ad 2360 vectors for ROWR, which is oly the 326% ad 135% of the respective MAX latecy Similar observatios hold for all circuits For both TVLR ad ROWR most faults are detected quickly ad a rule applies for the AVG latecy: 90% of the faults are detected withi 50% of the AVG latecy, while the other 50% is cotributed by the remaiig 10% of the faults For example, oce 500 vectors are applied to the 9 9 circuit, 9817% of all faults are activated, out of which 9365% are detected by TVLR ad 9654% by ROWR The AVG fault detectio latecy at this poit is 3740 vectors for TVLR ad 1450 vectors for ROWR, which represets the 5526% ad 6144% of the AVG latecy whe all faults are detected Similar observatios hold for all circuits Furthermore, a comparative latecy examiatio of TVLR ad ROWR leads to the followig two observatios: ROWR detects more faults slightly faster tha TVLR A plot of the faults activated, faults detected by TVLR, ad faults detected by ROWR as the umber of applied radom patters icreases is give i Figures 8 ad 9 for circuits 8 8 ad 9 9, respectively As demostrated, ROWR cosistetly detects more faults faster tha TVLR, up to the covergece poit where all faults are detected by both methods The observatio holds for all circuits ad, iterestigly, the gai is larger as the size of the circuit icreases ROWR detects faults with sigificatly lower AVG latecy tha TVLR A plot of the AVG fault detectio latecy of ROWR ad TVLR as the umber of applied radom patters icreases is give i Figures 10 ad 11 for circuits 8 8 ad 9 9 respectively As demostrated, ROWR cosistetly detects faults with lower AVG latecy tha TVLR Oce agai, the observatio holds for all circuits ad, iterestigly, the gai is larger as the size of the circuit icreases 5 Coclusios Cost-effective cocurret fault detectio requires careful examiatio of the trade-offs betwee the coflictig objectives of low hardware overhead, low fault detectio latecy, ad high fault coverage ROWR explores the trade-off betwee fault detectio latecy ad hardware overhead, uder the costrait that the origial circuit may ot be altered Thus, a compariso-based approach is employed, where the origial circuit is partially replicated ito a predictio logic that selectively tests the circuit durig ormal operatio The problem of idetifyig cost-effective predictio logic fuctios is theoretically formulated ad a algorithm for efficiet partial replicatio is proposed Experimetal results demostrate that ROWR reduces sigificatly the hardware overhead icurred by either duplicatio or TVLR, while preservig the ability to detect all permaet faults i the circuit Further reductio of this overhead is aticipated as the size of the circuit icreases While these savigs come at the cost of itroducig fault detectio latecy, the experimetally observed average latecy is lower tha the latecy of TVLR ad scales sub-liearly with the size of the circuit Thus, whe o-zero fault detectio latecy may be tolerated, ROWR is a superior alterative to both duplicatio ad TVLR Refereces [1] A Avizieis ad J P J Kelly, Fault tolerace by desig diversity: Cocepts ad experimets, IEEE Computer, vol 17, o 8, pp 67 80, 1984 [2] K K Saluja, R Sharma, ad C R Kime, A cocurret testig techique for digital circuits, IEEE TCAD, vol 7, o 12, pp , 1988 [3] I Voyiatzis, A Paschalis, D Nikolos, ad C Halatsis, R- CBIST: A effective RAM-based iput vector moitorig cocurret BIST techique, i ITC, 1998, pp [4] N K Jha ad S-J Wag, Desig ad sythesis of selfcheckig VLSI circuits, IEEE TCAD, vol 12, o 6, pp , 1993 [5] D Nikolos, Optimal self-testig embedded parity checkers, IEEE TCOMP, vol 47, o 3, pp , 1998 [6] N A Touba ad E J McCluskey, Logic sythesis of multilevel circuits with cocurret error detectio, IEEE TCAD, vol 16, o 7, pp , 1997 [7] C Zeg, N Saxea, ad E J McCluskey, Fiite state machie sythesis with cocurret error detectio, i ITC, 1999, pp [8] A Chatterjee ad R K Roy, Cocurret error detectio i o-liear digital circuits with applicatios to adaptive filters, i ICCD, 1993, pp [9] I Bayraktaroglu ad A Orailoglu, Low-cost o-lie test for digital filters, i VTS, 1999, pp [10] Y Makris, I Bayraktaroglu, ad A Orailoglu, Ivariacebased o-lie test for RTL cotroller-datapath circuits, i VTS, 2000, pp [11] R Sharma ad K K Saluja, A implemetatio ad aalysis of a cocurret built-i self-test techique, i FTCS, 1988, pp [12] R Motwai ad P Raghava, Radomized Algorithms, Cambridge Uiversity Press, 3rd editio, 1995 [13] E M Setovich et al, SIS: a system for sequetial circuit sythesis, ERL MEMO No UCB/ERL M92/41, EECS UC Berkeley CA 94720, 1992 [14] ATALANTA combiatioal test geeratio tool, Available from [15] H K Lee ad D S Ha, HOPE: A efficiet parallel fault simulator for sychroous sequetial circuits, IEEE TCAD, vol 15, o 9, pp , /03 $ IEEE