Frequency Offset Estimation With Improved Convergence Time and Energy Consumption

Transcription

1 Frequecy Offset Estimatio With Improved Covergece Time ad Eergy Cosumptio M. Josie Ammer ad Ja Rabaey {mjammer, Uiversity of Califoria, Berkeley Abstract-A approach to simultaeously improve the eergy cosumptio ad covergece time (give the iput SNR ad required estimatio variace) of feed-forward data-aided frequecy estimatio is preseted. Four well-kow frequecy estimatio algorithms are compared usig actual ASIC hardware implemetatios to verify the results. It is demostrated how a modificatio to the algorithms ca simultaeously achieve lower eergy cosumptio ad improved covergece time. For example, for a iput SNR of 1dB ad required estimatio variace of 1-5, covergece time is decreased by a factor of while decreasig the eergy cosumptio by a factor of.3. Directios o how to apply these algorithms to spread spectrum systems are provided. INTRODUCTION I a typical wireless commuicatio system, imperfect upad dow-coversio caused by oidealities i the trasmitter ad receiver local oscillators (O) result i a carrier offset at the receiver. This offset causes a cotiuous rotatio of the sigal costellatio, ad must be corrected for reliable demodulatio of the received sigal. I some commuicatio systems, carrier recovery is performed by a phase-locked loop (P). However, if the carrier offset is greater tha the pull-i rage of the P, a coarse feedforward frequecy estimatio ad correctio must be performed before the sigal eters the P []. I some systems, the P is ot used i favor of a all-feed-forward algorithm. Covergece time of the sychroizatio subsystem is critical i wireless systems. If implemetig a stadardized wireless system, such as.11b, sychroizatio time is limited by the stadard s preamble or sych word. Improved covergece time for oe sychroizatio parameter may mea beig able to icrease system performace ad reliability by allocatig more of the sych word to the estimatio of this or other sychroizatio parameters. I the case of a o-stadardized wireless system, improved covergece time allows the use of a shorter sych word, reducig the packet overhead ad thereby reducig the system power cosumptio. Sice most wireless commuicatio devices are batterypowered, low power operatio is a primary cocer. owpower research is cocetrated i the RF, MAC, Network ad Applicatio layers of the wireless device while the sychroizatio system is ofte overlooked. However, sychroizatio systems for several commo wireless stadards, such as Bluetooth ad.11a take up more tha 15% of the physical layer die area. While the power cosumptio umbers are ot separately reported, we ca assume that the sychroizatio system power cosumptio is sigificat because of its sigificat area ad high clock rates. Ideed, i our ow work, we have foud the sychroizatio to have sigificat power cosumptio [] (approx 15% of the system power). This work examies four feed-forward data-aided frequecy offset estimatio algorithms ad compares the estimatio performace ad power cosumptio of each over estimatio legth ad iput SNR. A modificatio of these algorithms is preseted that simultaeously achieves lower power ad faster covergece time. FREQUENCY ESTIMATION AGORITHMS As described i [1] ad [], i the absece of ISI ad with moderate frequecy offset (less tha ~15% of the symbol rate), the sampled output of the matched filter (at oe sample per symbol), assumig perfect symbol sychroizatio, is give by j( φ T r = ae ω ) w, (1) where a is the th (complex) data symbol, φ is the carrier phase, ω is the carrier frequecy offset, T is the symbol duratio, ad w is a complex Gaussia white oise process with idepedet, zero-mea real ad imagiary parts each with variace σ = N /(E s ) where E s is the symbol eergy ad N, the oe-sided spectral desity of the oise. Also, as i [], we use the coveiet otatio of ormalized frequecy offset, defied as Ω = ωt. We examie the case of data-aided estimatio where the kow data symbols are removed before frequecy estimatio. This reduces to the problem of frequecy estimatio with a umodulated carrier []. This is the most commo use of frequecy estimatio i systems where a sychroizatio header is used, such as.11b. There are two well-kow algorithms for frequecy estimatio operatig with timig iformatio derived from the maximum likelihood equatios. The differece betwee the two depeds o whether or ot the agle of r is take before derivig the M algorithm. If the agle is take before, the result is the estimator[], This work is fuded by DARPA, GSRC, ad the BWRC member compaies.

2 Ω ˆ = 1 = 1 { r r } b arg, () 1 if the agle is take after, the result is the estimator [1], Ω = 1 ˆ arg b ( r r 1), (3) = 1 where 6( ) b =. () ( 1) Neither algorithm requires phase uwrappig, ad both are limited to frequecy offsets that obey Ω < π (5) It should be oted, that while differet weightig fuctios, b, ca be used, the oe give i () is optimal. A simplificatio, suggested i [1], that is ofte used i practice, substitutes a itegrate-ad-dump filter (b =1/) that computes a uweighted average, for the filter fuctio i () that computes a weighted average. We apply this simplificatio to both the ad estimators to expad the umber of estimators cosidered here to be four. The variace of the weighted Ωˆ Mw ad uweighted Ωˆ versios of the estimator are give i [1] as, [ ˆ Var Ω Mw ] = (6) ( 1) E ( ) s 5 1 Es ad 1 1 Var[ Ωˆ ] = E ( ) s Es. (7) The simulated performace of the four estimators ( weighted ad uweighted ad weighted ad uweighted) is show i Figure 1. Va riace 1.E-1 1.E- 1.E-3 1.E- 1.E-5 1.E-6 1.E-7 1.E- 1.E-9 1.E-1 1.E-11 SNR=1dB SNR=dB SNR=dB SNR=1dB SNR=dB Figure 1: ad ad Performace. The simulatios match the performace predicted by very closely. As expected, at high SNR, the performace of the two weighted estimators approach the Modified Cramer- Rao boud give i [] as 6 MCRB( Ω ) =. () ( 1)( Es ) While these algorithms have bee derived for the flat fadig chael, i practice, they also work for the frequecy selective fadig chael. The improved covergece time is achieved by exploitig a little-kow modificatio to these algorithms described i [1]. I the estimator equatios, the product, ( r ) is replaced with ( r r ). While this is ot a ew result, it is ofte D overlooked, for istace i [3]. The variace of the estimator is improved roughly as D. For istace, the performace of the uweighted estimator is give i [1] by [ Ωˆ 1 ] D 1 Var = / ( ). (9) D Es N Es The algorithms are ow limited to frequecy offsets that obey ΩD < π. (1) I practice, may systems ca tolerate D>1. If followig the rule of thumb that frequecy offset should be less tha 15% of the symbol rate, the D 3 is possible. I.11b, with a 5ppm carrier offset from a.ghz referece, the maximum frequecy offset is /- 1KHz, allowig D= to be used. Figure shows that eve D= yields a huge improvemet (decrease) i for a give variace. 1.E-1 1.E- 1.E-3 1.E- 1.E-5 1.E-6 1.E-7 1.E- 1.E-9 1.E r 1 D=1 D= SNR=1dB SNR=dB SNR=dB Figure : D=1, Performace. The block diagrams for the ad weighted estimators are show i Figure 3 ad Figure. To implemet the uweighted estimators, oe or two scalar multipliers are removed from the or estimators respectively.

3 I Q I Q Z -D complex Rect to S Polar b clear Figure 3: Block Diagram of the Estimator. Z -D complex b clear Figure : Block Diagram of the Estimator. SS Rect to Polar The goal is to choose the lowest power frequecy estimatio algorithm to achieve a give variace. The Mery ad algorithms seem to have similar hardware complexity upo first glace because they cosist of the same operatios but i a differet order. However, the orderig of operatios i hardware ca have a large impact o the power cosumptio. The simplificatio suggested i [1] of b =1/, reduces the hardware, but icurs a performace pealty. It is uclear at what poit, if ay, this hardware simplificatio will actually decrease eergy cosumptio. Icreasig D requires margially more hardware but gives a sigificat improvemet i performace. It is expected that this will be a good tradeoff because the hardware cost is so small. However, it is ukow by oly lookig at the estimator equatio ad the variace performace which algorithm to choose for a low power system. POWER ESTIMATION METHODOOGY Each frequecy estimatio algorithm was coded as a parameterized module i a high-level hardware descriptio laguage i Syopsys Module Compiler. Each module was sythesized i Module Compiler for a rage of parameters, such as iput SNR ad estimatio legth. Each sythesized VHD etlist from Module Compiler is icremetally compiled i Syopsys Desig Compiler to isert a clock tree ad to add buffer delays to fix hold time violatios. This step is very importat to get accurate power cosumptio because the clock tree ad delay buffers ca accout for 3-5% of the block power depedig o the ratio of registers to combiatioal logic. The block is the simulated at the gate level i ModelSim usig realistic iput vectors to verify fuctioality ad to determie the switchig activity o each ode. Simulatio usig realistic vectors is importat because it accurately characterizes the correlatio i the data stream that ofte exists i commuicatio systems which results i reduced power cosumptio versus usig statistical switchig activity. Syopsys Power Compiler is used to estimate the power cosumptio of the block usig the back aotated switchig activity ad statistical wire load models. Our ow experimets o several frequecy estimatio blocks with Ωˆ Kw Ωˆ Mw varyig iput ad output bit-widths have show this gate-level estimatio method to be accurate to withi 15% of the power cosumptio estimated by extractig parasitics from a postplace-ad-route block ad simulatig usig a switch-level simulator like PowerMill or NaoSim. Our ow experiece ad reports from our foudry have show that switch-level simulatios give 1-15% agreemet with power cosumptio of actual chips. Gate-level power estimatio is used because it is over 5 times faster tha switch-level simulatio (ot icludig the time it takes to place-ad-route the block as required to extract accurate parasitics). The total time to characterize all 1 differet chose istatiatios (3 differet SNR s, 7 differet s) of each algorithm is uder 3 hours usig the gate-level method. Eergy, rather tha power, is used as the cost metric for each block. This is because the frequecy estimatio takes a differet umber of cycles depedig o the iput SNR, required estimatio variace, ad which algorithm is selected. Aggressive low power desigs will gate the clock ad power rails to the frequecy estimatio block whe ot i use. Therefore, the way to fairly compare differet blocks is the eergy cosumptio, which is the power cosumed whe the block is o times the amout of time the block eeds to be o to achieve the desired variace. The eergy cosumptio reported here is for a.13um CMOS process. While the actual eergy cosumptio will chage for differet processes, the compariso of oe algorithm vs. aother is valid for most cotemporary processes. Obviously, the ratio of leakage power to switchig power ad power cosumed i the wires will vary betwee process ad this will alter the crossover poits of the curves, however the geeral results will remai true. AGORITHM COMPARISON AND RESUTS For each implemetatio, it is assumed that the umber of bits at the iput to the estimator is scaled depedig o the iput SNR. This is a reasoable assumptio because most systems employ good AGC ad would ot pay the cost pealty of implemetig a ADC that coverted more bits tha ecessary or a frequecy estimator that achieved better precisio tha was eeded. The bit widths are scaled up i subsequet blocks to accommodate the growig precisio. The accumulators are pre-scaled to accommodate the summatio of samples, ad the precisio of the weightig taps, b, is icreased with. The b coefficiets are hardwired before sythesis for the lowest power operatio. The rectagular-to-polar coversio is performed by a CORDIC [6] ad the umber of CORDIC stages is icreased depedig o the required precisio. These adjustmets esure that the hardware is ot sigificatly limitig the expected variace. The resultig eergy cosumptio of each estimator is show versus variace for a rage of iput SNR ad. Sice lower variace ad lower eergy cosumptio are desired, data poits to the bottom ad left are better. While this is the right presetatio of the data for optimizig the eergy of the frequecy estimator i isolatio, must be cosidered if a system-wide reductio i power cosumptio is to be

4 achieved because the RF ad aalog frot-ed are o for differet amouts of time. For istace, i the case where the frot-ed power domiates that of the frequecy estimatio, choosig a algorithm with smaller may optimize system eergy eve if it has higher frequecy estimatio eergy. Sice the absolute eergy cosumptio ad the for each data poit is give i the graphs, the desiger ca make the appropriate trade-off. Obviously, cases where both the power cosumptio ad covergece time () are decreased for the same variace are hads-dow wiers. Figure 5 compares the eergy cosumptio vs. variace of the weighted ad uweighted versios of the algorithm. At low SNR ad at high required variace, it is more eergy efficiet to use the o-weighted versio. Here, there is a small differece i variace betwee the two algorithms, so the hardware simplificatio of uweighted combiig pays off. However, at high SNR or low variace, it is more eergy efficiet to use the weightig fuctio. Here the eergy savigs from the uweighted averagig are outweighed by the loger correlatio times required to overcome the degradatio i variace. For istace, at db SNR, ad a required variace of 3x1-7, the uweighted estimator coverges i 1 samples, whereas the weighted estimator takes oly samples ad as a result, cosumes margially less eergy. Figure 6 compares the weighted ad uweighted versios of the algorithm. For the estimator, it is almost always better to use the weighted versio of the algorithm. This is to be expected because the variace of the uweighted versio of the algorithm severely uder performs the weighted versio. I this case, the hardware simplificatio of a uweighted average is ot worth the degradatio i variace. For istace, at db SNR, ad a required variace of x1-6, the uweighted estimator coverges i 1 samples, whereas the weighted estimator takes oly 3 samples ad as a result, cosumes 1/3 as much eergy. Eergy (pj) 1.E5 1.E 1.E3 1.E 1.E1 1.E SNR=dB SNR=dB SNR=1dB = E E-9 1.E- 7 1.E-5 1.E- 1.E-6 1.E- 1.E- 1.E-6 1.E- 1.E- 1.E Eergy (pj) 1.E 1.E3 1.E 1.E1 1.E SNR=dB SNR=1dB = E- 9 1.E-7 1.E- 5 1.E- 3 1.E- 1 1.E- 1.E-6 1.E- 1.E- 1.E Figure 5: vs. Compariso. Figure 6: vs. Compariso. Eergy (pj) 1.E5 1.E 1.E3 1.E 1.E1 1.E SNR=dB 1.E E- 9 1.E- 7 1.E-5 SNR=dB SNR=1dB = E- 1.E-6 1.E- 1.E- 1.E- 7 1.E- 5 1.E-3 1.E- 1 Eergy (pj) 1.E5 1.E 1.E3 1.E 1.E1 1.E D=1 D= SNR=dB = E- 1.E- 6 1.E- 1.E- 1.E-6 1.E- 1.E- 1.E SNR=1dB Figure 7: vs. Compariso. Figure : D=1 vs. D= Compariso.

5 Figure 7 compares the weighted versios of the ad algorithms. The weighted algorithm is almost always better tha or equal to the weighted algorithm. At low SNR, the marked advatage of the algorithm is due to the combiatio of achievig better variace ad requirig cosiderably less hardware to implemet tha the algorithm. At high SNR where the algorithms have similar variace performace ad similar hardware requiremets, the mior differeces mostly result from the correlatio of the data as it flows though the hardware. At high variace there is little differece betwee the two, while at low variace the algorithm wis out. Figure compares the weighted versio of the algorithm for D=1,. Icreasig D is almost always the right choice, especially for low variace. The power pealty is very small (oly oe extra register) ad the covergece time ca be markedly better. For example, for a iput SNR of 1dB ad required estimatio variace of 1-5, the covergece time is decreased by a factor of while simultaeously decreasig the eergy cosumptio by a factor of.3. APPICATION TO DSSS SYSTEMS For DSSS, it is sometimes suggested i the literature to apply these frequecy estimatio algorithms to chips rather tha symbols to maximize D; this is ot usually advatageous. Whereas the ormalized frequecy offset, Ω = ωt, is used i this paper, whe comparig the variace betwee chips ad symbols, the o-ormalized variace, Var[ ω]=var[ω]/t, must be used. Whe operatig o chips rather tha symbols, D is icreased by a factor of N (where N is the spreadig code legth) but both T ad SNR are decreased by a factor of N. Assumig the same header legth ad miimal power loss i the code correlator due to frequecy offset, the performace whe operatig o chips is sigificatly worse tha whe operatig o symbols. The oly time oe would operate o chips is with a large frequecy offset. If, the costrait i (5) is ot satisfied for symbol operatio, oe could operate o chips ad still be able to use the algorithms described above without havig to resort to more complex FFT-based algorithms. The pealty for performig frequecy estimatio o chips is reduced whe there is severe SNR degradatio i the code correlator due to a large frequecy offset. For.11b-like symbols (11-bit barker sequece spreadig, root-raised cosie trasmit ad receive filters w/ 5% excess badwidth), the power loss for correlatio prior to frequecy-offset correctio is approximately 3db with a 6Khz offset. Depedig o the required variace, it may be advatageous to do a coarse frequecy estimatio by operatig o chips, the perform a coarse frequecy correctio, correlate to symbols, ad perform the fie frequecy estimatio by operatig o symbols. I all cases, because of the SNR degradatio due to correlatio i the presece of frequecy offset, eve if frequecy-offset estimatio is performed o symbols, the frequecy-offset correctio should be applied to chips. CONCUSIONS Four feed-forward frequecy estimators were characterized for eergy cosumptio ad variace for a give iput SNR ad correlatio legth. It was foud that the weighted estimator is a safe bet for all regios of operatio, especially for high SNR ad low required variace. The uweighted estimator may be used for low SNR ad high required variace. Exploitig D is the most powerful way to simultaeously decrease covergece time ad eergy cosumptio especially for low required variace. It is surprisig to fid that certai hardware simplificatios, such as usig D=1 ad uweighted averagig does ot usually result i lower eergy cosumptio. The degradatio i variace due to these simplificatios requires loger covergece times ad more eergy cosumptio. ACKNOWEDGMENT The authors would like to thak Mike Sheets for his valuable help with the power estimatio methodology. REFERENCES [1] H., M. Moeeclaey, ad S. A. Fechtel, Digital Commuicatio Receivers: Sychroizatio, Chael Estimatio ad Sigal Processig, Wiley Press, 199. [] G. Tavares,. Tavares, ad M. Piedade, Improved Cramer-Rao ower Bouds for Phase ad Frequecy Estimatio With M-PSK Sigals, IEEE Trasactios o Commuicatios, Vol. 9, No. 1, December 1. [3] K. Barma ad V Reddy, Maximum iklihood Clock ad Carrier Recovery i a Direct Sequece Spread Spectrum Commuicatio System, Proceedigs of the Iteratioal Coferece o Persoal Wireless Commuicatio,. [] M. J. Ammer, M. Sheets, T. Karalar, M. Kuulusa, ad J. Rabaey, A ow-eergy Chip-Set for Wireless Itercom, Proceedigs of the Desig Automatio Coferece (DAC), 3. [5] O. Besso ad P. Stoica, O Frequecy Offset Estimatio for Flat- Fadig Chaels, IEEE Commuicatio etters, Vol. 5, Issue 1, October 1. [6] K. Turkowski, Fixed-Poit Trigoometry with CORDIC Iteratios. Apple Computer White Paper, Jauary 17, 199.