ECE5461: Low Power SoC Design. Tae Hee Han: Semiconductor Systems Engineering Sungkyunkwan University

Transcription

1 ECE5461: Low Power SoC Desig Tae Hee Ha: Semicoductor Systems Egieerig Sugkyukwa Uiversity

2 Low Power SRAM Issue 2

3 Role of Memory i ICs Memory is very importat Focus i this lecture is embedded memory Percetage of area goig to memory is icreasig 3

4 Itroductio SRAM is the most commo embedded-memory optio for CMOS ICs As the supply voltage of low power ICs decreases, it must remai compatible with the operatig coditios At the same time, icreasigly parallel architectures demad more o-chip cache (or embedded SRAM array) to effectively share iformatio across parallel processig uits Achievig low-voltage operatio i SRAM faces a challeges, origiatig from process variatio, ad related to bit cell stability, sesig, architecture, ad efficiet CAD methodologies 4

5 Processor Area Becomig Memory Domiated SRAM Itel Pery (Picture courtesy of Itel) O chip SRAM cotais 50-90% of total trasistor cout Xeo: 48M/110M Itaium 2: 144M/220M SRAM is a major source of chip static power dissipatio Domiat i ultra-low power applicatios Substatial fractio i others 5

6 SRAM Metrics Fuctioality Data retetio Readability Writability Soft Errors Area Power Why is fuctioality a metric? Process variatios icrease with scalig Large umber of cells requires aalysis of tails (out to 6σ or 7σ) Withi-die V TH variatio due to Radom Dopat Fluctuatios (RDFs) 6

7 Where Does SRAM Power Go? Numerous aalytical SRAM power models Great variety i power breakdows Differet applicatios cause differet compoets of power to domiate Hece: Depeds o applicatios: e.g. high speed versus low power, portable 7

8 SRAM cell BL BL WL Q M3 M6 M2 M5 M1 M4 QB Traditioal 6-Trasistor (6T) SRAM cell wordlie Three tasks of a cell Hold data Write WL=0; BLs=X WL=1; BLs drive with ew data Read WL=1; BLs precharged ad left floatig b b 8

9 Key SRAM cell metrics BL BL WL Q M3 M6 M2 M5 M1 M4 QB Traditioal 6-Trasistor (6T) SRAM cell Key fuctioality metrics Hold Read Write Static Noise Margi (SNM) Data retetio voltage (DRV) Static Noise Margi (SNM) Write Margi Metrics: Area is primary costrait Next: Power, Delay 9

10 Static Noise Margi (SNM) BL WL BLB SNM gives a measure of the cell s stability by quatifyig the DC oise required to flip the cell M2 Q M3 M1 V N V N M6 M4 M5 QB Iv 1 Iv 2 QB(V) SNM VTC for Iv 2 VTC -1 for Iv 1 VTC for Iv2 with VN = SNM VTC -1 for Iv1 with VN = SNM SNM is legth of side of the largest embedded square o the butterfly curve Q (V) * VTC: Voltage Trasfer Curve 10

11 Static Noise Margi with Scalig Typical cell SNM deteriorates with scalig Variatios lead to failure from isufficiet SNM Tech ad V DD scalig lower SNM Variatios worse tail of SNM distributio (Results obtaied from simulatios with Predictive Techology Models [Ref: PTM; Y. Cao 00]) 11

12 Variability: Write Margi BL BLB WL Normalized QB Write failure: Positive SNM Domiat fight (ratioed) Normalized Q Cell stability prior to write: Normalized QB Normalized QB Successful write: Negative SNM Normalized Q Normalized Q 12

13 Variability: Cell Writability V DD =0.6V Write Fails SNM (V) TT WW -0.2 SS WS SW Temperature ( o C) Write margi limits V DD scalig for 6T cells to 600mV, best case. 65m process, V DD = 0.6V Variability ad large umber of cells makes this worse 13

14 Cell Array Power Leakage Power domiates while the memory holds data BL WL BL 0 1 Importace of Gate tuelig ad GIDL depeds o techology ad voltages applied Sub-threshold leakage 14

15 Usig Threshold Voltage to Reduce Leakage High V TH cells ecessary if all else is kept the same To keep leakage i 1 MB memory withi bouds, V TH must be kept i [0.4, 0.6] rage 1-Mb array retetio curret (A) 10 0 T j =125 C L g =0.1 mm 100 C W (Q T)=0.20 mm 75 C W (Q D)=0.28 mm W (Q L)=0.18 mm 50 C 25 C ma 0.1 ma high speed (0.49) low power (0.71) Average extrapolated V TH (V) at 25 ºC Extrapolated V TH =V TH (A/mm)+0.3 V [Ref: K. Itoh, ISCAS 06] 15

16 Multiple Threshold Voltages BL WL BL BL WL BL 0 Dual V TH cells with low V TH access trasistors provide good tradeoffs i power ad delay [Ref: Hamzaoglu, et al., TVLSI 02] High V TH Use high V TH devices to lower leakage for stored 0, which is much more commo tha a stored 1 Low V TH 16

17 Multiple Voltages Selective usage of multiple voltages i cell array e.g. 16 fa/cell at 25 C i 0.13 μm techology 1.0V 1.0V WL=0V 1.5V 0.5V High V TH to lower sub-v TH leakage Raised source, raised V DD, ad lower BL reduce gate stress while maitaiig SNM [Ref: K. Osada, JSSC 03] 17

18 Power Breakdow Durig Read Accessig correct cell V DD_Prech Decoders, WL drivers For Lower Power: hierarchical WLs Address Mem Cell WL pulsed decoders Performig read Charge ad discharge large BL capacitace Sese Amp Data For Lower Power: SAs ad low BL swig Lower V DD Hierarchical BLs May require read assist Lower BL precharge 18

19 Hierarchical Word-lie Architecture Reduces amout of switched capacitace Saves power ad lowers delay [Ref s: Rabaey, Pretice 03; T. Hirose, JSSC 90] 19

20 Hierarchical Bitlies Local BLs Global BLs Divide up bit-lies hierarchically May variats possible Reduce RC delay, also decrease CV 2 power Lower BL leakage see by accessed cell 20

21 BL Leakage Durig Read Access Leakage ito o-accessed cells Raises power ad delay Affects BL differetial 1 0 Bit-lie 0 21

22 Bitlie Leakage Solutios 1 0 VGND Vg Raise V SS i cell (VGND) VSSWL VSSWL 1 0 Negative Wordlie (NWL) Hierarchical BLs Raise V SS i cell Negative WL voltage Loger access FETs Alterative bit-cells Active compesatio Lower BL precharge voltage [Ref: A. Agarwal, JSSC 03] 22

23 Lower Precharge Voltage Lower BL precharge voltage decreases power ad improves Read SNM Iteral bit-cell ode rises less Sharp limit due to accidetal cell writig if access FET pulls iteral 1 low 23

24 V DD Scalig Lower V DD (ad other voltages) via classic voltage scalig Saves power Icreases delay Limited by lost margi (read ad write) Recover Read SNM with read assist Lower BL precharge Boosted cell V DD [Ref: Bhavagarwala 04, Zhag 06] Pulsed WL ad/or Write-After-Read [Ref: Khellah 06] Lower WL [Ref: Ohbayashi 06] 24

25 Power Breakdow Durig Write Accessig cell V DD_Prech Similar to Read For Lower Power: Hierarchical WLs Address Mem Cell WL Performig write Traditioally drive BLs full swig For Lower Power : Data Charge sharig Data depedecies Low swig BLs with amplificatio 25

26 Charge recyclig to reduce write power Share charge betwee BLs or pairs of BLs Saves for cosecutive write operatios Need to assess overhead Basic charge recyclig saves 50% power i theory BL= 0V BLB= V DD BL= V DD /2 BLB= V DD /2 BL= V DD BLB= 0V old values coect floatig BLs discoect ad drive ew values [Ref s: K. Mai, JSSC 98; G. Mig, ASICON 05] 26

27 Memory Statistics 0 s more commo SPEC2000: 90% 0s i data SPEC2000: 85% 0s i istructios Assumed write value usig iverted data as ecessary [Ref: Y. Chag, ISLPED 99] New Bitcell: BL BL WL WZ 1R, 1W port W0: WZ=0, WWL=1, WS=1 W1: WZ=1, WWL=1, WS=0 WWL WS [Ref: Y. Chag, TVLSI 04] 27

28 Low-Swig Write Drive the BLs with low swig Use amplificatio i cell to restore values EQ BL V DD_Prech BLB SLC WL WL EQ SLC Q QB WE BL/BLB Q/QB V DD -V TH -delv BL VDD-VTH V WR =V DD -V TH -delv BL V WR Di WE colum decoder [Ref: K. Kada, JSSC 04] 28

29 Write Margi Fudametal limit to most power-reducig techiques Recover write margi with write assist, e.g. Boosted WL Collapsed cell VDD [Itoh 96, Bhavagarwala 04] Raised cell VSS [Yamaoka 04, Kada 04] Cell with amplificatio [Kada 04] 29

30 No-traditioal cells Key tradeoff is with fuctioal robustess Use alterative cell to improve robustess, the trade off for power savigs e.g. Remove read SNM WBL RWL WWL WBL Register file cell 1R, 1W port Read SNM elimiated Allows lower V DD 30% area overhead Robust layout RBL 8T SRAM cell [Ref: L. Chag, VLSI 05] 30

31 Cellss with Pseudo-Static SNM Removal Isolate stored data durig read Dyamic storage for duratio of read BL WL BL BL WL WWL BL WLW Differetial read WLB Sigle-eded read [Ref: S. Kosoocky, ISCICT 06] [Ref: K. Takeda, JSSC 06] 31

32 Emergig Devices: Double-gate MOSFET Emergig devices allow ew SRAM structures Back-gate biasig of thi-body MOSFET provides improved cotrol of shortchael effects, ad re-istates effective dyamic cotrol of V TH Source Gate Gate legth = Lg Fi Width = T Si Source Gate legth = Lg Gate1 Gate2 V TH Cotrol Drai Fi Height H FIN = W/2 Switchig Gate Drai Fi Height H FIN = W Double-gated (DG) MOSFET [Ref: Z. Guo, ISLPED 05] Back-gated (BG) MOSFET Idepedet frot ad back gates Oe switchig gate ad V TH cotrol gate 32

33 6T SRAM Cell with Feed-back Double-Gated (DG) NMOS pull-dow ad PMOS load devices Back-Gated (BG) NMOS access devices dyamically icrease β-ratio SNM durig read ~ 300mV Area pealty ~ 19% Vs2 (V) T DG-MOS Vs1 (V) [Ref: Z. Guo, ISLPED 05] Vs2 (V) T BG-MOS Vs1 (V) 33

34 Summary ad Perspectives Fuctioality is mai costrait i SRAM Variatio makes the outlyig cells limiters Look at hold, read, write modes Use various methods to improve robustess, the trade off for power savigs Cell voltages, thresholds Novel bit-cells Emergig devices Embedded memory major threat to cotiued techology scalig iovative solutios ecessary 34