SNM Analysis of 6T SRAM at 32NM and 45NM Technique

Transcription

1 SNM Analysis of 6T SRAM at 32NM and 45NM Technique Anurag Dandotiya ITM Universe Gwalior Amit S. Rajput Assistant Professor ITM Universe Gwalior OBJECTIVE OF THE CHAPTER In this paper we analyze the effect of SNM dependent on different parameter in read mode and write mode. We analyze SNM of different modulation like cell ratio (CR), voltage supply (Vdd), word line (WL) and bit line (BL) by spice tools using BPTM Low Power model in different technologies. We define the read margin to characterize the SRAM cells read stability. Many researchers use only 45nm technology, but we are scaling down the technologies which is more stability for the circuit. Actually stability of SRAM cell only depends on the static noise margin (SNM) and SNM is effect the stability of SRAM cell during read operation of SRAM cells. 1. BACKGROUND AND RELATED WORK SRAMs, are widely used in electronic systems [1]. SRAM cell read stability are major concerns in CMOS technologies. Actually stability of SRAM cell only depends on the static noise margin (SNM). Till now we have been using only 45nm technology, which is Welsh for stability and performance of cell. We continue to scale down the device dimension because device should be small [2] [8]. Now a days circuit designer has focused on lower supply voltage, but lower supply voltage can reduce the static noise margin and static noise margin is proportional to the performance of SRAM cell so performance of SRAM cell is also reduced. In this project we scaled down the technology and variation of different parameter such as cell ratio (CR), voltage supply (Vdd), word line (WL) and bit line (BL). It has been most beneficial of performance of cell and size will reduced as much as possible. 2. METHODOLOGY AND IMPLEMENTATION 2.1 Static Noise Margin and Derivation Static noise margin of SRAM cell depends on the cell ratio (CR) [9] supply voltage [10] and pull up ratio [11]. High value of SNM is required for the high stability of SRAM cell. Both read margin and write margin are also affected by the static noise margin of SRAM cell. In this section, Butterfly method for measuring static noise margin is introduced. It is the maximum amount of noise voltage that can be tolerated in 6T SRAM cell while still maintaining the correct In this section, Butterfly method for measuring static noise margin is introduced. It is the maximum amount of noise voltage that can be tolerated in 6T SRAM cell while still maintaining the correct. The two output curves are rotated according to X-Y coordinates which results in butterfly structure [3] The CMOS model which is use to calculate SNM I D - ) 2 I D V DS GS -V T - V DS ) In the saturated and linear regions, respectively SNM 6T = V T - ( ) { Where BL-bar Vdd BL r = ratio = WL q = M5 M3 M4 WL V T = threshold voltage C BL_bar Q_ bar Q M6 k = ({ -1} M1 M2 Vs = V DD -V T C BL V r = V s -( )V T Figure 1. 6T SRAM cell 30

2 Vdd modulation during read mode-,cr=3,bl=1,blb=1 Figure 2. Calculation of snm after rotation 2.2 Cell Ratio (Cr) In this section static noise margin is calculated by varying the cell ratio of transistors. Cell ratio is the ratio of sizes of driver transistor to the access transistor. As the cell ratio increases by increasing the size of driver transistor, Static noise margin of memory cell also increases which results in increase of current in a memory cell [4]. Cell Ratio (CR)= (W1/L1) / (W6/L6) 2.3 Pull Up Ratio (Pr) In this section, static noise margin is calculated by varying the Pull up ratio of transistors. Pull up ratio is the ratio of sizes of load transistor to the access transistor. As the Pull up ratio increases by increasing the size of driver transistor, Static noise margin of memory cell also increases which results in increase of current in a memory cell [4]. Pull up Ratio (PR) = (W4/L4) / (W5/L5) 3. RESULTS & DISSCUSSION SNM DEPENDENCES This section explores the different parameters on which the SNM is dependent. The factor are supply voltage (Vdd), cell ratio (CR), word line (WL), and bit line(bl) read and write condition. 3.1 SNM DEPENDENCES ON Vdd The 32nm and 45nm dependent of supply voltage (Vdd). We use PTM Low Power model to determine SNM of these technology on spice tools from [5]. Vdd modulation table and graph shown in below Figure 3. Output waveform of Snm at different voltage at read mode Vdd 45nm 32nm E E E E E E E E E E E E E E E E E E-01 Vdd modulation during write mode-,cr=3,bl=blb=wl=vdd Vdd 45nm 32nm E E E E E E E E E E E E E E E E-01 Figure 4. Output waveform of Snm at different voltage at write mode E E-01 31

3 3.2 SNM Dependences on Cell Ratio (CR) The cell ratio has very little impact on SNM during Sub threshold read. The CR modulation on 32nm and 45nm to finding SNM on read and write condition. These effects depend on the technology and make the general SNM modeling more complicated see [5,6]. CR 45nm 32nm E E E E E E E E E E E E-01 CR efect on SNM during read Mode- BL =1,V DD=1,WL1,CR= Figure 6. Output waveform CR efect on SNM during write Mode 3.3 SNM Dependences on Word Line (WL) We modulate word line to finding snm of these technology. WL(V) 45nm 32nm E E E E E E E E E E E E E E E E-01 Figure 5. Output waveform CR efect on SNM during read Mode CR 45nm 32nm E E-01 World line modulation during read mode- V DD=1,CR=3,BL=1,BLB= E E E E E E E E E E E E-01 Effect of CR on SNM During write Mode- BL=0,VDD=1,WL=0 BLB=1,CR=3 Figure 7. Output waveform World line modulation during read mode 32

4 WL(V) 45nm 32nm Bit Line Modulation During Read Mode- VDD=1,CR=3,WL= E E E E E E E E E E E E E E E E E E E E-01 World line modulation during write mode- V DD=1,CR=3,BL=1,BLB=0 Figure 9. output waveform bit line modulation during read mode BL(V) 45nm 32nm E E E E E E E E E E E E E E-01 Figure 8. output waveform World line modulation during write mode 3.4 SNM DEPENDENCES ON BIT LINE All of the above technique finding snm by modulation of bitline (BL) in read and write mode.table and graph shown in below: E E E E E E-01 Bit Line Modulation During write Mode- V DD=1,CR=3,WL=1 BLB=0 BL(V) 45nm 32nm E E E E E E E E E E E E E E E E E E E E-01 Figure10. output waveform bit line modulation during write mode 33

5 4. INTERPRETATIONS Read and Write Ability of 6T SRM Cell There are three types of mode of SRAM cell are read mode, write mode and hold mode. In the hold mode word line (WL) should be 0. In order to hold its data properly, the crosscoupled two inverters in the cell must sustain bi-stable operating points. From [14] the SNM is a common measure of the ability for the cell inverters to maintain their state. The SNM equals the minimum noise voltage present at each of the data storage nodes necessary to flip state of the cell. The Conventional 6T SRAM cell is more sensitive to noise during read mode. When the cell is in the read mode, the WL is connected to Vdd while the BL and BLB are precharged to Vdd. The data 0 store node rise to a certain voltage higher than the ground, according to the voltage dividing across the driver transistor and access transistor. 5. CONCLUSION In this paper, we have analyzed SNM during read state and write state modulation of cell ratio, voltage supply,word line and bitline in 22nm,32nm and 45nm. As the different technique is now a days a prime concern in the realization of the performance of a CMOS circuit. In this paper SNM of SRAM dependences various parameter in read and write mode. 6. REFRENCE [1] Chua-Chin Wang, Po-Ming Lee, and Kuo-Long Chen An SRAM Design Using Dual Threshold Voltage Transistors and Low-Power Quenchers IEEE journal of solid-state circuits, vol. 38, no. 10, october [2] Chris Hyung-il Kim, Jae-Joon Kim, Student Member, IEEE, Saibal Mukhopadhyay, Student Member, IEEE, and Kaushik Roy, Fellow, IEEEA Forward Body-Biased Low- Leakage SRAM Cache: Device, Circuit and Architecture Considerations IEEE transactions on very large scale integration (vlsi) systems, vol. 13, no. 3, march 2005 [3] Shilpi Birla, R.K.Singh, Member IACSIT, and Manisha Pattnaik, Static Noise Margin Analysis of Various SRAM Topologies, IACSIT International Journal of Engineering and Technology, Vol.3, No.3, June [4] Andrei Pavlov & Manoj Sachdev, CMOS SRAM Circuit Design and Parametric Test in Nano-Scaled Technologies. Intel Corporation, University of Waterloo, 2008 Springer Science and Business Media B.V., pp: [5] Benton H. Calhoun Anantha P. Chandrakasan Static Noise Margin Variation for Sub-threshold SRAM in 65 nm CMOS, Solid-State Circuits, IEEE Journal vol. 41, Jan.2006, Issue 7, pp [6] Koichi Takeda et al, A Read Static Noise Margin Free SRAM cell for Low Vdd and High Speed Applications, Solidvol. 41, Jan.2006, Issue 1, pp [7] Simran Kaur, Ashwani Kumar Analysis of Low Power SRAM Memory Cell using Tanner Tool IJECT Vol. 3, Issue 1, Jan. - March 2012 [8] Kevin Zhang, Member, IEEE, Uddalak Bhattacharya, Zhanping Chen, Member, IEEE, Fatih Hamzaoglu, Daniel Murray, Narendra Vallepalli, Member, IEEE, Yih Wang, Member, IEEE, B. Zheng, and Mark Bohr, Fellow, IEEE SRAM Design on 65-nm CMOS Technology With Dynamic Sleep Transistor for Leakage Reduction IEEE journal of solid-state circuits, vol. 40, no. 4, april [9] Benton H. Calhoun Anantha P. Chandrakasan, Analyzing Static Noise Margin for Sub-threshold SRAM in 65nm CMOS,ESSCIRC,2005 [10] Rajshekhar Keerthi, Henry Chen, Stability and Static Noise margin analysis of low power SRAM IEEE International Instrumentation & Measurement Technology Conference, Victoria Canada, May 2008,pp IJCA TM : 34