Optimizing Design Time

Size: px

Start display at page:

Download "Optimizing Design Time"

Ralph Flowers
5 years ago
Views:

1 Optimizing Design Time Memory Benton H. Calhoun Jan M. Rabaey

2 Role of Memory in ICs Memory is very important Focus in this chapter is embedded memory Percentage of area going to memory is increasing [Ref: V. De, Intel 2006]

$of chip static power dissipation Dominant in ultra low-power applications Substantial fraction in others Intel Penryn Intel Penryn (Picture courtesy of Intel )$

3 Processor Area Becoming Memory Dominated On-chip SRAM contains 50 90% of total transistor count Xeon: 48M/110M Itanium 2: 144M/220M SRAM SRAM is a major source of chip static power dissipation Dominant in ultra low-power applications Substantial fraction in others Intel Penryn Intel Penryn (Picture courtesy of Intel )

4 Chapter Outline Introduction to Memory Architectures Power in the Cell Array Power for Read Access Power for Write Access New Memory Technologies

5 Basic Memory Structures Row address Column address Block address Block 0 Block i Block P 1 Control circuitry Block selector Global amplifier/driver Global data bus I/O [Ref: J. Rabaey, Prentice 03]

6 SRAM Metrics Functionality Data retention Readability Writability Soft Errors Area Power Why is functionality a metric? Process variations increase with scaling Large number of cells requires analysis of tails (out to 6σ or 7σ) Within-die V TH variation due to Random Dopant Fluctuations (RDFs)

7 Where Does SRAM Power Go? Numerous analytical SRAM power models Great variety in power breakdowns Different applications cause different components of power to dominate Hence: Depends on applications: e.g., high speed versus low power, portable

8 SRAM cell BL M3 M2 M1 WL Q QB M6 M5 M4 Traditional 6-Transistor (6T) SRAM cell BL Three tasks of a cell Hold data WL = 0; BLs = X Write WL = 1; BLs driven with new data Read WL = 1; BLs precharged and left floating

9 Key SRAM cell metrics BL BL Hold WL M3 M2 M1 Q QB M6 M5 M4 Key functionality metrics Hold Static Noise Margin (SNM) Data retention voltage (DRV) Read Static Noise Margin (SNM) Write Write Margin Traditional 6-Transistor (6T) SRAM cell Metrics: Area is primary constraint Next, Power, Delay

Static Noise Margin (SNM) BL WL BLB SNM gives a measure of the cell s stability by quantifying the DC noise required to flip the cell M2 Q M3 M1 V N V N M6 M4 M5 QB Inv 1 Inv 2 QB(V) 0.

10 Static Noise Margin (SNM) BL WL BLB SNM gives a measure of the cell s stability by quantifying the DC noise required to flip the cell M2 Q M3 M1 V N V N M6 M4 M5 QB Inv 1 Inv 2 QB(V) 0.3 VTC for Inv 2 VTC 1 for Inv 1 VTC for Inv2 with V N = SNM VTC 1 for Inv1 with V N = SNM SNM 0.15 SNM is length of side of the largest embedded square on the butterfly curve Q (V) [Ref: E. Seevinck, JSSC 87]

11 Static Noise Margin with Scaling Typical cell SNM deteriorates with scaling Variations lead to failure from insufficient SNM Tech and V DD scaling lower SNM Variations worsen tail of SNM distribution (Results obtained from simulations with Predictive Technology Models [Ref: PTM; Y. Cao 00])

12 Variability: Write Margin 1 BL WL 0 1 Cell stability prior to write: BLB 0 Dominant fight (ratioed) Normalized QB Normalized Q Normalized QB Normalized QB Normalized Q Normalized Q Write failure: Positive SNM Successful write: Negative SNM

13 Variability: Cell Writability SNM (V) TT WW SS WS SW V DD = 0.6 V Write Fails Temperature ( C) Write margin limits V DD scaling for 6T cells to 600 mv, best case. 65 nm process, V DD = 0.6 V Variability and large number of cells makes this worse

14 Cell Array Power Leakage Power dominates while the memory holds data BL WL BL 0 1 Importance of Gate tunneling and GIDL depends on technology and voltages applied Sub-threshold leakage

Using Threshold Voltage to Reduce Leakage High-V TH cells necessary if all else is kept the same To keep leakage in 1 MB memory within bounds, V TH must be kept in 0.4 0.

15 Using Threshold Voltage to Reduce Leakage High-V TH cells necessary if all else is kept the same To keep leakage in 1 MB memory within bounds, V TH must be kept in V range 1 MB array retention current (A) µa 0.1 µa T L g = 0.1 μm j = 125 C 100 C W (Q T ) = 0.20 μm 75 C W (QD ) = 0.28 μm W (Q L ) = 0.18 μm 50 C 25 C high speed (0.49) low power (0.71) Average extrapolated V TH (V) at 25 C Extrapolated V TH = V TH (na /μm) V [Ref: K. Itoh, ISCAS 06]

16 Multiple Threshold Voltages BL WL BL BL WL BL 0 Dual V TH cells with low-vth access transistors provide good tradeoffs in power and delay [Ref: Hamzaoglu, et al., TVLSI 02] High V TH Use high- V TH devices to lower leakage for stored 0, which is much more common than a stored 1 Low V TH [Ref: N. Azizi, TVLSI 03]

17 Multiple Voltages Selective usage of multiple voltages in cell array e.g.,16 fa/cell at 25 C in 0.13 μm technology 1.0V WL=0V 1.0V 1.5V 0.5V High V TH to lower sub- V TH leakage Raised source, raised V DD, and lower BL reduce gate stress while maintaining SNM [Ref: K. Osada, JSSC 03]

Power Breakdown During Read Accessing correct cell Decoders, WL drivers For Lower Power: hierarchical WLs pulsed decoders Performing read Charge and discharge large

18 Power Breakdown During Read Accessing correct cell Decoders, WL drivers For Lower Power: hierarchical WLs pulsed decoders Performing read Charge and discharge large BL capacitance For Lower Power : SAs and low BL swing Hierarchical BLs Lower BL precharge V DD_Prech WL Address Mem Sense mp Data Lower V DD May require read assist

19 Hierarchical Wordline Architecture Global word line Subglobal word line Local word line Local word line Block group select Block select Memory cell Block 0 Reduces amount of switched capacitance Saves power and lowers delay Block 1 Block select [Ref s: Rabaey, Prentice 03; T. Hirose, JSSC 90] Block 2

20 Hierarchical Bitlines Local BLs Global BLs Divide up bitlines hierarchically Many variants possible Reduces RC delay, also decreases CV 2 power Lower BL leakage seen by accessed cell

21 BL Leakage During Read Access Leakage into nonaccessed cells Raises power and delay Affects BL differential 1 0 Bit-line 0

cell Negative WL voltage Longer access FETs Alternative bit-cells

22 Bitline Leakage Solutions 1 0 V SSWL 1 0 V SSWL V GND V G Raise V SS in cell (VGND) Negative Wordline (NWL) Hierarchical BLs Raise V SS in cell Negative WL voltage Longer access FETs Alternative bit-cells Active compensation Lower BL precharge voltage [Ref: A. Agarwal, JSSC 03]

23 Lower Precharge Voltage Lower BL precharge voltage decreases power and improves Read SNM Internal bit-cell node rises less Sharp limit due to accidental cell writing if access FET pulls internal 1 low

24 V DD Scaling Lower V DD (and other voltages) via classic voltage scaling Saves power Increases delay Limited by lost margin (read and write) Recover Read SNM with read assist Lower BL precharge Boosted cell V DD [Ref: Bhavnagarwala 04, Zhang 06] Pulsed WL and/or Write-after-Read [Ref: Khellah 06] Lower WL [Ref: Ohbayashi 06]

25 Power Breakdown During Write Accessing cell Similar to Read For Lower Power: Hierarchical WLs Performing write Address V DD_Prech Mem Cell WL Traditionally drive BLs full swing For Lower Power : Charge sharing Data dependencies Low swing BLs with amplification Data

Charge recycling to reduce write power Share charge between BLs or pairs of BLs Saves for consecutive write operations Need to assess overhead Basic charge recycling saves 50% power in

26 Charge recycling to reduce write power Share charge between BLs or pairs of BLs Saves for consecutive write operations Need to assess overhead Basic charge recycling saves 50% power in theory BL = 0 V BLB = V DD BL = V DD /2 BLB = V DD /2 BL = BLB = V DD 0 V old values connect floating BLs disconnect and drive new values [Ref s: K. Mai, JSSC 98; G. Ming, ASICON 05]

27 Memory Statistics 0 s more common SPEC2000: 90% 0s in data SPEC2000: 85% 0s in instructions Assumed write value using inverted data as necessary [Ref: Y. Chang, ISLPED 99] New Bitcell: BL WL BL WZ 1R, 1W port W0: WZ = 0, WWL = 1, WS = 1 W1: WZ = 1, WWL = 1, WS = 0 WWL WS [Ref: Y. Chang, TVLSI 04]

DD_Prech BLB Q QB WE BL/BLB Q/QB V DD V TH delv BL VDD VTH V

28 Low-Swing Write SLC Drive the BLs with low swing Use amplification in cell to restore values WL EQ EQ WL SLC BL V DD_Prech BLB Q QB WE BL/BLB Q/QB V DD V TH delv BL VDD VTH V WR =V DD V TH ΔV BL V WR D in WE column decoder [Ref: K. Kanda, JSSC 04]

29 Write Margin Fundamental limit to most power-reducing techniques Recover write margin with write assist, e.g., Boosted WL Collapsed cell V DD [Itoh 96, Bhavnagarwala 04] Raised cell V SS [Yamaoka 04, Kanda 04] Cell with amplification [Kanda 04]

Non-traditional cells Key tradeoff is with functional robustness Use alternative cell to improve robustness, then trade off for power savings

30 Non-traditional cells Key tradeoff is with functional robustness Use alternative cell to improve robustness, then trade off for power savings e.g. Remove read SNM WBL RWL WWL WBL Register file cell 1R, 1W port Read SNM eliminated Allows lower V DD 30% area overhead Robust layout 8T SRAM cell RBL [Ref: L. Chang, VLSI 05]

31 Cells with Pseudo-Static SNM Removal Isolate stored data during read Dynamic storage for duration of read BL WL BL BL WL WWL BL WLW Differential read [Ref: S. Kosonocky, ISCICT 06] WLB Single-ended read [Ref: K. Takeda, JSSC 06]

Emerging Devices: Double-gate MOSFET Emerging devices allow new SRAM structures Back-gate biasing of thin-body MOSFET provides improved control of short-channel effects, and re-instates effective

32 Emerging Devices: Double-gate MOSFET Emerging devices allow new SRAM structures Back-gate biasing of thin-body MOSFET provides improved control of short-channel effects, and re-instates effective dynamic control of V TH. Source Gate length = L G Gate Fin Width = T Si Drain Fin Height H FIN = W /2 Source Switching Gate Gate length = Lg Gate1 Drain Gate2 V TH Control Fin Height H FIN = W Double-gated (DG) MOSFET Back-gated (BG) MOSFET Independent front and back gates One switching gate and V TH control gate [Ref: Z. Guo, ISLPED 05]

6T SRAM Cell with Feedback Double-Gated (DG) NMOS pull-down and PMOS load devices Back-Gated (BG) NMOS access devices dynamically increase β-ratio SNM during read ~300 mv Area penalty ~ 19% PL PR 1 0

33 6T SRAM Cell with Feedback Double-Gated (DG) NMOS pull-down and PMOS load devices Back-Gated (BG) NMOS access devices dynamically increase β-ratio SNM during read ~300 mv Area penalty ~ 19% PL PR 1 0 AR AL NL NR β ratio increased V sn2 (V) mv READ STANDBY 6T DG-MOS 210 mv V sn1 (V) Vsn2 (V) [Ref: Z. Guo, ISLPED 05] T BG-MOS mv READ 0.5 STANDBY mv V sn1 (V)

34 Summary and Perspectives Functionality is main constraint in SRAM Variation makes the outlying cells limiters Look at hold, read, write modes Use various methods to improve robustness, then trade off for power savings Cell voltages, thresholdsh Novel bit-cells Emerging devices Embedded memory major threat to continued technology scaling innovative solutions necessary

35 References Books and Book Chapters K. Itoh et al., Ultra-Low Voltage Nano-scale Memories, Springer A. Macii, Memory Organization for Low-Energy Embedded Systems, in Low-Power Electronics Design, C. Piguet Ed., Chapter 26, CRC Press, V. Moshnyaga and K. Inoue, Low Power Cache Design, in Low-Power Electronics Design, C., Piguet Ed., Chapter 25, CRC Press, J. Rabaey, A. Chandrakasan and B. Nikolic, Digital Integrated Circuits, Prentice Hall, T. Takahawara and K. Itoh, Memory Leakage Reduction, in Leakage in Nanometer CMOS Technologies, S. Narendra, Ed., Chapter 7, Springer Articles A. Agarwal, H. Li and K. Roy, A Single-Vt low-leakage gated-ground cache for deep submicron, IEEE Journal of Solid-State Circuits,38(2),pp , Feb N. Azizi, F. Najm and A. Moshovos, Low-leakage asymmetric-cell SRAM, IEEE Transactions on VLSI, 11(4), pp , Aug A. Bhavnagarwala, S. Kosonocky, S. Kowalczyk, R. Joshi, Y. Chan, U. Srinivasan and J. Wadhwa, A transregional CMOS SRAM with single, logic V DD and dynamic power rails, in Symposium on VLSI Circuits, pp , Y. Cao, T. Sato, D. Sylvester, M. Orshansky and C. Hu, New paradigm of predictive MOSFET and interconnect modeling for early circuit design, in Custom Integrated Circuits Conference (CICC), Oct. 2000, pp L. Chang, D. Fried, J. Hergenrother et al., Stable SRAM cell design for the 32 nm node and beyond, Symposium on VLSI Technology, pp , June Y. Chang, B. Park and C. Kyung, Conforming inverted data store for low power memory, IEEE International Symposium on Low Power Electronics and Design, 1999.

36 References (cont.) Y. Chang, F. Lai and C. Yang, Zero-aware asymmetric SRAM cell for reducing cache power in writing zero, IEEE Transactions on VLSI Systems, 12(8), pp , Aug Z. Guo, S. Balasubramanian, R. Zlatanovici, T.-J. King, and B. Nikolic, FinFET-based SRAM design, International Symposium on Low Power Electronics and Design, pp. 2 7, Aug F. Hamzaoglu, Y. Ye, A. Keshavarzi, K. Zhang, S. Narendra, S. Borkar, M. Stan, and V. De, Analysis of Dual-V T SRAM cells with full-swing single-ended bit line sensing for on-chip cache, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 10(2), pp , Apr T. Hirose, H. Kuriyama, S. Murakam, et al., A 20-ns 4-Mb CMOS SRAM with hierarchical word decoding architecture, IEEE Journal of SolidState Circuits-, 25(5) pp , Oct K. Itoh, A. Fridi, A. Bellaouar and M. Elmasry, A Deep sub-v, single power-supply SRAM cell with multi-v T, boosted storage node and dynamic load, Symposium on VLSI Circuits, 133, June K. Itoh, M. Horiguchi and T. Kawahara, Ultra-low voltage nano-scale embedded RAMs, IEEE Symposium on Circuits and Systems, May K. Kanda, H. Sadaaki and T. Sakurai, 90% write power-saving SRAM using sense-amplifying memory cell, IEEE Journal of Solid-State Circuits, 39(6), pp , June S. Kosonocky, A. Bhavnagarwala and L. Chang, International conference on solid-state and integrated circuit technology, pp , Oct K. Mai, T. Mori, B. Amrutur et al., Low-power SRAM design using half-swing pulse-mode techniques, IEEE Journal of Solid-State Circuits, 33(11) pp , Nov G. Ming, Y. Jun and X. Jun, Low Power SRAM Design Using Charge Sharing Technique, pp , ASICON, K. Osada, Y. Saitoh, E. Ibe and K. Ishibashi, 16.7-fA/cell tunnel-leakage- suppressed 16-Mb SRAM for handling cosmic-ray-induced multierrors, IEEE Journal of Solid-State Circuits, 38(11), pp , Nov PTM Predictive Models. Available: ptm

37 References (cont.) E. Seevinck, F. List and J. Lohstroh, Static noise margin analysis of MOS SRAM Cells, IEEE Journal of Solid-State Circuits, SC-22(5), pp , Oct K. Takeda, Y. Hagihara, Y. Aimoto, M. Nomura, Y. Nakazawa, T. Ishii and H. Kobatake, A readstatic-noise-margin-free SRAM cell for low-vdd and high-speed applications, IEEE International Solid-State Circuits Conference, pp , Feb M. Yamaoka, Y. Shinozaki, N. Maeda, Y. Shimazaki, K. Kato, S. Shimada, K. Yanagisawa and K. Osadal, A 300 MHz 25 µa/mb leakage on-chip SRAM module featuring process-variation immunity and low-leakage -active mode for mobile-phone application processor, IEEE International Solid-State Circuits Conference, 2004, pp

SUB-THRESHOLD digital circuit design has emerged as

SUB-THRESHOLD digital circuit design has emerged as IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 41, NO. 7, JULY 2006 1673 Static Noise Margin Variation for Sub-threshold SRAM in 65-nm CMOS Benton H. Calhoun, Member, IEEE, and Anantha P. Chandrakasan, Fellow,