CONTROLLING STATIC POWER LEAKAGE IN 7T SRAM CELL USING POWER GATING TECHNIQUE

Transcription

1 CONTROLLING STATIC POWER LEAKAGE IN 7T SRAM CELL USING POWER GATING TECHNIQUE Mr.T.Mani 1, P.Praveen 2, P.Soundararajan 3, M.Suresh 4, D.Prakash 5 1 (Assistant professor, Department of ECE, Jay shriram group of institutions, Dharapuram road, Avinashipalayam, Tiruppur) 2 (Department of ECE, UG Student, Jay shriram group of institutions, Dharapuram road, Avinashipalayam, Tiruppur) 3 (Department of ECE, UG Student, Jay shriram group of institutions, Dharapuram road, Avinashipalayam, Tiruppur) 4 (Department of ECE, UG Student, Jay shriram group of institutions, Dharapuram road, Avinashipalayam, Tiruppur) 5 (Department of ECE, UG Student, Jay shriram group of institutions, Dharapuram road, Avinashipalayam, Tiruppur) Abstract Nowadays power leakage on-chip SRAM is a crucial part in many applications. In existing 7T SRAM cell with super cut-off word line technology static power leakage is reduced up to 26%. In proposed system static power leakage is further reduced by using power gating technique. Static power reduction using power gating technique can be providing better performance than the convectional 7T SRAM and in super cut-off word line technique. Power gating technique can of two types coarse grain and fine gain technique. In proposed system uses coarse grained technique. Header coarse grained and footer coarse grained used to reduce the static power leakage in 7T SRAM. By using header coarse grained technique is reduces more power when compared to footer coarse grain technique. Keywords Power gating technique, super cut-of word line, course grained technique, fine gain technique, header and footer course grained technique INTRODUCTION On chip cache represents a large portion of the chip and it is expected to increase in future in both portable devices and high-performance processors. To achieve higher reliability and longer battery life for portable application, power leakage SRAM is a necessity. Increased leakage current and device variability are posing major challenges to CMOS circuit designs in deeply scaled technologies. Static Random Accessed Memory (SRAM) has been and continues to be the largest component in embedded digital systems or Systems-on- Chip. It is expected to occupy over 90% of the area of System on Chip. As a result, SRAM is more vulnerable to those challenges. To effectively reduce SRAM static power leakage, power gating technique is often introduced. For low- energy applications, SRAMs operating with VDD near/below the threshold voltage (VT) are also proposed.system access performance, and hold stability, are less reliable at lower voltage, which leads to the reduction of yield. The minimum supply voltage (Vmin) is limited by the lowest acceptable yield and determines the maximum achievable power reduction. Applying an underestimated Vmin will cause intolerable failures and decrease SRAM yield. On the other hand, applying an overestimated Vmin will waste power and energy. However, finding the optimum Vmin becomes difficult in the presence of global and local variations.in this particularly explores SRAM Vmin during standby mode, i.e. data retention voltage (DRV). The goal is to develop effective methods for achieving the best leakage power reduction while the SRAM is in static mode. During write operation, only bit line or bit line bar current will charge or discharge through it, but there is no guarantee that the bit line and bit line bar will be switched. These results in wrong data being stored in the storage nodes during write operation. Proposed architecture has two access transistors. In write operation, if bit line is charging through an access transistor, then the bit line bar will discharge through the other access transistor. It ensures reliable write operation. Cell area is minimized by using smaller device dimensions for back to back connected inverters. Leakage power reduced in a SRAM cell by minimizing sub-threshold leakage current. Read delay is reduced by discharging read bit line voltage through a single transistor instead of two transistors. The paper is organised as follows CMOS Inverter SRAM cell and proposed 7T SRAM cell architecture is discussed in Section II. Section III covers simulation results which include Static Voltage Noise margin (SVNM), Write Trip Voltage (WTV), leakage power, read delay and read power, write delay and write power and area. Finally, conclusions are drawn in section CMOS INVERTER Complementary metal oxide semiconductor, abbreviated as CMOS, is a technology for constructing integrated circuits. CMOS technology is used in microprocessors, microcontrollers, static RAM, and other digital logic circuits. CMOS technology is also used for several analog circuits such as image sensors (CMOS sensor), data converters, and highly integrated transceivers for many types of communication.cmos is also sometimes referred to as complementary-symmetry metal oxide semiconductor. The words "complementary-symmetry" refer to the fact that the typical design style with CMOS uses complementary and symmetrical pairs of p-type and n-type metal oxide semiconductor field effect transistors (MOSFETs) for logic functions. Volume: 04 Issue:

2 Two important characteristics of CMOS devices are high noise immunity and low static power consumption. Since one transistor of the pair is always off, the series combination draws significant power only momentarily during switching between on and off states. Consequently, CMOS devices do not produce as much waste heat as other forms of logic, for example transistor transistor logic (TTL) or NMOS logic, which normally have some standing current even when not changing state. CMOS also allows a high density of logic functions on a chip. It was primarily for this reason that CMOS became the most used technology to be implemented in VLSI chips SRAM CELL Static random-access memory (static RAM or SRAM) is a type of semiconductor memory that uses bistable latching circuitry (flip-flop) to store each bit. SRAM exhibits data remanence, but it is still volatile in the conventional sense that data is eventually lost when the memory is not powered. The term static differentiates SRAM from DRAM (dynamic random-access memory) which must be periodically refreshed. SRAM is faster and more expensive than DRAM; it is typically used for CPU cache while DRAM is used for a computer's main memory.the power consumption of SRAM varies widely depending on how frequently it is accessed; in some instances, it can use as much power as dynamic RAM, when used at high frequencies, and some ICs can consume many watts at full bandwidth. On the other hand, static RAM used at a somewhat Slower pace, such as in applications with moderately clocked microprocessors, draws very little power and can have a nearly negligible power consumption when sitting idle in the region of a few micro-watts. Several techniques have been proposed to manage power consumption of SRAM-based memory structures. READING OPERATION In theory, reading only requires asserting the word line WL and reading the SRAM cell state by a single access transistor and bit line, e.g. M 6, BL. Nevertheless, bit lines are relatively long and have large parasitic capacitance. To speed up reading, a more complex process is used in practice: The read cycle is started by pre-charging both bit lines BL and BL, i.e., driving the bit lines to a threshold voltage (midrange voltage between logical 1 and 0) by an external module (not shown in the figures). Then asserting the word line WL enables both the access transistors M 5 and M 6, which causes the bit line BL voltage to either slightly drop (bottom NMOS transistor M 3 is ON and top PMOS transistor M 4 is off) or rise (top PMOS transistor M 4 is on). It should be noted that if BL voltage rises, the BL voltage drops, and vice versa. Then the BL and BL lines will have a small voltage difference between them. A sense amplifier will sense which line has the higher voltage and thus determine whether there was 1 or 0 stored. The higher the sensitivity of the sense amplifier, the faster the read operation. WRITING OPERATION The write cycle begins by applying the value to be written to the bit lines. If we wish to write a 0, we would apply a 0 to the bit lines, i.e. setting BL to 1 and BL to 0. This is similar to applying a reset pulse to an SR-latch, which causes the flip flop to change state. A 1 is written by inverting the values of the bit lines. WL is then asserted and the value that is to be stored is latched in. This works because the bit line inputdrivers are designed to be much stronger than the relatively weak transistors in the cell itself so they can easily override the previous state of the cross-coupled inverters. In practice, access NMOS transistors M5 and M6 have to be stronger than either bottom NMOS (M1, M3) or top PMOS (M2, M4) transistors. This is easily obtained as PMOS transistors are much weaker than NMOS when same sized. Consequently when one transistor pair (e.g. M3 and M4) is only slightly overridden by the write process, the opposite transistors pair (M1 and M2) gate voltage is also changed. This means that the M1 and M2 transistors can be easier overridden, and so on. Thus, cross-coupled inverters magnify the writing process. HOLD MODE: During hold mode, RBL voltage is at logic zero. In this mode, Leakage is the only source for power consumption. During hold mode WRSIG=0, RVDD =0. No leakage current flows through read path because current is zero between same potentials at RVDD and RBL. This minimizes sub threshold current, which is the main source of leakage current in hold mode. The bit line leakage current will flow through write path only. Sub threshold current through back to back inverters is minimized by using small device dimensions. POWER GATING TECHINQUE A.FINE-GRAIN POWER GATING Adding a sleep transistor to every cell that is to be turned off imposes a large area penalty, and individually gating the power of every cluster of cells creates timing issues introduced by inter-cluster voltage variation that are difficult to resolve. Fine-grain power gating encapsulates the Volume: 04 Issue:

3 switching transistor as a part of the standard cell logic. Switching transistors are designed by either the library IP vendor or standard cell designer. Usually these cell designs conform to the normal standard cell rules and can easily be handled by EDA tools for implementation. The size of the gate control is designed considering the worst-case scenario that will require the circuit to switch during every clock cycle, resulting in a huge area impact. Some of the recent designs implement the fine-grain power gating selectively, but only for the low Vt cells. If the technology allows multiple Vt libraries, the use of low Vt devices is minimum in the design (20%), so that the area impact can be reduced. When using power gates on the low Vt cells the output must be isolated if the next stage is a high Vt cell. Otherwise it can cause the neighbouring high Vt cell to have leakage when output goes to an unknown state due to power gating. Gate control slew rate constraint is achieved by having a buffer distribution tree for the control signals. The buffers must be chosen from a set of always on buffers (buffers without the gate control signal) designed with high Vt cells. The inherent difference between when a cell switches off with respect to another, minimizes the rush current during switch-on and switch-off. Usually the gating transistor is designed as a high Vt device. Coarse-grain power gating offers further flexibility by optimizing the power gating cells where there is low switching activity. Leakage optimization has to be done at the coarse grain level, swapping the low leakage cell for the high leakage one. Fine-grain power gating is an elegant methodology resulting in up to 10 times leakage reduction. This type of power reduction makes it an appealing technique if the power reduction requirement is not satisfied by multiple Vt optimization alone. B. COARSE-GRAIN POWER GATING The coarse-grained approach implements the grid style sleep transistors which drives cells locally through shared virtual power networks. This approach is less sensitive to PVT variation, introduces less IR-drop variation, and imposes a smaller area overhead than the cell- or cluster-based implementations. In coarse-grain power gating, the powergating transistor is a part of the power distribution network rather than the standard cell. There are two ways of implementing a coarse-grain structure Ring-based: The power gates are placed around the perimeter of the module that is being switched off as a ring. Special corner cells are used to turn the power signals around the corners. Column-based: The power gates are inserted within the module with the cells abutted to each other in the form of columns. The global power is the higher layers of metal, while the switched power is in the lower layers. Gate sizing depends on the overall switching current of the module at any given time. Since only a fraction of circuits switch at any point of time, power gate sizes are smaller as compared to the fine-grain switches. Dynamic power simulation using worst-case vectors can determine the worstcase switching for the module and hence the size. The IR drop can also be factored into the analysis. Simultaneous switching capacitance is a major consideration in coarsegrain power gating implementation. In order to limit simultaneous switching, gate control buffers can be daisy chained, and special counters can be used to selectively turn on blocks of switches. 1) FOOTER SWITCHING TECHNIQUE Power gating technique is used to save the leakage power when the system is not in operation. This is accomplished by adding a switch either to VDD or VSS supply. When the design is power gated it literally means the block is powered OFF. Powering OFF a design block is the most beneficial technique of all the low power techniques because you dissipate near zero power. Near zero because the switching circuit used for implementing power gating still dissipate leakage power even in power gating mode. The control to the power gating switching circuit is generated by the Power gating control block. If VSS is gated we call it as footer switch. 2) HEADER SWITCHING TECHNIQUE Power gating technique is used to save the leakage power when the system is not in operation. This is accomplished by adding a switch either to VDD or VSS supply. When the design is power gated it literally means the block is powered OFF. Powering OFF a design block is the most beneficial technique of all the low power techniques because you dissipate near zero power. Near zero because the switching circuit used for implementing power gating still dissipate leakage power even in power gating mode. The control to the power gating switching circuit is generated by the Power gating control block. When VDD is gated the power switch is called the header switch. PROPOSED SYSTEM Power gating is the main power reduction techniques for the static power. As long as technology scaling is taking place, static power becomes paramount important factor to the VLSI designs. Proposed =system is to reduce the static power leakage in the 7T SRAM. The power gating technique can be used to reduce the static power leakage in the SRAM. Basically power gating technique is of two types Course grained technique and Fine grained technique. In our project we uses course grained technique to reduce Volume: 04 Issue:

4 the power leakage. Both Header course grained technique and Footer course grained technique. HEADER COURSE GRAINED TECHNIQUE Header Coarse grained Recovery Boosting technique is implemented in caches to achieve less power. Cache dead time can increases cache missing significantly. SRAM cells (which are traditionally implemented using six-transistor cells) can limit SRAM stability concerns due to gate oxide breakdown. Eight-transistor (8T) cells were proposed to enhance gate oxide stability under voltage scaling. 8T cells, however, suffer from costly write operations caused by the column selection issue. Previous work has proposed Read- Modify Write (RMW) to address this issue at the expense of an increase in cache access frequency. In this work, we introduce voltage feeding inverter solutions (modified SRAM circuit) to address this inefficiency. Our solutions rely on overcome cache missing by reducing gate oxide breakdown voltage that avoids SRAM dead time made to overcome cache failure. FOOTER COURSE GRAINED TECHNIQUE The coarse-grained power gating drives cells locally through shared virtual power networks. Each virtual power network is gated by one P-MOS or N-MOS switch or switches. Coarse-grained power gating architecture imposes a smaller area overhead than the _ne-grained one which implements power gating in each cell. But when the powergating sleep transistor drives many standard cells, sleep transistor is a part of the power distribution. The size of power gating sleep transistor depends on the overall switching current of the module at any given time. Since only a fraction of circuits switch at any point of time, power gate sizes are smaller compared to the _negrained switches. Dynamic power simulation using worst case vectors can determine the worst case switching for the module and hence the size. The IR drop can also be factored into the analysis. Simultaneous switching capacitance is a major consideration in coarse-grained power gating implementation. In order to limit simultaneous switching, gate control can be daisy chained, and special counters can be used to selectively turn on blocks of switches. Footer technique can be used to reduce the power leakage in the SRAM circuit Header course technique can be used reduce the static power leakage in the SRAM. And the header switching can reduce the power than the footer switching, the simulation header switching is below Simulation of the power leakage using footer course grained technique can be simulated using tanner s-edit in 65nm.this may use to illustrate the power reduction in 7T SRAM cell. The simulation result of footer course grain technique can be below POWER GATING: Power gating is a technique used in integrated circuit design to reduce power consumption, by shutting off the current to blocks of the circuit that are not in use. In addition to reducing stand-by or leakage power, power gating has the benefit of enabling vdd testing. Power gating technique means applying sleep transistor both the header and footer Volume: 04 Issue:

5 Simulation of the power gating technique can be simulated using tanner s-edit in 65nm.this may use to illustrate the power reduction in 7T SRAM cell. The simulation result of footer course grain technique can be below REFERENCES [1] J. Rabaey, A. Chandrakasan, and B. Nikolic, Digital intergrated circuits: A Design Perspective, 2nd ed. Prentice Hall, [2] L. Villa, M. Zhang, and K. Asanovic, "Dynamic zero compression for cache energy reduction," in Proc. 33rd Int. Symp. Microarchitecture Mzcro-33, 2000, pp [3] M. Yoshimoto et al., "A 64kb CMOS RAM with divided word line structure, in IEEE Int. Solid State Circuits Conj Tech. Digest, 1983, pp [4] K. W. Mai et al., "Low-Power SRAM design using halfswing pulse-mode techniques," IEEE J Solid State Circuits, vol. 33, pp , Nov [5] S. Hattori, and T. Sakurai, "90% Write power saving SRAM using sense-amplifying memory cell," IEEE J Solid State Circuits, vol. 39, pp , June [6] A. Karandikar, and K. K. Parhi, "Low power SRAM design using hierarchical divided bit-line approach," in Int. Conference Computer. Design, 1998, pp [7] N. Azizi et al., "Low-leakage Asymmetric-Cell SRAM," IEEE. Trans. Very Large Integrated Scale (VLSI) Syst., vol. 11, pp , [8] J. Hennessy, and D. Patterson, Computer Architecture: A Quantitative Approach, 3rd ed. Morgan Kaufmann, [9] Seevinck et al., "Static-Noise Margin Analysis of MOS SRAM Cells," IEEE J Solid-State Circuits, vol. 22, pp , [10] K. Zhang et al., "A SRAM design on 65nm CMOS technologywith integrated leakage reduction scheme," VLSI Circuits Sym. Tech. Digest, p294, Jun Power gate size: The power gate size must be selected to handle the amount of switching current at any given time. The gate must be bigger such that there is no measurable voltage (IR) drop due to the gate. As a rule of thumb, the gate size is selected to be around 3 times the switching capacitance. Designers can also choose between header (P- MOS) and footer (N-MOS) gate. Usually footer gates tend to be smaller in area for the same switching current. Dynamic power analysis tools can accurately measure the switching current and also predict the size for the power gate POWER GATING MERITS: Power gating technique power consumption is less than the super cut off word line technique. Among three power gating technique header course grained technique. Power leakage can be further reduced in the SRAM circuit. CONCLUSION Proposed 7T SRAM cell plays an important role where stability, leakage power and area cannot be compromised while designing memory circuits. 7T SRAM cell architecture in this paper has separate read and write paths. Proposed7T SRAM cell has lowest leakage power consumption in power gating technique compare to super cut off wave line technique. Proposed SRAM cell occupies less power compared to 6T, 8T and 9T SRAM cells. Compared to conventional 7T SRAM cell, the proposed 7T SRAM cell has reduced power,. The overall performance of proposed 7T is best among the SRAM cells. Volume: 04 Issue: