RF Circuit Designs for Reliability and Process Variability Resilience

Transcription

1 Uiversity of Cetral Florida Electroic heses ad Dissertatios Doctoral Dissertatio (Ope Access) RF Circuit Desigs for Reliability ad Process ariability Resiliece 06 Ekavut Kritchachai Uiversity of Cetral Florida Fid similar works at: Uiversity of Cetral Florida Libraries Part of the Electrical ad Electroics Commos SARS Citatio Kritchachai, Ekavut, "RF Circuit Desigs for Reliability ad Process ariability Resiliece" (06). Electroic heses ad Dissertatios. Paper 490. his Doctoral Dissertatio (Ope Access) is brought to you for free ad ope access by SARS. It has bee accepted for iclusio i Electroic heses ad Dissertatios by a authorized admiistrator of SARS. For more iformatio, please cotact lee.dotso@ucf.edu.

2 RF CIRCUI DESIGNS FOR RELIABILIY AND PROCESS ARIABILIY RESILIENCE by EKAU KRICHANCHAI B.S. Kasetsart Uiversity, 007 M.S. Uiversity of Cetral Florida, 00 A dissertatio submitted i partial fulfillmet of the requiremets for the degree of Doctor of Philosophy i the Departmet of Electrical ad Computer Egieerig i the College of Egieerig ad Computer Sciece at the Uiversity of Cetral Florida Orlado, Florida Sprig erm 06 Major Professor: Jia S. Yua

3 06 Ekavut Kritchachai ii

4 ABSRAC CMOS devices are scaled dow ad beyod pose sigificat process variability ad reliability issues. Negative biased temperature istability (NBI) ad hot carrier ijectio (HCI) are well-kow agig pheomea that degrade trasistor ad circuit performace. Yield aalysis ad optimizatio, which takes ito accout the maufacturig toleraces, model ucertaities, variatios i the process parameters, ad agig factors are kow as idispesable compoets of the circuit desig procedure. Process variability issues become more predomiat as the feature size decreases. With these isights provided, reliability ad variability evaluatios o typical RF circuits ad possible compesatio techiques are highly desirable. I this work, a class F power amplifier was desiged ad evaluated usig SMC 0.8 µm RF techology. he PA s output power ad power-added efficiecy were evaluated usig the ADS simulatio. Physical isight of trasistor operatio i the RF circuit eviromet was examied usig the Setaurus mixed-mode device ad circuit simulatio. he hot electro effect ad device self-heatig degraded the output power ad power-added efficiecy of the power amplifier, especially whe both the iput trasistor ad output trasistor suffered high impact ioizatio rates ad lattice heatig. RF power amplifier adaptive body bias compesatio techique was used for output power ad power-added efficiecy resiliet to process, supply voltage, ad temperature variatios. he adaptive body biasig scheme used a curret source for P sesig to provide resiliece through the threshold voltage adjustmet to maitai power amplifier performace over a wide rage of variability. he resiliet iii

5 body biasig desig improved the robustess of the power amplifier i output power ad power-added efficiecy over process, supply voltage, ad temperature variatios. Process variatio ad agig effect were studied o a RF mixer. he mixer compesatio usig a process ivariat curret source was evaluated. Mixer parameters such as coversio gai, oise figure, ad output power before ad after compesatio over a wide rage of variability were examied. Aalytical equatios were derived for physical isight. ADS ad Mote-Carlo simulatio results showed that the use of ivariat curret source improved the robustess of the mixer performace agaist process variatios ad device agig. Fially, Semicoductor process variatio ad reliability agig effect o CMOS CO performace was studied. A techique to mitigate the effect of process variatios o the performaces of ao-scale CMOS LC-CO was preseted. he LC-CO compesatio used a process ivariat curret source. CO parameters such as phase oise ad core power before ad after compesatio over a wide rage of variability were examied. ADS ad Mote-Carlo simulatio results showed that the use of ivariat curret source improved the robustess of the CO performace agaist process variatios ad device agig. iv

6 o my family. v

7 ACKNOWLEDGMENS First, I would like to express my special thaks to my advisor, Professor Jia S. Yua, for his warm, strog support, cosideratio, ad ecouragemet throughout my graduate studies. His passio ad dedicatio to research has soud effects o me ad will guide me i my future life. His cosideratio ad support has wo my greatest respect ad sicere friedship. He cotributed cotiuous guidace ad suggestios i this work. At the meatime, I have bee provided with the essetial lab resources ad software tools to coduct the research work. His techical ad editorial experieces were very critical to the completio of this dissertatio too. My thaks also go to my other four dissertatio committee members: Dr. Kalpathy B. Sudaram, Dr. Lei Wei, ad Dr. Lee Chow ad Dr. Migjie Li for attedig my proposal ad dissertatio defese, readig previous drafts of this dissertatio ad providig valuable commets that improved the presetatio ad cotets of this dissertatio. I am grateful to all my colleagues: Shuyu Che, Yiheg Wag, Yuyig Zhag, Chegcheg Xiao, Yu Bi, Ursila Kha, Georgie Brusseskiy. I particular, Shuyu Che helped me with PA circuit desig ad ADS Mote Carlo simulatio. Yiheg gave me lots of suggestios o the RF PA desig; especially o load pull ad source pull simulatios. I have collaborated with Yu Bi, Ursila Kha ad Georgie Brusseskiy i may other issues, they gave me precious ispiratios. Last, but ot least, I would like to thak my family, especially my girlfried Sopacha Phipitkuthor, for their uderstadig ad support durig the past few years. It was their love ad support that made this dissertatio possible. My parets humrog ad Sriwa Kritchachai have my deepest gratitude ad love for their dedicatio ad may years of support durig my studies. vi

8 ABLE OF CONENS LIS OF FIGURES... ix LIS OF ACRONYMS AND ABBREIAIONS... xii CHAPER ONE: INRODUCION.... Motivatio.... Goal of research.... Results outlie... CHAPER WO: RF CIRCUIS AND RELIABILIY ISSUES OERIEW.... Oxide Breakdow.... Hot Carrier Effect ariability Issues... 8 CHAPER HREE: EALUAION OF ELECRICAL SRESS EFFEC ON CLASS F PA.... RF Power Amplifiers Fudametals.... Class E PA Reliability Issues.... Desig of Class F PA Mixed Mode Simulatio RF Stress Simulatio....6 Summary... 8 CHAPER FOUR: POWER AMPLIFIER RESILIEN DESIGN FOR PROCESS, OLAGE AND EMPERAURE ARIAIONS Curret Source Desig uig for ariability Compesated Results Summary... 4 CHAPER FIE: PROCESS ARIAION SUDY ON RF MIXER Process ariatios Mixer Circuit Desig Ivariat Curret Source Simulatio Results Mote Carlo Simulatio Summary... 8 vii

9 CHAPER SIX: PROCESS ARIAION SUDY ON CMOS OLAGE CONROL OSCILLAOR Process ariability Details Related Work Oscillator Circuit Desig Ivariat Curret Source Simulatio Results Mote Carlo Simulatio Summary CHAPER SEEN:CONCLUSIONS Accomplishmets LIS OF REFERENCES viii

10 LIS OF FIGURES Figure raps i the gate oxide whe soft hard ad hard breakdow happe... 5 Figure EMMI image of the gate after breakdow Figure Mechaisms of Hot Carrier Effects... 8 Figure 4 ariability issue iside ad amog dies Figure 5 Geeral power amplifier model... Figure 6 Curret ad voltage waveforms of class A, AB, B ad C power amplifiers.... Figure 7 Curret ad voltage waveforms of class D, E ad F power amplifiers.... Figure 8 Schematic of class F power amplifier Figure 9 Layout view of the class F power amplifier Figure 0 (a) Output curret versus time (b) Output voltage versus time Figure (a) Output power ad power gai versus iput power. (b) Power-added efficiecy versus iput power Figure Drai-source ad gate-source voltage of the iput trasistor M.... Figure Drai-source ad gate-source voltage of the output trasistor M.... Figure 4 Impact ioizatio rates of the iput stage (left plot) ad output stage (right plot) trasistors.... Figure 5 Lattice temperature of the iput stage (left plot) ad output stage (right plot) trasistors.... Figure 6 Normalized output power versus (a) threshold voltage ad (b) mobility shift... 5 Figure 7 Normalized power-added efficiecy versus (a) threshold voltage ad (b) mobility shift ix

11 Figure 8 Normalized (a) output power ad (b) power-added efficiecy versus temperature rise Figure 9 Curret-source circuit schematic Figure 0 A class AB PA with adaptive body biasig... Figure (a) Output power versus threshold voltage shift. (b)output power versus mobility variatio... 5 Figure Output power versus process corer models Figure Output power versus temperature Figure 4 Output power versus supply voltage Figure 5 Power-added efficiecy as a fuctio of threshold voltage... 8 Figure 6 Power-added efficiecy as a fuctio of mobility Figure 7 Power-added efficiecy vs process corer models Figure 8 Power-added efficiecy versus temperature Figure 9 Power-added efficiecy versus supply voltage Figure 0 he mixig process... 7 Figure Schematic of a double-balace Gilbert RF mixer... 7 Figure Process isesitive curret source Figure (a) Coversio gai predicted by differet process models. (b) Coversio gai versus threshold voltage. (c) Coversio gai versus electro mobility Figure 4(a) Noise figure predicted usig differet process models. (b) Noise figure versus threshold voltage. (c) Noise figure versus electro mobility Figure 5(a) Predicted mixer out power usig differet process models. (b) Output power versus threshold voltage. (c) Output versus electro mobility Figure 6 (a) Coversio gai statistical distributio without compesatio (b) Coversio gai x

12 statistical distributio after process compesatio effect Figure 7 (a) Noise figure statistical distributio without curret compesatio (b) Noise figure statistical distributio after process compesatio effect... 8 Figure 8 (a) Output power statistical distributio without curret compesatio (b) Output power statistical distributio after process compesatio effect... 8 Figure 9 Schematic of a LC-CO Figure 40 Process isesitive curret source Figure 4 he output spectrum Figure 4 (a) Phase oise by differet process models (b) Phase oise versus threshold voltage (c) Phase oise versus electro mobility... 9 Figure 4 (a) Power cosumptio predicted usig differet process models (b) Power cosumptio versus threshold voltage (c) Power cosumptio versus electro mobility... 9 Figure 44 (a) Phase oise statistical distributio without compesatio (b) Phase oise statistical distributio after process compesatio effect... 9 xi

13 LIS OF ACRONYMS AND ABBREIAIONS ADS ASIC BD BI CDMA CHE CMOS DC FE HC HCI HCD HF IC KCL KL LNA MC MOS Advaced Desig System Applicatio Specific Itegrated Circuits Breakdow Bias emperature Istability Code Divisio Multiple Access Chael Hot Electro Complemetary Metal Oxide Semicoductor Direct Curret Field Effect rasistor Hot Carrier Hot Carrier Ijectio Hot Carrier Degradatio High Frequecy Itegrated Circuit Kirchhoff s Curret Law Kirchhoff s oltage Law Low Noise Amplifier Mote Carlo Metal Oxide Semicoductor xii

14 MOSFE NBI NF NMOSFE OPAMP PA PAE PBI PMOSFE RF RFIC SBD SH SNR SOC SOI SD DDB MOS Field Effect rasistor Negative Bias emperature Istability Noise Figure or Noise Factor N-type MOS Field Effect rasistor Operatio Amplifier Power Amplifier Power Added Efficiecy Positive Bias emperature Istability P-type MOS Field Effect rasistor Radio Frequecy Radio Frequecy Itegrated Circuit Soft Breakdow Self-Heatig Sigal-to-Noise Ratio System o Chip Silico-o- Isulator Stadard Deviatio ime Depedet Dielectric Breakdow µ Mobility of N-ype MOS Field Effect rasistor LSI DD ery-large-scale Itegratio DC Supply oltage hreshold oltage xiii

15 CHAPER ONE: INRODUCION. Motivatio Advaces i process techologies ad circuit desig techiques, alog with sophisticated RF desig kits, have made CMOS techology the platform of choice for wireless desigs. With the rapid growth of IC idustry, CMOS RFICs are widely used i wireless commuicatio systems, like mobile phoe ad, Bluetooth, WLAN, wireless sesig system, etc. Usig RF CMOS to fabricate highly itegrated sigle-chip solutios eables products that are smaller, more affordable, more power efficiet ad have a loger rage tha previously possible. Due to aggressive scalig i device dimesios for improvig speed ad fuctioality, CMOS trasistors i the deep sub-micrometer to aometer regime has resulted i major reliability issues icludig gate oxide breakdow ad chael hot electro degradatio, NBI, ad variability. Most of RF circuits are vulerable to the reliability issues. hey suffer from differet reliability problems sice they have differet operatio schemes ad differet structures. It is very urget to study why they are suffer from the reliability ad variability issues. Nowadays, there have ot bee ay uiversal rules developed o the relatioship betwee RF circuits ad susceptible reliability issues yet. Each RF circuits should be studied idividually accordig to its uique features. Power amplifier, mixers ad oscillator are essetial parts i RF trasceivers. Power amplifier is the last oe before atea i a trasmitter ad serves to amplifier the power to be trasmitted. Mixers are used to yield both, a sum ad a differece frequecy at a sigle output port whe two distict iput frequecies are iserted ito the other two ports. Oscillators are used to provide sigal

16 sources for frequecy coversio ad carrier geeratio. It is of great sigificace to keep them workig stably over variatios of temperature, process, voltage supply, ad other stress ad degradatio coditios.. Goal of research his work is maily focused o solvig issues listed below:. Priciple ad theoretical study of typical reliability issues ad verificatio by device ad circuit level simulatios.. Circuit desig ad chip implemetatio of RF PA, mixer, oscillator circuits.. Reliability aalysis based o experimetal results o class F PA. 4. Propose ad compare possible compesatio circuits, such as adaptive body biasig circuits, a process ivariat curret source, etc. 5. Mote-Carlo simulatio to demostrate variability issues ad compesatio effects of adaptive body biasig circuit.. Results outlie o summarize, chapter two gives a overview of curret reliability ad variability issues remaied i RF circuits desig. he author evaluated hot electro ad oxide stress effects o Class F PA by experimets, details are show i chapter three. Adaptive body biasig techique to miimize P variatios of RF class AB power amplifier is evaluated, verified with aalytical equatios, this is described i chapter four. Chapter five examied Process variatios ad reliability o mixer usig a process ivariat curret source, ad supported by aalytical equatios. A robust, adaptive desig techique to reduce P variatio effects o RF oscillator circuits is developed i chapter six. Chapter seve is the fial coclusio ad future work.

17 CHAPER WO: RF CIRCUIS AND RELIABILIY ISSUES OERIEW. Oxide Breakdow Oxide Breakdow [] is defied as the destructio of the oxide layer (usually silico dioxide or SiO) i a semicoductor device. Oxide layers are used i may parts of the semicoductor device: such as the dielectric layer i capacitors; the gate oxide betwee the metal ad the semicoductor i MOS trasistors; the iter-layer dielectric to isolate coductors from each other, etc. Oxide breakdow is also cosidered as oxide rupture or oxide puch-through. I the moder world with the dimesios reductios of the trasistor, oe of the reliability issues called Oxide breakdow has bee cocered by the idustry. While the other features of the device are scaled dow, the oxide thickess must be reduced. Oxides become more vulerable to the gate to source ad drai to source voltages whe they get thier. Right ow the thiest oxide layers i the world are already less tha 0 agstroms thick. A oxide layer ca break dow easily at oce at 8- M per cm of thickess. here are several classificatios of the oxide breakdow base o differet kids of defiitio. he first type is Early-life dielectric breakdow. Early-life dielectric breakdow refers to the breakdow happes i the early device life, such as withi the first - years of the ormal operatio. Early life dielectric breakdow is maily because of the presece of weak spots withi the dielectric layer arisig from its poor processig or ueve growth. hese weak spots or dielectric defects could be caused by: ) radiatio damage; ) cotamiatio, wherei particles or impurities are trapped o the silico prior to oxidatio; ) the presece of mobile sodium (Na) ios i the oxide; ad 4) crystallie defects

18 he secod type is ime-depedet dielectric breakdow (DDB). ime-depedet dielectric breakdow refers to the breakdow happes after a loger use of time, such as 6-0 years, usually cosiders as the wear-out stage. However the mechaism is the same as the early-life breakdow. he last type is EOS/ESD-iduced dielectric breakdow. he third classificatio is selfexplaatory, which is merely to gate oxide destructio due to the applicatio of excessive voltage or curret to the device. Gate oxide breakdow could also divide ito soft breakdow ad hard breakdow. Whe breakdow just happes, it could be cosidered as the soft breakdow, ad whe breakdow happes i a log time it could be cosidered as hard breakdow. Usually soft breakdow does ot degrade the device performace a lot, but hard breakdow could usually damage the device. As Figure shows, i (a) first the traps start to form i the gate oxide, but they do ot overlap ad coduct; i (b) as more ad more traps are created, the the traps start to overlap ad coductio path is created, as soo as the coductio path is created, the soft breakdow happes. After soft breakdow happes, i (c), the traps are overlappig, at this time thermal damage was happe. Because coductio leads to heat, ad heat leads to thermal damage. Ad fially i (d), hard breakdow happes, because the silico i the breakdow spots melts ad oxyge is released. 4

19 Figure raps i the gate oxide whe soft hard ad hard breakdow happe Figure is a picture of after-breakdow from Emissio Microscopy (EMMI). [] Light regios are the areas of gate oxide breakdow where the Silico has melted. After a hard breakdow, usually silico i the breakdow spots melts, oxyge is released, ad silico filamet is formed from gate to substrate. ypically, ot oly the gate oxide is ruptured after hard breakdow, but also the Si substrate chael is severely damaged by gate oxide BD-iduced thermal effect. I some cases, a direct short i the chael betwee source ad drai is observed from EM i HBD MOSFEs. 5

20 Figure EMMI image of the gate after breakdow.. Hot Carrier Effect Hot carrier effect is oe of the most sigificat reliability problems of advaced MOSFEs devices. Hot carrier refers to either holes or electros that have gaied very high kietic eergy after beig accelerated by a strog electric field i areas of high field itesities withi a semicoductor device. Hot carrier usually ijects ito the gate oxide or substrate layers because of the high electrical field. A path of traps ad charges will be created which will degrade the semicoductor device performace. Hot carries effects refers to device degradatio or istability caused by hot carrier ijectio. here are four types of hot electro ijectio mechaisms. he first type is the chael hot electro ijectio. Chael hot electro ijectio happes whe both the gate voltage ad drai voltage are higher tha the source voltage, with D G. Due to the high gate voltage, chael carriers sometimes are drive to the gate oxide before they reach the drai side. he secod type is the substrate hot electro ijectio. Substrate hot electro ijectio usually happes whe the substrate bias is very high such as, B >>0. Substrate field drives the carriers to the Si-SiO iterface uder this coditio. I the process the carriers gai a lot of kietic eergy from the high electrical field so that they could go ito the surface depletio regio. I the ed, they overcome the surface eergy barrier ad iject ito the gate oxide. he third type is the drai avalache hot carrier ijectio. 6

21 he drai avalache hot carrier (DAHC) ijectio is show i Fig.. his is the worst device degradatio uder ormal operatig temperature. his happes whe a high voltage applied at the drai at the coditio of (D > G ) the chael carriers will accelerate ito the drai s depletio regio. he results show that the worst effects happe whe D = G. his acceleratio of chael carriers creates dislodged electro-hole pairs. he pheomeo is kow as impact ioizatio, some electro-hole pairs gai eough eergy to overcome the electric potetial barrier betwee the gate oxide ad the silico substrate. he some of the electro ad carriers iject ito the gate oxide layer as well as the substrate layer where they are sometimes trapped. Hot carriers ca be trapped at the Si-SiO iterface or withi the oxide itself, creatig a space charge which will icrease over time as more charges are trapped. hese trapped charges chage some of the device characteristics, for example the threshold voltage ( th ) ad mobility. Ijected carriers will ot become gate curret i the gate oxide. Meawhile, most of the holes from the electro-hole pairs geerated by impact ioizatio flow back to the substrate, comprisig a large portio of the substrate s curret. he forth type is the secodary geerated hot electro ijectio. Secodary geerated hot electro ijectio ivolves the geeratio of hot carriers from impact ioizatio ivolvig a secodary carrier which was created by a earlier icidet of impact ioizatio. his happes whe a high voltage applied at the drai side or D > G. he back bias results i a field which teds to drive the hot carriers geerated by the secodary carries to the surface regio ad get eough kietic eergy to overcome the surface eergy barrier. 7

22 Figure Mechaisms of Hot Carrier Effects. ariability Issues As the characteristic dimesios of device becomes smaller ad smaller, it becomes harder ad harder to precisely cotrol the physical dimesios ad dopat levels durig the fabricatio process. As a result, these growig ucertaities lead to more ad more statistic variatios i circuit performace ad behaviors from desiged circuit. raditioally, desigers ted to thik i a determiistic way, while with these variability issues become too big to igore, desigers got more problem to solve. As show i Figure 4, iitially, process variatio has bee treated maily as die to die variatio, that is the differece origiated from differet die eviromets, but devices from the same die share the same properties. With the device size shriks, itra-die variatios have become the mai cocer for desig sice it will cause local 8

23 mismatch eve if chips are cut from the same die. Figure 4 ariability issue iside ad amog dies. he major sources of process variability iclude radom dopat fluctuatios (RDF), lie-edge ad lie-width roughess (LER ad LWR) ad oxide thickess ad iterface roughess etc []. Radom dopat fluctuatios results from the radom fluctuatios i the umber ad locatio of the dopat atoms i the chael of a trasistor ad is a major source of process variability i advaced CMOS techology. As the umber of dopat atoms i the chael decreases with scaled dimesios, the impact of the variatio associated with the atoms icreases. he major effect of radom dopat fluctuatios is itroducig threshold voltage shift ad mismatch. he impact of process variability due to dopat variatio o threshold voltage mismatch derived from the overall umber variatio of the total depletio charge is give by [4] : 4 δ = ( 4q ε si Ø B ) ( ) ( ox W eff L eff 9 4 N CH ε ox ) ( ) where q is the electro charge, εsi, εox are the permittivity of the silico ad SiO, ØB is the built-i potetial of S/D-to-chael PN juctio of MOFEs, NCH is the chael dopig cocetratio, Leff is the effective chael legth ad Weff is the effective chael width. he threshold voltage variatio is iversely proportioal to the square root of the active device area. As a result of scalig dow techology, dopat variatio is sigificatly icreased i the process variability for scaled CMOS techology beyod 90-m regime. As a example, it is estimated that the radom dopat fluctuatio

24 cotributes over 60% to the threshold voltage mismatch i sub-90-m MOSFEs [5]. he secod major source of process variability is lie-edge ad lie-width roughess that causes the critical dimesio variatio ad is due to the toleraces iheret to materials ad tools used i the lithography process. he edge roughess remais typically o the order of 5m almost idepedet of the type of lithography used i productio [6]. Lie-edge ad lie-width roughess does ot scale accordigly as the techology scalig, becomig a icreasigly larger fractio of the gate legth. LER ad LWR will result i the icreases i the subthreshold curret [7] ad the degradatio i the threshold voltage () characteristics [8]. he variatio effect due to LER ad RDF are statistically idepedet ad ca be modeled idepedetly [9]. he scalig of the MOSFEs to deep submicrometer ivolves aggressive reductio i the gate oxide thickess. Whe the oxide thickess is equivalet to oly a few silico atomic layers, the atomic scale iterface roughess steps betwee Si-SiO ad SiO-polysilico gate will result i sigificat oxide thickess variatio (O) withi the gate regio. Aseov et al. [0] show that itrisic threshold voltage fluctuatios iduced by local oxide thickess variatios become comparable to voltage fluctuatios itroduced by RDF for covetioal MOS devices with dimesios of 0m ad below. A H fluctuatio of about 0 m is produced due to gate oxide thickess fluctuatio by iterface roughess for a MOSFE with L=W=0m. 0

25 CHAPER HREE: EALUAION OF ELECRICAL SRESS EFFEC ON CLASS F PA. RF Power Amplifiers Fudametals Power amplifiers ca be categorized ito differet types (A, AB, B, C, D, E, F) distiguished primarily by bias coditios ad coductio agle. For the four classic classes A. AB, B ad C, the iput sigal overdrive is relatively small ad the device is operated more as a curret source. Class A, AB, B, ad C may be studied with a sigle model as i Figure 5. Figure 5 Geeral power amplifier model I this geeral model, the resistor RL represets the load. he RF choke feeds DC power to the drai. he RF choke is assumed large eough so that the curret through it is substatially costat. he matchig etwork formed with LC tak is used to optimize gai. he drai voltage of the output trasistor swigs betwee groud ad DD depedig o the iput power level. he curret ad voltage waveforms of class A, AB, B ad C power amplifiers are show i Fig..5. Class A power amplifier is operated i full iput ad output rage which provides good liearity at the cost of low efficiecy. For class AB, B ad C, the gate bias voltage is decreased 0 to reduce the coductio agle for higher efficiecy as illustrated i Figure 6. he maximum efficiecy for class A is 50%. With a smaller coductio agle, the power efficiecy of class AB ca reach up to 78.5%. For class C, as the coductio agle shriks to zero, the efficiecy ca reach 00%

26 Figure 6 Curret ad voltage waveforms of class A, AB, B ad C power amplifiers. For class D, E ad F power amplifiers, the trasistor is used as a switch. he curret ad voltage waveforms for class D, E ad F power amplifiers are show i Figure 7. Sice there is either zero voltage across it or zero curret across it, the trasistor dissipates o power ad the theoretical efficiecy is 00%. Figure 7 Curret ad voltage waveforms of class D, E ad F power amplifiers.

27 . Class E PA Reliability Issues he advace i CMOS techology for high frequecy applicatios has made it a atural choice for itegrated, low cost RF power amplifiers (PAs) for wireless commuicatios ICs. Depedig o its applicatios, the power trasistor ca be used as a curret source (class A, B, ad C mode) or a switch (class D, E, ad F mode). Switchig-type amplifiers achieve high power efficiecy [] ad are desirable for portable commuicatio systems such as cell phoes, global positio systems, ad wireless local area etworks. he tradeoff betwee liearity ad efficiecy i power amplifiers has bee ivestigated extesively. o liearly amplify the modulated sigals, the PAs typically operate i a back-off power regio at the expese of efficiecy. However, polar modulatio trasmitter architecture [], where a phase modulated sigal with costat evelope is amplified by a o-liear (switchig type) PA, has the potetial to ehace the efficiecy while achievig high liearity. Due to aggressive scalig i device dimesios for improvig speed ad fuctioality, CMOS trasistors i the aometer regime cotiue to edure major reliability issues such as chael hot electro degradatio [] ad gate oxide breakdow [4]. I the past 0 years, umerous papers o the stress effect o digital ad RF circuits have bee published [5-8]. For example, the gate oxide stress decreases the static oise margi of 6-trasistor SRAM cells [5]. Hot electro icreases the oise figure of the low-oise amplifier [9], ad the phase oise of the voltage-cotrolled oscillator [0]. I this work, a class F power amplifier is desiged. Its RF performaces before ad after layout are aalyzed. he desig of the class F power amplifier, the Cadece layout ad post layout simulatio results are preseted. he physical isight of the device behavior i the class F PA operatio eviromet is illustrated.

28 . Desig of Class F PA he Class F RF power amplifiers utilize multiple harmoic resoators i the output etwork to shape the drai-source voltage. he drai curret flows whe the drai-source voltage is low, ad the drai-source voltage is high where the drai curret is zero. his reduces the trasistor switchig loss ad icreases the drai efficiecy of the class F PA. I class F amplifiers with odd harmoics, the drai-source voltage cotais oly odd harmoics ad the drai curret cotais oly eve harmoics. hus, the iput impedace of the load etwork represets a ope circuit at odd harmoics ad a short circuit at eve harmoics. he DS of class F PA with odd harmoics ca be writte as DS DD m cos( 0 t) m cos( 0t) ( ),5,7,... were DD is the supply voltage, m is the fudametal compoet of drai voltage, m is the amplitude of - th harmoic of DS, ad 0 is the agular frequecy at the operatig poit. he drai curret id is give by i DS I DD I m cos( 0 t) I m cos( 0t) ( ),4,6,... where IDD is the DC curret from DD, Im is the fudametal compoet of drai curret, Im is the amplitude of - th harmoic of ids. No real power is geerated at harmoics because there is either o curret or o voltage preset at each harmoic frequecy. I class F amplifiers with eve harmoics, o the other had, the drai-source voltage cotais oly eve harmoics ad the drai curret cotais oly odd harmoics. I this work, the PA is desiged with third hamoic peakig. he detail of class F PA desig ca be referred i []. he load etwork cosists of a parallel LC resoat circuit tued to the operatig frequecy f0 ad a parallel resoat circuit tued to the third harmoic f0. he two resoat circuits 4

29 are coected i series. he ac power is delivered to the load resistor. Figure 8 shows the schematic view of the PA with a class-f output stage. he output of the iput stage trasistor is coected to the gate of the output stage trasistor by a couplig capacitor C. he circuit is tued ad simulated usig ADS software []. G DD G DD R L D C R L D C L f0 RFout RF i Iput Matchig M M C f0 C f0 L f0 Figure 8 Schematic of class F power amplifier. he class F power amplifier has bee laid out usig Cadece irtuoso software, followed by Calibre DRC for desig rule checkig ad LS for layout versus schematic verificatio. A silico chip layout of µm is displayed i Figure 9. I this figure spiral iductors, capacitors, trasistors, GSG RF iput ad output pads, biasig ad supply voltage DC pads are show. he layout (itercoectio) parasitic effects are extracted usig ADS Mometum EM simulatio to geerate s-parameters. hese s-parameters implicitly accout for itercoect resistive, capacitive, ad iductive behaviors. he extracted itercoect parasitic effects (s-parameter boxes) are the added to the origial ADS circuit simulatio for post-layout simulatio. he post-layout simulatio results are show i Figure 0 ad. he layout parasitic effect decreases the output power ad power-added efficiecy of the amplifier, as expected. Parasitic resistace itroduces additioal power loss i the circuit which reduces the power efficiecy. Layout itercoectios are very importat for CMOS RFIC parasitic effects []. o reduce layout parasitic effects, we adjust iductors, capacitors, ad trasistors locatio ad orietatio i our desig. 5

30 he simulated output curret ad voltage versus time, output power ad power-added efficiecy versus iput power are as show i Figure 0 ad, respectively. I Figure 8 the lie with triagles represets the pre-layout simulatio results ad the lie with squares represets the post-layout simulatio results. As see i Figure 8 the output power icreases with iput power ad reaches saturated output power at about 7.5 dbm. he post layout parasitics decrease the output power at a give iput power. he power-added efficiecy ( (RF output power - RF iput power)/total DC power dissipatio) icreases with iput power, reaches its peak value, ad the decreases with iput power. he power-added efficiecy starts to decrease after reachig its peak because of the gai reachig a compressio poit, resultig i the output power o loger icreasig. he maximum power-added efficiecy approaches %, drops to 9.5% after post-layout simulatio. Note that the power-added efficiecy is lower tha the drai efficiecy because of additioal power dissipatio i the iput stage. 6

31 Figure 9 Layout view of the class F power amplifier. 7

32 Output Curret (ma) ime (s) (a) Output oltage () ime (s) (b) Figure 0 (a) Output curret versus time (b) Output voltage versus time. 8

33 Output Power (dbm) pre-layout post-layout Iput Power (dbm) (a) Power-added Efficiecy (%) pre-layout Iput Power (dbm) post-layout (b) Figure (a) Output power ad power gai versus iput power. (b) Power-added efficiecy versus iput power. 9

34 .4 Mixed Mode Simulatio o evaluate the physical isight of hot electro effect i RF operatio, the mixed-mode simulatio of Setaurus CAD software is used []. he mixed-mode device ad circuit simualatio allows oe to evaluate the device physical isight uder the real circuit opreatio coditio. I Setaurus simulatio, physical equatios such as Poisso s ad cotiuity equatios for drift-diffusio trasport are implemeted. he Shockley-Read-Hall carrier recombiatio, Auger recombiatio, ad impact ioizatio models are also used. he impact ioizatio va Overstraetede Ma model [4] assumes the impact ioizatio coefficiet to be a fuctio of the local field. o accout for lattice heatig, hermodyamic, hermode, RecGeHeat, ad AalyticEP models i Setaurus are used. he thermodyamic model exteds the drift-diffusio approach to accout for electrothermal effects. A hermode is a boudary where the Dirichlet boudary coditio is set for the lattice. RecGeHeat icludes geeratio-recombiatio heat sources. AalyticEP gives aalytical expressio for thermoelectric power. he ambiet temperature is at 00 K. Figure ad show the gate-source voltage ad drai-source voltage of the iput trasistor M ad the output trasistor M from Setaurus simulatio. It is clear from Figure ad that the output trasistor has much larger GS ad DS swigs tha those of the iput trasistor. Whe the gate-source voltage is above the threshold voltage ad the drai-source voltage is very high, the trasistor is uder high electric field stress. Sufficiet high field may trigger device avalache ad hot carrier ijectio. 0

35 M rasistor oltage () GS DS ime (s) Figure Drai-source ad gate-source voltage of the iput trasistor M. M rasistor oltage () DS GS ime (s) Figure Drai-source ad gate-source voltage of the output trasistor M. Figure 4 shows impact ioizatio rates for the iput ad output trasistor trasistors of the PA at high DS. he supply voltage i Setarus simulatio is set at DD =.. As see i Figure 4 the

36 I.I. rates at the peak of output voltage waveform from M (left plot) are much higher tha those i M (right plot). High impact ioizatio rates ( 0 0 /cm /s) at the drai of M trasistor suggest large hot electro ijectio ito the gate of the M ear the drai edge. Hot electro effects result i the MOS trasistor performace degradatio [5]. Figure 5 shows the lattice temperature of M ad M. he maximum lattice temperature at the drai of M icreases to about 0 K, while the lattice temperature of M is virtually the same from source to drai. he curret desity i M is higher tha that i M due to larger gate-source voltage ad drai-source voltage simultaeously (data ot show here). High curert desity ad high drai voltage produce self-heatig ad high lattice temperature ear the drai edge. From the reliability poit of view, the output stage trasistor of the class F power amplifier is more vulerable to chael hot electro effect ad gate oxide stress. It is clear from Fig. that the peak drai-gate voltage of the secod stage trasistor is above 5.6 due to larger DS ad GS which provides high voltage stress betwee the drai ad gate oxide. For example, the electric field of a 4- m oxide thickess at 5.6 voltage stress ca approach 4 M/cm, a precursor for gate-drai oxide breakdow. Note that the drai stress voltage ca further icrease whe the supply voltage DD icreases. Figure 4 Impact ioizatio rates of the iput stage (left plot) ad output stage (right plot) trasistors.

37 Figure 5 Lattice temperature of the iput stage (left plot) ad output stage (right plot) trasistors. he oxide uder high voltage stress may experiece some kid of soft breakdow before hard breakdow [6]. Soft breakdow icreases the gate leakage curret oise due to formulatio of radom defects ad coductig path withi the oxide [7]. Soft breakdow effect may be modeled usig oliear curret sources [9], while the hard breakdow ca be realized by usig breakdow resistaces [8]. I geeral, oxide breakdow decreases the output power ad power efficiecy of power amplifiers [9]..5 RF Stress Simulatio Hot electro ijectio origiates from eergetic electros or holes i the chael eterig oxide layer produce oxide trap charge ad iterface states, which i tur icrease the trasistor threshold voltage ad decreases the effective chael electro mobility. he output power ad poweradded efficiecy versus threshold voltage shift ad mobility degradatio are depicted i Figs. 6 ad 7, respectively. I geeral, the threshold voltage shift accumulates over time ( t ). o accout for differet degrees of hot electro stress effects o M ad M over a period of time, the shift of threshold voltage i M is modeled differetly tha that i M. For example, 0 i M could be set to /8, ¼, ½, ad 0 of M. As see i Fig. 6(a) the largest output power degradatio occurs

38 whe 0 M =0 M. his is because the output of the first stage trasistor M drives the secod stage trasistor M for output power. Whe the iput trasistor s drivig curret drops, the overall output power of the PA decreases. Similar characteristics are observed for the output power versus electro mobility shift. he output power decreases whe the electro mobility decreases. he worst case of degradatio occurs whe M = M as show i Fig. 6(b). Furthermore, the ormalized power-added efficiecy versus ormalized threshold voltage shift ad mobility degradatio has bee examied. he simulatio results are show i Fig. 7. he poweradded efficiecy decreases with the icrease i threshold voltage ad the decrease i electro mobility. Agai, the worst case of degradatio occurs whe 0 M =0 M ad M = M. o reduce hot electro degradatio effects o power amplifier performace, the cascode trasistor topology may be used to reduce electro field o the drai edge of MOS trasistors. 4

39 0-5 0 M = M P o /P o (%) M = 0 M 0 M = M 0 M = M -0 M: iput trasistor of the PA M: output trasistor of the PA / 0 (%) (a) 0 P o /P o (%) M = M M = 0.5 M M = 0.5 M M: iput trasistor of the PA M: output trasistor of the PA M = 0.5 M / (%) (b) Figure 6 Normalized output power versus (a) threshold voltage ad (b) mobility shift 5

40 add add (%) M = 0 M 0 M = 0 M 0 M = M M: iput trasistor of the PA M: output trasistor of the PA 0 M = M / 0 (%) (a) add add (%) M = M M = 0.5 M M = M M: iput trasistor of the PA M: output trasistor of the PA M = 0.5 M / (%) (b) Figure 7 Normalized power-added efficiecy versus (a) threshold voltage ad (b) mobility shift. High drai curret ad high drai-source voltage result i large power dissipatio, which causes device self-heatig. he trasistor temperature rise i M is geerally larger tha that i M due 6

41 to larger dc curret ad ac power flowig through the output trasistor M. o accout for a wide rage of temperature rise, M = /8, ¼, ½, ad M are simulated. Both the output power ad power-added efficiecy decrease with icreasig temperature resultig from device self-heatig as show i Fig P o /P o (%) M = M M = M M = 0.5 M M: iput trasistor of the PA M: output trasistor of the PA M = M ( 0 C) (a) 0 add add (%) M = M M = M M = 0.5 M M: iput trasistor of the PA M: output trasistor of the PA M = M ( 0 C) (b) Figure 8 Normalized (a) output power ad (b) power-added efficiecy versus temperature rise. 7

42 .6 Summary A class F power amplifier at 5.8 GHz has bee desiged ad aalyzed. Its pre-layout ad post-layout performaces are compared. Post-layout parasitic effect decreases the output power ad power-added efficiecy. Physical isight of hot electro impact ioizatio ad device self-heatig has bee examied usig mixed-mode device ad circuit simulatio to mimic the class F PA operatig eviromet. he output trasistor has larger impact ioizatio rates ad self-heatig due to larger power dissipatio ad higher drai electric field tha those of the iput trasistor. Hot electro effect icreases the threshold voltage ad decreases the electro mobility of the -chael trasistor, which i tur decreases the output power ad power-added efficiecy of the power amplifier, as evideced by the RF circuit simulatio results. he device self-heatig also reduces the output power ad power-added efficiecy of the PA. 8

43 CHAPER FOUR: POWER AMPLIFIER RESILIEN DESIGN FOR PROCESS, OLAGE AND EMPERAURE ARIAIONS his chapter is about a robust adaptive desig techique to reduce P variatio effects o RF circuits. he adaptive body biasig scheme uses a curret source for P sesig to provide resiliece through the threshold voltage adjustmet to maitai power amplifier performace over a wide rage of variability. his adaptive body biasig techique is used to miimize P variatios of RF class AB power amplifier. 4. Curret Source Desig A o-chip variability sesor usig curret source is proposed to detect process, supply voltage, ad temperature variatios or eve reliability degradatio stemmig from hot electro effect. he P variatios yield a cotrol sigal from the desiged curret source. I Fig. the curretsource circuit is made of -chael trasistors M, M ad M. he trasistors M ad M have the same width ad legth ad two times width of trasistor M. O the right brach i Figure 9, a resistor R is used to set a cotrol voltage Ctrl. he referece curret Iref is depedet o the P fluctuatios. 9

44 DD I ref M R Ctrl M M Figure 9 Curret-source circuit schematic. he Kirchhoff s curret law to solve for Ctrl is give by Ctrl DD I ref R ( 4 ) ad Iref is the referece curret ad ca be obtaied as [0] ( Iref = DD L KW L ) KW ( 5 ) where is the threshold voltage, L is the chael legth, W is the chael width, ad K is the trascoductace factor (K = µεox/tox). Subscripts ad represet the trasistors M ad M, respectively. he Ctrl shift because of supply voltage variatio is derived usig ( ad ) 0

45 ) ( K W L K W L R DD DD Ctrl ( 6 ) he Ctrl shift due to mobility fluctuatio is give by ) ( W L W L t R DD ox ox Ctrl ( 7 ) Furthermore, the Ctrl shift resultig from fluctuatio of the threshold voltage from M or M is, K W L K W L R DD Ctrl ( 8 ) Combig (6) (8) yields the overall Ctrl variatio as follows: ( 9 ) DD DD DD ox ox DD DD Ctrl KP W L KP W L R KP W L KP W L R KP W L KP W L t R KP W L KP W L R

46 4. uig for ariability he sesitivity of the class AB PA is evaluated i Figure 0. he P variatios chage behaviors of the PA ad also degrade the performace. I the simulatio, the P variatios are give to the PA circuit. Adaptive body biasig is used to fid a rage of body biasig voltage (ABB) to compesate each variatio. Ctrl sigal is efficietly trasformed to a optimal body bias sigal for power amplifier applicatio. From a rage of ABB, a operatioal amplifier is used as a voltage shifter ad amplifier to adjust the Ctrl to meet a required ABB (see Figure 0). Choosig appropriate size of resistor R ad R usig (0) provides a matched ABB for PA. For example, for a referece voltage (ref) of 0.4, R ad R ca be desiged at 500 Ω ad 500 Ω, respectively. Figure 0 A class AB PA with adaptive body biasig. ABB R ( Ctrl ref ) ( 0 ) R Due to the body effect, the threshold voltage of the power amplifier trasistor is described by the followig expressio

47 ) ( 0 F ABB F ( ) where γ is the body effect factor ad ϕf represets the Fermipotetial. he threshold voltage shift of the PA trasistor is modeled by the fluctuatio of 0 ad ABB as ABB ABB F ABB ABB ( ) From (0) the ABB shift is give by Ctrl Ctrl Ctrl ABB ABB R R ( ) hus, the threshold voltage shift of the power amplifier iput trasistor due to P variatios are summed as 0 DD DD DD ox ox DD DD ABB F K W L K W L R K W L K W L R K W L K W L t R K W L K W L R R R ( 4 ) he drai curret fluctuatio subjects to key trasistor parametric drifts Δµ, ΔGS ad Δ ca be modeled as D GS GS D D D I I I I ( 5 )

48 4 Assume the GS shift is proportioal to the fluctuatio of DD. GS DD ( 6 ) where a is a fittig parameter. Usig (4) (6) the fluctuatio of drai curret ormalized to its fresh curret is expressed as follows: 0 DD DD DD ox ox DD DD ABB F GS GS DD K W L K W L R K W L K W L R K W L K W L t R K W L K W L R R R ( 7 ) I the above equatio the terms beyod Δ0 represet the DD, mobility, ad threshold voltage compesatio effects. o ormalized output power degradatio is related to the ormalized drai curret degradatio as follows [8]: D D I I Po Po ( 8 ) 4. Compesated Results he power amplifier with the curret source compesatio techique is compared with the PA without compesatio usig ADS simulatio. For the process variatio effect, the output power is evaluated agaist threshold voltage ad mobility variatios as show i Figure (a) ad (b). It is clear from Figure (a) ad (b) that the power amplifier with adaptive body bias is more robust agaist threshold voltage variatio (see Figure (a)) ad mobility fluctuatio (Figure (b)). For the process variatio effect, the output power of the PA has also bee evaluated usig differet

49 process corer models due to iter-die variatios. he simulatio result of the fast fast, slow slow, ad omial omial models is show i Figure. (a) (b) Figure (a) Output power versus threshold voltage shift. (b)output power versus mobility variatio 5

50 Figure Output power versus process corer models. Clearly, the PA usig the adaptive body bias compesatio exhibits better stability agaist process variatio effect. Figure ad 4 show the output power of the power amplifier versus temperature variatio ad supply voltage chage, respectively. As see i Figs. ad 4 the output power of the PA usig the adaptive body bias compesatio techique demostrates less sesitivity over temperature ad DD variatios. 6

51 Figure Output power versus temperature. Figure 4 Output power versus supply voltage. 7

52 Figure 5 Power-added efficiecy as a fuctio of threshold voltage. I additio, the power-added efficiecy of the power amplifier with or without adaptive body bias compesatio is examied agaist semicoductor process variatios effects. Figure 5 ad 6 display the improvemet of power-added efficiecy of the PA with ABB compesatio over that without adaptive body bias for the threshold voltage shift (see Figure 5) ad mobility variatio (see Figure 6). 8

53 Figure 6 Power-added efficiecy as a fuctio of mobility. Figure 7 Power-added efficiecy vs process corer models. 9

54 Figure 8 Power-added efficiecy versus temperature. Figure 9 Power-added efficiecy versus supply voltage. For the process corer models the power-added efficiecy of the PA with ABB compesatio shows less process sesitivity, as evideced by the plot i Figure 7. he, the power-added efficiecy is 40

55 compared agaist temperature ad supply voltage variatios. he power-added efficiecy is getter better for the PA with ABB compesatio as show i Figure 8 ad Summary I this work, the P compesatio of power amplifier usig a curret-source as a o-chip sesor has bee preseted. he adaptive body bias desig usig curret sesig makes the output power ad power-added efficiecy much less sesitive to process, supply voltage, ad temperature variatios, predicted by derived aalytical equatios ad verified by ADS circuit simulatio results. 4

56 CHAPER FIE: PROCESS ARIAION SUDY ON RF MIXER 5. Process ariatios o gai better speed ad further reduce coat, silico CMOS are scaled dow to m [] ad beyod. he well-kow reliability mechaisms such as gate oxide breakdow (GOB), hot carrier ijectio (HCI), ad egative bias temperature istability (NBI) remai very importat for the desig of digital ad RF circuits. HCI is associated with hot carrier get trapped i gate oxide which is deteriorated by high lateral field iduced impact ioizatio (I.I.), while GOB is related to field -iduced oxide traps or defects due to oxide vertical scalig. NBI occurs due to a build-up of positive charges occurs either at the Si/SiO iterface or i the oxide layer of p-chael MOSFEs uder egative gate bias at higher temperatures. he reactio-diffusio model [] illustrates the holes i the iversio layer of pmosfes react with the Si-H bods at the SiO/Si iterface. he hydroge species diffuse away from the iterface toward the polysilico gate. his causes the threshold voltage shift of p-mosfes. Origially, process variatios were cosidered i die to die variatios. However, with trasistors progress ito aoscale regime, itra die variatios are posig the major desig challege as techology ode scales. Fluctuatios with itrisic device parameters that result from process ucertaities have substatially affected the device characteristics. For state-of-theart ao-scale circuits ad systems, device variatio ad ucertaity of sigal propagatio time betwee dies ad iside die have become crucial i the variatio of system timig ad the determiatio of clock speed. Yield aalysis ad optimizatio, which takes ito accout the 4