ANALOG AND DIGITAL PERFORMANCE OF THE SCREEN-GRID FIELD EFFECT TRANSISTOR (SGrFET)

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Iteratioal Joural of High Speed Electroics ad Systems World Scietific Publishig Compay ANALOG AND DIGITAL PERFORMANCE OF THE SCREEN-GRID FIELD EFFECT TRANSISTOR () K. FOBELETS, P.W. DING, Y.

1 Iteratioal Joural of High Speed Electroics ad Systems World Scietific Publishig Compay ANALOG AND DIGITAL PERFORMANCE OF THE SCREEN-GRID FIELD EFFECT TRANSISTOR () K. FOBELETS, P.W. DING, Y. SHADROKH Departmet of Electrical & Electroic Egieerig, Imperial College Lodo Exhibitio Road, SW7 2BT South Kesigto, UK J.E. VELAZQUEZ-PEREZ Departmet of Applied Physics, Uiversity of Salamaca Pza de la Merced s/, 378 Salamaca, Spai Received 15 February 28 Revised 24 March 28 The Scree-Grid Field Effect Trasistor () is a plaar MOSFET-type device with a gatig cofiguratio cosistig of metal cylidrical figers iside the chael perpedicular to the curret flow. The operates i a MESFET mode usig oxide isulated gates. The multi-gate cofiguratio offers advatages for both aalog ad digital applicatios, whilst the gate cylider holes ca be exploited for bio-applicatios. I this mauscript TCAD results are preseted o the aalog ad digital performace of the Scree-Grid Field Effect Trasistor. The results are compared to the operatio of a SOI-MOSFET ad a fifet. Keywords: MOSFET; multi-gate; performace compariso; fifet. 1. Itroductio Util recetly, the research o field effect trasistors has bee cotrolled by the overpowerig presece of silico based covetioal Metal-Oxide-Semicoductor Field- Effect Trasistors (MOSFETs). This success was esured by the abudace of Si ad the quality of the silico oxide (SiO 2 ). Oly i domais such as e.g. commuicatios, where high speed operatio is required, alterative trasistor ad gatig structures have bee used. As a result of the requiremet for higher speed ad higher packig desity, the dimesios of the Si MOSFETs have bee aggressively scaled dow 1. The gate legth has bee reduced to sub-5 m, the oxide thickess to 1.2 m, the dopig i the chael has icreased ad the juctio depth has decreased. The MOSFET has ow reached GHz operatio speeds as a result of this dramatic dowscalig. However, the price for this speed performace is a icrease i power cosumptio that results from the leakage currets that are partially associated with short chael effects (SCEs) 2. Oe of the importat parameters that bechmark the SCEs is Drai Iduced Barrier Lowerig (DIBL). DIBL is related to a threshold voltage shift as a fuctio of applied drai bias ad is a cosequece of the ifluece of the drai potetial o the source-chael 1

2 2 K. Fobelets, P.W. Dig, Y. Shadrokh, ad J.E. Velazquez-Perez potetial barrier. I electrically robust MOSFETs, the source-chael potetial barrier is cotrolled by the gate voltage oly, however, for dramatically reduced gate legths where the drai becomes close to the source, the drai potetial shares the cotrol of the barrier with the gate. I order to prevet the drai from takig cotrol, the dopig level i the chael is icreased. This practice severely reduces the mobility of the carriers i the chael due to impurity scatterig. As a cosequece of all these factors, MOSFET techology has ow reached the poit where idustry is actively pursuig research ito alterative field effect trasistor structures preferably based o Si. The first accepted chage was the itroductio of silico-o-isulator substrates (SOI) 3. A approach that takes cotrol of the leakage ito the substrate ad that reduces the parasitic capacitaces of the juctios. Aother approach that has proved successful is the multi-gate FET (MuGFET). Although it was kow for a log time that addig supplemetary gates will improve the cotrol of the carriers i the chael ad therefore help to cotai DIBL, the MuGFET idea oly became successful with the discovery of a CMOS-compatible fabricatio approach. Now the best kow MuGFET is the fifet 4. The fifet has a out-of-plae chael (the fi) that is partially surrouded by the gate electrode. FiFETs take advatage of the SOI techology to restrict carrier flow to the chael. Apart from these popular high-visibility alterative MOSFET structures, the research literature presets may more sophisticated approaches; examples iclude the wrap-aroud aowire FET 5, the ballistic deflectio trasistor 6, the source-gated trasistor 7, the Scree-Grid Field Effect Trasistor () 8, etc. I this mauscript the aalog ad digital performace of the will be evaluated ad compared to that of the SOI-MOSFET ad fifet. The evaluatio ad compariso will be doe usig TCAD from Syopsys 9, 2D Medici ad 3D Taurus. The mauscript is orgaized as follows: sectio 2 describes the differet device structures used i the simulatios ad gives some DC performace compariso. I 3 the aalog RF performace is compared. I 4 the use of the multi-gate character of the ad fifet for digital applicatios is explored. Coclusios are preseted i The simulated device structures Three devices, SOI-MOSFET, fifet ad were simulated i order to make a performace compariso betwee them. The simulatios were doe usig the hydrodyamic model ad the full coupled eergy balace equatios where ecessary. The field effect mobility is used to take ito accout the ifluece of the effective electric field o the mobility of the carriers. The aalog performace is studied usig 3D Taurus simulatios. The digital performace is doe i 2D as the circuits cosist of more tha oe trasistor ad thus create a large umber of mesh poits that ca impede covergece of the simulatios. The simulated 3D structures obtaied via the Taurus process simulatio software are show i fig. l.

Aalog ad digital performace of the 3 a) b) c) Fig. 1. Three differet devices fabricated usig Taurus process simulatio. Gree: Si, yellow: isulator, red: gate. Source ad drai are at the left, resp.

I order to visualize the fuctioig of the differet structures a cross-sectio is take from surface ito the buried oxide (BOX) layer for the SOI-MOSFET ad perpedicular to the surface for both fifet ad.

The chael/fi regio is checked, light grey is oxide, dark grey is depletio regio, dotted dark grey are the gate cotacts.

3 Aalog ad digital performace of the 3 a) b) c) Fig. 1. Three differet devices fabricated usig Taurus process simulatio. Gree: Si, yellow: isulator, red: gate. Source ad drai are at the left, resp. right of the gated area i all devices. a) SOI-MOSFET, b) a fifet with 4 parallel fis ad c) ad with 4 parallel chaels/uit cells. I order to visualize the fuctioig of the differet structures a cross-sectio is take from surface ito the buried oxide (BOX) layer for the SOI-MOSFET ad perpedicular to the surface for both fifet ad. These cross sectios are give i fig. 2. SOI-MOSFET L SD V GS fifet L SD V GS V GS L SD V GS t Si V DS W fi V DS L u L c V DS V GS V GS V GS Fig. 2. The cross sectio through oe chael/fi regio for the three devices. The chael/fi regio is checked, light grey is oxide, dark grey is depletio regio, dotted dark grey are the gate cotacts. Black arrows idicate the directio of the field imposed by the gate voltage, grey arrows idicate the positio ad directio of the carrier flow. The geometry give for the is called a uit cell. The mai differeces see i the schematic cross sectios i fig. 2 are that the SOI- MOSFET has oe chael created by iversio at the Si/SiO 2 iterface. Thus the carriers will scatter at this iterface reducig the chael mobility µ. Uless the Si body thickess t Si is sufficietly thi, this device will suffer from SCE. The fifet ca have two chaels for oe fi, both created by iversio. The chael is close to the oxide iterface ad thus mobility will be similarly reduced by iterface roughess scatterig. The fifet is robust agaist dowscalig if the fi width W fi is correctly scaled with the sourcedrai distace L SD. The has oe chael for the same dimesios as the fifet. The fuctios by cotrollig the carrier desity by depletio as i a MESFET. The carriers flow away from the iterface, thus suffer reduced surface roughess scatterig ad have higher mobility. The is robust agaist dowscalig whe the

4 4 K. Fobelets, P.W. Dig, Y. Shadrokh, ad J.E. Velazquez-Perez width L c is reduced with a reductio of L SD. The gate legth i the is ucoupled from the source-drai distace but the miimum L SD is imposed by the radius of the gate cyliders. The depletio widths aroud the gates are ot symmetrical i the legth of the device. Those aroud the drai-side gates expad faster with drai voltage tha the source-sided oes. The row of gates ear the drai electrostatically shield the source from the drai potetial, prevetig its parasitic cotrol of the source-chael barrier ad thus helps to cotrol DIBL [8]. A compariso of the mai performace bechmarks: threshold voltage, subthreshold slope ad DIBL are give i fig. 3 as a fuctio of source-drai distace L SD. The gate for all devices is Al with a workfuctio of φ Al =4.1eV. The chael dopig is N A/D = 1 15 cm Threshold voltage (V) fifet L S-D (m) Sub-threshold Slope (mv/dec) fifet Threshold voltage DIBL shift (mv/v) fifet LS-D (m) LS-D (m) Fig.3. Dowscalig tred of some device bechmarks, threshold voltage (top), subthreshold slope (left bottom) ad drai iduced barrier lowerig (right bottom) for the, the fifet ad the SOI-MOSFET. The simulated bechmark parameters preseted i fig. 3 are typical DC parameters ad thus do ot take ito accout capacitive parasitics. The simulatios are doe for all devices with the same dimesios: t Si = 4 m (the Si body thickess o top of the SOI layer), t ox = 5 m (oxide thickess), W fi = L u = 3 m (the fi width resp. uit cell width), thus L c = 25 m for the. The radius of the gate cyliders for the is 5 m. From the graphs i fig. 3 we coclude that the shows a excellet robustess

5 Aalog ad digital performace of the 5 agaist SCE, high potetial for ultra low-power applicatios (the subthreshold slope is very close to the theoretical limit) ad immuity agaist threshold voltage roll-off with dowscalig. The drawback at these small dimesios is that e-beam lithography (or soft impritig techiques) is ecessary to defie the device fabricatio steps that are curretly maily used i research ad developmet eviromets. 3. Aalog RF performace of the devices The radio frequecy (RF) performace of the devices is ivestigated usig Taurus. The AC small-sigal simulatios give the Y-parameters as a fuctio of frequecy ad bias voltages. From these, the high frequecy parameters such as small-sigal curret gai (h21) ad Maso uilateral power gai (U) ca be derived, which yield the correspodig cut-off frequecies (f T ) ad the maximum oscillatio frequecy (f max ). Basic aalog parameters such as trascoductace (g m ), trascoductace efficiecy (g m /I DS ), output resistace (r o ) ad itrisic voltage gai (A v ) ca also be extracted. The device simulatios are carried out igorig ay cotact resistace of gate, source ad drai. This assumptio causes a overestimatio of the high frequecy performace. Additioally the hydrodyamic model, which is used for icreased accuracy at small device dimesios, teds to predict higher trascoductace 1 ad lower gate-to-source capacitace, C GS 11 tha what is experimetally obtaied. Thus the extracted cut-off frequecy will be overestimated. This however is ot a issue i a comparative study. I order to extract r o =1/g ds, g m /I DS, f T ad A v =g m /g ds a simple MOSFET equivalet circuit has bee used for all devices, give i fig. 4. G C gd D v gs C gs g m v gs g ds C ds S Fig. 4: Simple equivalet circuit for all FETs icludig the gate-source capacitace C gs, the gate-drai capacitace C gd, the drai-source capacitace C ds, the output coductace g ds ad the curret source g m v gs g m is the trascoductace. The circuit compoets are the extracted from the simulated Y-parameters as 12 : Im( Y ) C GD = 12 (1) w C GS = C GG C GD Im( Y = 11 ) CGD (2) w g m = Re( Y 21 ) (3)

6 6 K. Fobelets, P.W. Dig, Y. Shadrokh, ad J.E. Velazquez-Perez g (4) ds = Re( Y22 ) w= f T g m gm = (5) 2π ( C + C ) 2πC GS GD GG where C GG is the total gate capacitace. The cut-off frequecy f T give i (5) is oly a approximatio ad i this work f T has bee derived by plottig the simulated curret gai h21 as a fuctio of frequecy. The frequecy where h21 becomes uity defies f T. The magitude of curret gai, h21 is give by: Y21 h 21 = (6) Y 11 Output Resistace (kω/µm) fifet Trascoductace Efficiecy (V -1 ) 3.5E+1 3.E+1 2.5E+1 2.E+1 1.5E+1 1.E+1 5.E+ fifet Cutoff Frequecy (Hz) 4.E E+11 3.E E+11 2.E E+11 1.E+11 5.E+1..E+ 1.E-4 2.E-4 3.E-4 Drai Curret (A/µm) fifet.e+.e+ 1.E-4 2.E-4 3.E-4 Drai Curret (A/µm) Cutoff Frequecy (Hz) 1.E-17 1.E-8 1.E-7 1.E-6 1.E-5 1.E-4 1.E-3 5.E E+11 4.E E+11 3.E E+11 2.E E+11 Drai Curret (A/µm) 1.E LS-D (m) fifet Voltage Gai (db) Fig. 5. The performace parameters of the, SOI-MOSFET ad the fifet as a fuctio of curret drive. Bottom right: the cut-off frequecy, f T ad voltage gai, A v as a fuctio of source-drai distace, L SD at a curret drive of.1 A/µm as idicated i bottom left figure. Dashed lies: A v, full lies f T. I fig. 5, r o, g m /I DS ad f T are give as a fuctio of source-drai curret for the three devices uder study. f T ad A v as a fuctio of L SD are also show. r o ad g m /I DS are best i the whilst f T is highest i the SOI-MOSFET. The graph o dowscalig gives a iterestig result: A v is ot degraded for the whilst dowscalig. This result stads i cotrast with all other FET behavior which shows systematic A v degradatio for

7 Aalog ad digital performace of the 7 smaller source-drai distaces. The price that is paid for this gai however is a lower f T for the. As ca be see from the g m /I DS plot, the behaves best at lower curret levels, cofirmig the potetial of the for low-power applicatios as poited out before. This is because whe drivig the i strog iversio the iversio chael aroud the circular gate figers do ot overlap ad therefore the eergy used for iversio ca ot be exploited for higher curret drive. This ca chage whe explorig still smaller dimesios i which the iversio layers iteract. 4. Digital performace of the devices 2D TCAD has bee used to aalyze ad compare the digital performace of the with the fifet of the same dimesios. Both device types are ideally suited for multigate fuctioality (MuGFETs) where differet gate voltages are applied to the differet gate cotacts. A aalysis of the digital oly was preseted i [13]. I this mauscript we will focus o a compariso of the switchig speeds ad multi-gate operatio of both techologies. The MuGFET approach reduces the circuit complexity ad ehaces speed. The gate metal for the ehacemet mode devices is Au (φ Au =4.8eV) ad for the depletio mode devices Al. The chael has a dopig of N A/D = 1 15 cm -3. a) b) V i V i p C- - C-fiFET -fifet c) d) Vout (V) V i V i p Vi (V) Fig. 6. Left: Defiitio of device circuit symbols ad circuit. Black/white device rectagle: depletio/iversio mode. Letter i rectagle defies device type. a) - iverter, b) C- iverter c) -fifet iverter [12] d) C-fiFET iverter [12]. Right: output characteristic. =.27fF ad.24ff for the ad fifet respectively. = 1V. Four differet logic gates have bee ivestigated, the iverter, NAND, NOR ad XOR. The dimesios of the devices are: gate oxide thickess t ox = 2 m, source-drai distace L SD = 14 m, L c = W fi = 5 m (see fig.2). This meas that the width of a uit cell is L u = 2 L o /2+2 t ox +L c. The diameter of the gate cyliders is L o = 5 m. The gate

8 8 K. Fobelets, P.W. Dig, Y. Shadrokh, ad J.E. Velazquez-Perez diameter is a extra parameter that ca be used to cotrol its operatio. All circuits operate at = 1V. Note that the is ot as aggressively scaled dow as for the aalog performace study i order to allow sufficiet drive curret. The fifet circuits are as those preseted i [14], the reader is referred to the circuit diagrams preseted i [14]. I fig. 6 the iverter circuits, both CMOS ad all -MOS are give together with the output characteristics for both fifet ad. The differece betwee the outputs from both devices is egligible. The all -type iverters exhibit the typical poor switch-off characteristics. Icreasig the width of the driver mitigates this problem but does ot solve it. I the good off-switchig ca be obtaied by addig extra uit cells to the driver. This icreases curret drive whilst retaiig the other FET parameters. The total width of the driver for N uit cells the becomes N L u ad the umber of gate figers (N+1) 2, with the gate figers at the outer edges halve cyliders. Thus the complete switch-off character comes at a price of a icreased footprit to 312 m. The same approach for fifets eeds N parallel fis, givig a footprit of mi. 25m for N=3. This is possible for the iverter circuits but for the other logic circuits, where the gate at each side of all fis eeds a idepedet voltage, this approach will be difficult to implemet. Therefore i those fifet circuits icreased curret drive i the driver ca oly be practically doe by icreasig its width. This teds to reduce its V DD V 1 p R1 R 2 V 2 V 2 V 1b V 1 V 2 V 2b V 1 performace. Fig. 7: logic circuits. (left) NAND, (middle) NOR, (right) XOR. For full switch off, a 3 uit cell device is used. V 1,2 max=1v ad =1V. V ib meas NOT(V i) with i=1,2. The fifet circuits ca be foud i [13]. The multi-uit cell approach was used i the NAND, NOR ad XOR circuits, the circuit diagrams are give i fig. 7. I the logic gates a 3-uit cell device is used to obtai complete switch-off. Note that the XOR ca be costructed with oly 2 s. Table 1: The rise time of the differet logic circuits usig fifets or s. Device Type Circuit & delay NAND t r (ps) NOR t r (ps) fifet XOR t r (ps)

9 Aalog ad digital performace of the 9 For the fifet logic gates the fi width is icreased to 3 W fi =15m to miimize leakage while maitaiig good fifet performace. However o full OFF-switchig could be obtaied uless the maximum value of the iput voltage is icreased to 1.5V, a impractical solutio. Oly the switchig characteristics of the XOR are give here (see fig. 8). The fifet XOR cosists or 3 devices [14]. The poor performace of the fifet XOR circuit is potetially due to the ustable circuit ode where the source ad drai electrodes of the two drivers are coected V1=1 V1=1 V1= V1= V2=1 V2= V2= V2=1 4 5 time (s) V1= 1V1=1 2 V1= 3 V1=1 4 5 V2= V2= V2=1 t ime (s) V2=1 Fig. 8. Left: XOR output characteristics, right: fifet XOR output characteristics. Values of the iput voltages i each time period of 1 s are give i grey o the x-axis. A summary of the performace of the differet logic circuits is give i Table 1. The results show that the logic is faster tha the fifet logic. This result must be attributed to the higher mobility of carriers i the tha the fifet ad the uit cell cofiguratio of the. Table 2 gives the ON ad OFF currets i all devices whe takig the iput voltage for ON=1V ad OFF=V. As the threshold voltage of both ad fifet are the same withi ±.1V, the gate voltage overdrive at V ON is approximately the same for both devices. ON currets i fifets are higher tha i s ad thus cosume more power durig switchig. OFF currets i fifets are also higher ad thus the stad-by power cosumptio will be higher. This result leads us to coclude that the ca deliver faster switchig speed i its split-gate logic cofiguratio for reduced power cosumptio tha the fifet with the same geometrical dimesios. Table 2: ON ad OFF state for ehacemet mode, I N,P deotes,p-type device curret. V i (V) I N- (A/µm 2 ) I P- (A/µm 2 ) I N-fiFET (A/µm 2 ) I P-fiFET (A/µm 2 ) V ON = =1 V 2.8E E E E -4 V OFF = V 8.23E E E E Coclusios The performace of the compares well to that of both the fifet ad the more traditioal SOI-MOSFET. The RF performace aalysis shows that the desig of the allows it to preserve high values of the low-frequecy voltage gai uder aggressive chael scalig. This is a strog feature as all FETs suffer from a loss of

10 1 K. Fobelets, P.W. Dig, Y. Shadrokh, ad J.E. Velazquez-Perez voltage gai for decreased gate legths. The exhibits lower cut-off frequecies, f T tha its couterparts oly for higher values of drai curret, whereas the f T values are similar for low-power applicatios i the three trasistors. For digital applicatios the leds itself well for low power, high speed operatio with reduced devices per circuit ad high switchig speeds. The footprit of the is larger tha the fifet but the multiple uit cell approach esures low OFF currets. Ackowledgmets This research has bee partially fuded by EPSRC grat umber EP/E2315/1. JEVP thaks MEC-FEDER (TEC /MIC) ad MMA (52/26) for fiacial support. Refereces 1 Y. Taur, D.A. Buchaa, W. Che, D.J. Frak, K.E. Ismail, S.H. Lo, G.A. SaiHalasz, R.G. Viswaatha, H.J.C. Wa, S.J. Wid ad H.S. Wog, Proc. IEEE 85(4), 486 (1997). 2 A. Chaudhry ad M.J. Kumar, IEEE Tras. Dev. Mat. Reliability 4(1), 99 (24 ) 3 S. Cristoloveau, D. Muteau, M.S.T. Liu, IEEE Tras. Electro Dev. 47(5), 118 (2). 4 D. Hisamoto, W.C. Lee, J. Kedzierski, H. Takeuchi, K. Asao, C. Kuo, E. Aderso, T.J. Kig, J. Bokor, C.M. Hu, IEEE Tras Electro Dev. 47(12), 232 (2). 5 N. Sigh, A. Agarwal, L.K. Bera, T.Y. Liow, R. Yag, S.C. Rustagi, C.H. Tug, R. Kumar, G.Q. Lo, N. Balasubramaia ad D.L. Kwog, IEEE Electro Dev. Lett. 27(5) 383 (26). 6 Q. Diduck, M. Feldma, ad M. Margala, A Room Temperature Ballistic Deflectio Trasistor for THz Applicatios, WOFE 7 Cozumel, Mexico December (27). 7 F. Ballo, ad J.M. Shao, B.J. Sealy, Appl. Phys. Lett. 86(7), 7353 (25) 8 K. Fobelets, P.W. Dig, ad J.E. Velazquez-Perez, Solid-State Electroics 51(5), 749 (27) T. Grasser, et al., Proc. IEEE 91(2), 251 (23) 11 T. Oh, C. Jugema, ad R.W. Dutto, Hydrodyamic simulatio of RF oise i deep-submicro MOSFETs, i Proc. It. Cof. o Simulatio of Semico. Processes ad Dev. Masachussets, USA, 3-5 September 23, p M.S. Alam, ad G.A. Armstrog, Solid State Electro., 48(5) 669 (23) 13 Y. Shadrokh, K. Fobelets, ad J.E. Velázquez-Pérez, Two Device Scree Grid Field Effect Trasistor Logic, accepted i the Romaia Joural of Iformatio Sciece ad Techology (27) 14 S. Mitra, A. Salma, D.P. Ioaou, C. Tretz, ad D.E. Ioaou, Solid-State Electro. 48(1-11), 1727 (24).

R. W. Erickson. Department of Electrical, Computer, and Energy Engineering University of Colorado, Boulder

R. W. Erickson. Department of Electrical, Computer, and Energy Engineering University of Colorado, Boulder R. W. Erickso Departmet of Electrical, Computer, ad Eergy Egieerig Uiversity of Colorado, Boulder Specific o-resistace R o as a fuctio of breakdow voltage V B Majority-carrier device: AARR #$ = kk μμ $