Improvement of Commutation Time in Matrix Converter

Transcription

1 Iteratioal Joural of Scietific & Egieerig Research Volume 3, Issue 6, Jue-01 1 ISSN Improvemet of Commutatio Time i Matrix Coverter Idrajit Sarkar, Sumata Kumar Show, Prasid Syam Abstract Matrix Coverter is a ear ideal static frequecy chager which provides solutio to the problem of covertig ac from oe frequecy ad oe magitude to variable frequecy ad variable magitude ac, without ay bulky eergy storig compoets like capacitors or iduct ors. Oe of the major obstacles towards commercial acceptace of this topology has bee the commutatio of the bidirectioal switches. A attempt has bee made here to fid a very fast ad simple but safe curret commutatio techique. It has bee foud that with simple modificatio of the Iput Curret Filterig circuit ad Diode Clamp circuit; the Stepless curret commutatio ca be achieved givig the fastest, safe ad simplest commutatio techique without ay voltage & curret sesors ad complex commutatio steps. The differet aspects of this realizatio are verified through s imulatio i PSPICE ad Hardware implemetatio. The challeges still uresolved are also metioed. Idex Terms Commutatio Time, Curret Commutatio, Diode Clamp Circuit, Matrix Coverter, Iput Curret Filter, Stepless Curret Commutatio, Udamped LC Filter 1 INTRODUCTION P OWER frequecy chager is a itegral part of ac drive applicatios. From power quality poit of view, it is desirable to use a compact voltage source coverter to provide siusoidal output voltages with varyig amplitude ad frequecy, while drawig siusoidal iput currets with uity power factor from the ac source. The Matrix Coverter offers a almost all silico solutio for early ideal solid state power frequecy chager [1]. The importat features of Matrix Coverter are - (a) Simple ad compact power circuit (b) Geeratio of load voltage of variable amplitude ad frequecy (b) Siusoidal iput ad output curret waveforms with reductio of higher order harmoics (c) Cotrol over iput power factor irrespective of loads (d) Iheret bi-directioal power flow (e) Miimum eergy storage requiremet Idrajit Sarkar is curretly pursuig Masters i Electrical Egieerig (Specializatio - Power Electroics Ad Drives) at Begal Egieerig Ad Sciece Uiversity (BESU), Shibpur, Idia, PH E- mail: jsr.idrajit@gmail.com SumataKumar Show is curretly workig at IIT Kharagpur, Idia as a Project Assistat, PH sumata.show@gmail.com Prasid Syam, Professor, Departmet of EE, BESU, Shibpur, Idia, PH prasidsyam@yahoo.co.uk, ps@ee.becs.ac.i Although it ca fulfil all of these ideal characteristics, there is however some practical issues i its implemetatio. Sice there are o freewheelig paths, it is difficult to reliably commutate curret from oe bi-directioal switch cell to other, without iterruptig the load curret ad simultaeously ot causig iput short circuit. Thus commutatios are usually carried out i differet steps ad commutatio time thus depeds o the switchig time of the devices udergoig commutatio, implyig it limits the maximum switchig frequecy. Matrix Coverter uses a array of self cotrolled bidirectioal semicoductor switches ad ca give variable magitude variable frequecy output voltage without havig ay dc lik bulky eergy storig elemets. Iput filters cosistig of shut capacitors ad lie iductors are ecessary to elimiate high frequecy uwated curret compoets eterig ito the supply utility. A high speed diode bridge clamp circuit coectig iput ad output is required to reduce over voltages across the switches durig fault or whe iput supply goes off. CURRENT COMMUTATION The process of turig off a coductig semicoductor switch ad turig o a o-coductig semicoductor switch without iterruptig the load curret is kow as Curret Commutatio [1]. As show i figure 1 curret commutatio is takig place from switch cell-s1 to switch cell-s for output phase U ad from switch cell-s3 to switch cell-s4 for output phase V. It is a itegral part of a Matrix Coverter realizatio where load curret eeds to be trasferred i ay oe of the three iput phases depedig upo the modulatio logic usig oe of the three differet bi-directioal switch cells coectig a output phase to the iput phases. A switch cell is geerally costructed usig IGBTs ad diodes i various cofiguratios for medium power applicatios. There are differet schemes used for curret commutatio [1-5]. All schemes try to follow the switchig costraits ad also take ito accout the fiite switchig times of semicoductor devices ad sesor delays. Some of these rely o output curret directio, while others rely o relative magitudes of iput voltages to activate the commutatio stages. Switchig costrais are - 1) The iput phases ca ever be shorted (short circuit may result large amout of currets through phases).

2 Iteratioal Joural of Scietific & Egieerig Research Volume 3, Issue 6, Jue-01 ISSN ) Assumig output curret to be iductive i ature, the out put phases must ot be left ope (ope circuit may destroy switches due to switchig voltage spikes)..1 Basic Curret Commutatio I Overlap Curret Commutatio, the icomig cell is fired before the outgoig cell is switched off. This would ormally cause a lie-to-lie short circuit. Extra lie iductace slow dows the rise of curret so that safe commutatio is achieved. This is ot a desirable method sice the iductors used are large. The switchig time for each commutatio is also greatly icreased which may cause cotrol problems. I Dead-Time Commutatio there is a period where o devices are gated causig a mometary ope circuit of the load. Subbers or clampig devices are the eeded across the switch cells to provide a path for the load curret. This method is udesirable sice eergy is lost durig every commutatio. The bidirectioal ature of the switch cells further complicates the subber desig. The clampig devices ad the power loss associated with them also results i icreased coverter volume. Output curret directio based we have Four Step, Three Step, Two Step ad Sigle Step Curret commutatio strategies. I cotrast to the above metioed curret commutatio strategies, where we eed either curret ad/or voltage sesig circuits (relative magitudes as well as directios) to commutate switch cell currets, a Stepless Curret commutatio strategy [9,1] is proposed where such circuits are ot required. I case of Stepless Curret commutatio strategy switchig sigals are provided to both of the switches i a sigle switch cell simultaeously ad this is doe irrespective of the magitude ad directios of voltage ad curret. The respective switch will O i accordace with the directio ad magitude of voltage ad curret, which implies that the switchig loss will remai same as that of sigle step curret commutatio, eglectig extra losses due to short circuit for very small duratio of time (00 s) if ay. Commutatio iterval will reduce sigificatly ad limited oly by the turoff/tur-o time of the devices. But Stepless Curret commutatio results high iput short circuit curret, uless ot limited by exteral circuits ad high Ldi/dt voltage at the output (uless the iductive eergy is ot coverted to capacitive stored eergy) i case of output ope circuit for iductive load. Iput short circuit curret ca be limited by iput curret filter circuit with appropriate modificatios ad output ope circuit ca be mitigated by Diode Clamp circuit, which ormally exists for protectio i Matrix Coverter. I our simulatio study ad hardware implemetatio we have adopted Stepless Curret commutatio strategy with some modificatios i the Iput Filter circuit to limit iput short circuit curret ad with some modificatios of the Diode Clamp circuit to limit output voltage spikes.. Safe ad Reliable Curret Commutatio Two differet commutatio strategies are: i) Relative iput voltage magitude based curret commutatio ii) Output curret directio detectio based curret commutatio.3 Output Curret Based Commutatio Strategy Fig. 1 Two phase to Two phase Matrix Coverter with IputCurret Filter Circuit ad Clamp Capacitor Circuit Fig. Logic sigal applied to the Gates of IGBT S1F, S1R, SF ad SR i Stepless Curret Commutatio

3 Iteratioal Joural of Scietific & Egieerig Research Volume 3, Issue 6, Jue-01 3 ISSN INPUT CURRENT FILTER CIRCUIT I Matrix Coverter, Iput Filter basically serves to mitigate ear switchig frequecy curret i the iput supply lies. This filter circuit is also used for safe Stepless Curret commutatio. Prelimiary idea for the filter desig is take from [5] ad the aalysis is exteded to suit our purpose. 3.1 Udamped LC Filter as Iput Filter The udamped L-C passive filter is a secod order filter provides 1dB per octave of atteuatio after the cutoff frequecy f. Gai = Curret through filter Capacitor/ Source Curret (Ii). Takig source as a curret source it has o gai after f ad presets a peakig at resoat frequecy f. Fig. 4 Gai ad Phase Plots Where f = 1 LC Fig. 3 Iput Curret Filter Hz I case of damped iput filter - S R S L 1 LC Where R = Dampig resistace. 0 Comparig it with secod order equatio - S S R L, 0 1 LC, R Where ξ = Dampig co-efficiet ad C L = Natural frequecy of oscillatio. I our study switchig frequecy take as 7.8 KHz ad f to be 1/3rd of it = 7.8/3 =.6 KHz. The value of filter iductor ad filter capacitor [10] take as 0.78mH (as available i the lab), 6 μf (Two capacitors i parallel 3 µf each) ad the correspodig cutoff frequecy f =.36 KHz. Dampig resistace used as 1 Ω ad a additioal resistace of 0.1 Ω is provided by the filter iductor, hece dampig resistace becomes 1.1 Ω ad dampig coefficiet is.048. From above MATLAB Gai ad Phase plots for the LC Curret filter used, the gai becomes positive ad phase becomes zero after f. Itroductio of a extra resistace i series with filter capacitor reduces the magitude of iput short circuit curret for stepless curret commutatio. But this will itroduce further loss i the filter circuit ad icrease the impedace of the brach which will reduce the share of the iput high frequecy curret. Therefore to meet both eds the iput filter is modified as follows. 3. Modified Iput Filter Figure 1 shows a Two phase to Two phase Matrix Coverter. I our simulatio study two phases are take as 110 Volts 0 ad 110 Volts 10 (50 Hz). Two outputs loads are Load1 as 48.6 Ω ad 1.89 mh, Load 59.6 Ω ad mh. Switchig frequecy is take as 7.8 KHz. Iductors L1 ad L of 70 μh are itroduced i series with R-C i order to limit short circuit curret as well as to reduce watt loss i R11 ad R1. I this case dampig co-efficiet reduces a bit. Iductor i series with R-C may block high frequecy currets through L-R-C brach resultig voltage spikes at the coverter iput, hece a path is provided for high frequecy curret compoets with reduced magitude by usig aother resistor R1 ad R i parallel with L11 ad L1 of L-C filter respectively. The Iput Filter arragemet is show i the figure 1. The L-C filter compoets are L11 = L1 = 0.78mH ad C1 = C = 6 μf. These values of iductors adcapacitors are take as oly these were available i the laboratory. Dampig resistace i series with filter capacitor R11 = R1 = 1 Ω ad i parallel with filter iductor R1 = R = 10 Ω. Watt loss i R11 ad R1

4 Iteratioal Joural of Scietific & Egieerig Research Volume 3, Issue 6, Jue-01 4 ISSN becomes 0.5 Watt (from 4 Watt) ad watt loss i R1 ad R is 0. Watt. Total watt loss i iput filter is 0.7 watt. 4 DIODE CLAMP CIRCUIT The overvoltage protectio scheme proposed is a Clamp circuit [6] made up of capacitor coected to all iput ad all output lies through two diodes bridges as show i figure 5. It is operative for all of the 18 IGBTs ad protects the switches from the surge comig from iput AC lie as well as from the surge o the output side that would be otherwise produced wheever a emergecy shut-dow of the coverter is required or commutatio of the switches takig place. Whe the output iductive currets of the motor are iterrupted, the eergy stored i the load is trasferred to the Clamp capacitor ad o critical overvoltage is caused if the capacitor is large eough. Coverter 5 CLAMP CIRCUIT CALCULATIONS Durig fault coditio the iductio machie s rotor adstator iductace stored eergy will act as curret source ad will charge the Clamp capacitor. Equivalet circuit of Diode Clamp circuit (per phase) i cojuctio with the iductio machie is show i figure 7 [6]. IS, Ir ad Im are the motor s per phase stator curret, rotor curret ad magetizig curret respectively. VC is the voltage across Clamp capacitor. Fig. 7 Per phase equivalet circuit of Diode Clamp circuit elimiatig Iductio M/C s shut brach It is assumed that the motor speed remais costat durig Clamp capacitor chargig. Fig. 5 Diode Clamp Circuit Furthermore, the Clamp circuit prevets output voltage spikes caused durig curret commutatio by the lie iductace of the power switch matrix ad by the uavoidable timig iaccuracies. Sice the capacitor voltage icreases at each switchig operatio, some meas to discharge the capacitor is required. A efficiet eergy removal method is to pump back the clamp eergy to power system, but with Diode Bridge circuit it is ot possible. Here we have used a resistor kow as bleeder resistor i parallel with the Clamp capacitor to dissipate the clamp eergy. Iductio Machie Parameters- Slip Rig Iductio Motor, 1 KW, 30 Volts/Phase, 50 Hz, 3 phase, 6.5 Amps, 1400 RPM, Rotor Volts- 40 Volts/Phase, Rotor Amps 10 Amps, Cold resistace of stator = 1.3 Ω /Phase, LS = Lr = 5.88 mh. Total magetic eergy stored i a three phase iductor carryig balaced three phase currets,, is (RMS values)- Q = L (i a +i b +i c )/ = 3LI /4 Where I is the peak value of phase currets. Applyig the same for a three phase iductio motor ad eglectig magetizig brach we have- ΔQ = 3(L s+l r) I /4 = 3LI / Where IS = Ir = I ad LS= Lr = L. Takig a safety factor of 1.5 for curret, we have - ΔQ = (3/) 3 LI Applyig eergy balace equatio - ½ C CV C = ½ C CV C0 + ΔQ Fig. 6 Clamp circuit arragemet for three phase to three phase Matrix ½ C CV C = ½ C CV C0 + (3/) 3 LI

5 Iteratioal Joural of Scietific & Egieerig Research Volume 3, Issue 6, Jue-01 5 ISSN Where V C0 is the iitial voltage of the capacitor Cc is the capacitace value of the Clamp capacitor VC is the fial voltage of C c. Now VC0 = /π = 540. Volts ad allowig Vc to be maximum of 700 Volts, L = 5.88 mh, I = 1.5*6.5 Amps Cc becomes 8.46 μf. Clamp capacitor take as 4 μf/1000 Volts [11]. Bleeder resistace is used to maitai a steady value of voltage across the capacitor depedig o the iput supply voltage. The capacitor voltage may rise above this steady value durig output ope circuit or iput ope circuit coditio. Bleeder resistace gives a path to discharge capacitace up to the steady value after fault coditio subsides. It is importat to ote that diode bridges of both sides of the capacitor do ot allow capacitor to pump back his stored eergy. I our case the value of Bleeder resistor take as 5.5 KΩ correspodig to Clamp Capacitor dischargig time 0.13 secods. The Clamp circuit capacitor curret ad the voltage across it durig commutatio are observed ad are withi limit. The same capacitace value ad bleeder resistace is sufficiet to keep the output voltage spikes withi limitif output opecircuit coditio arises durig Stepless Curret commutatio. No further modificatio is eeded. Fig. 9 V phase load voltage (a) Experimetal result (b) Simulated result i Fig. 10 U phase load curret (a) Experimetal result (b) Simulated result i Fig. 11 V phase load curret (a) Experimetal result (b) Simulated result i 6 CURRENT AND VOLTAGE WAVEFORMS I our study two iput voltage sources are take as 110 Volts ad 110 Volts 10 at 50 Hz ad two phase loads as Load Ω ad 1.89 mh, Load 59.6 Ω ad mh. Switchig Frequecy 7.8 KHz. The ratio of Voltage Trasducer is = 69 ad that of Curret Trasducer is =.56. Fig. 1 R phase source voltage (a) Experimetal result (b) Simulated result i Fig. 8 U phase load voltage (a) Experimetal result (b) Simulated result i Fig. 13 R phase source curret (a) Experimetal result (b) Simulated result i

6 Iteratioal Joural of Scietific & Egieerig Research Volume 3, Issue 6, Jue-01 6 ISSN Fig. 14 S phase source curret (a) Experimetal result (b) Simulated result i Fig. 18 IGBT Module ad Driver Circuits Fig. 15 R phase Voltage waveform at the coverter iput (a) Experimetal (b) Simulated i Fig. 19 Filter Circuit ad Logic Circuit Fig. 16 S phase Voltage waveform at the coverter iput (a) Experimetal (b) Simulated i Fig. 17 Voltage across Clamp capacitor (a) Experimetal (b) Simulated i Fig. 0 Diode Clamp Capacitor Circuit

7 Iteratioal Joural of Scietific & Egieerig Research Volume 3, Issue 6, Jue-01 7 ISSN CONCLUSION Fig. 1 Two phase R-L Loads Stepless Curret commutatio techiques are studied i depth. The reductios of iput short circuit curret, overshoot of voltages ad commutatio itervals are the major objectives of ay commutatio techiques. The commutatio time ca be reduced to miimum possible i Stepless Curret commutatio techique but may cause severe iput short circuit curret. To reduce this short circuit curret, the iput filter is modified accordigly. It limits the iput short circuit curret to a acceptable level ad presece of resistor i parallel with filter iductor elimiates ay voltage spikes to appear just after series filter iductor. The additioal Clamp circuit with two phase to two phase coverters further improves the output voltage ad curret waveforms with reductio i the commutatio time. It is iterestig to ote that most of these passive elemets are usually preset i a Matrix Coverter circuit for filter ad protectio requiremets. Additio of the resistace will add to the commutatio losses but its advatages will outweigh this disadvatage. Ay voltage overshoot i iput ad output of the coverter is further reduced by the presece of Diode Clamp circuit. [3] P.Wheeler, J. Clare, L. Emprigham, M. Blad, M.Apap, Gate Drive level Itelligece ad Curret Sesig for Matrix Coverter curret Commutatio IEEE Tras. Id. Electro, vol. 49, pp , Apr. 00. [4] L.Emprigham, P. W. Wheeler, ad J. C. Clare, Itelliget commutatio of matrix Coverter Bidirectioal switch cells usig ovel gate drive techiques i Proc. IEEE PESC 98, 1998, pp [5] P.wheeler ad D.Grat, Optimizatio iput filter desig ad low-loss switchig techique for a practical matrix coverter IEE Proceedigs of Electric Power Applicatios, vol. 144, o. 1, pp 53-60, Ja [6] Peter Nielse, Frede Blaabjerg, Seior Member, IEEE, ad Joh K. Pederse, Member, IEEE New Protectio Issues of a Matrix Coverter: Desig Cosideratios for Adjust able-speed Drives IEEE Trasactios o Idustry Applicatios, Vol 35, No. 5, September/October 1999 [7] A.Dasgupta, S.Mukherjee, M.Segupta, P.Syam ad A.K.Chattopadhyay Implemetatio of Uiversal Logic System of Geeratig Commutatig Pulses i Matrix Coverters usig FPGAs, IEEE- ICIT06, Mumbai, December 006 (Proceedigs i CDROM), pp [8] Ned Moha, William Robbis ad Tore Udelad, Power Electroics coverters, Applicatios ad Desig Media Ehaced third editio, WILEY INDIA EDITION, 007 [9] Sumata Kumar Show, Idrajit Sarkar, Prasid Syam, Explorig the possibility of Sigle Step Curret Commutatio i a Matrix Coverter NPEC-011, BESU, Shibpur, December 011 [10] Idrajit Sarkar, Sumata Kumar Show, Prasid Syam, Role of Iput Curret Filter to Facilitate Sigle Step Commutatio i Matrix Coverter NPEC-011, BESU, Shibpur, December 011 [11] Idrajit Sarkar, Sumata Kumar Show, Prasid Syam, Role of Diode Clamp Circuit to Facilitate Sigle Step Commutatio i Matrix Coverter NPEC-011, BESU, Shibpur, December 011 [1] Sumata Kumar Show, Sigle Step curret commutatio techique i a Matrix Coverter ME Thesis, Dept. of EE BESU Shibpur, 011 ACKNOWLEDGMENTS Authors are thakful to departmet of Electrical Egieerig, Begal Egieerig ad Sciece Uiversity Shibpur for the ecouragemet ad support i this work. REFERENCES [1] P. Wheeler, J. Rodriguez, J. Clare, L. Emprigham, A. Weistei, Matrix Coverters: A Techology Re view, IEEE Tras. Id. Electro., vol. 49, pp , Apr.00. [] P. Wheeler, J. Clare, L. Emprigham, Ehacemet of matrix coverter Output Waveform Quality Usig Miimized Commutatio Times IEEE Tras. Id. Electro, vol. 51, pp , Feb. 004.