Development of Improved Diode Clamped Multilevel Inverter Using Optimized Selective Harmonic Elimination Technique

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1 Emergig Treds i Electrical, Electroics & Istrumetatio Egieerig: A iteratioal Joural (EEIEJ), Vol, No, August Developmet of Improved Diode Clamped Multilevel Iverter Usig Optimized Selective Harmoic Elimiatio Techique Tariq Kamal, Syed Zulqadar Hassa, Syeda Zahra Naqvi, Imraullah Departmet of Electroics Egieerig Uiversity of Egieerig & Techology Peshawar, Abbottabad Campus,Pakista ABSTRACT I this paper the role of Selective Harmoic Elimiatio (SHE) is preseted for diode clamped twelve-level multilevel iverter (DCMLI) based o dog leg optimizatio algorithm No-liear equatios has bee solved to elimiate specific low order harmoics, usig the developed DOP algorithm, while at the same time the fudametal compoet is retaied efficietly The o-liear ature of trascedetal equatio provide multiple or eve o solutio for a particular modulatio idex The proposed optimizatio method solvig the oliear trascedetal equatios providig all possible solutios The paper also showig the compariso betwee differet modulatio techiques icludig the proposed method The etire system has bee simulated usig MATLAB/Simulik Simulatio results cofirm the effectiveess with egligible THD KEYWORDS DCMLI,SHEPWM, Switchig Agles, DOP, THD I INTRODUTION I power electroics, the developmet of multilevel iverter provide a ew ad alterative optio i high power applicatios The high voltage sharig ability, low electromagetic iterferece (EMI), lower harmoics, made multilevel iverter a very hot area i today s power system ad large motor drives It is ot difficult to develop high voltage iverters with multilevel structure i which voltage are cotrolled, but the mai problem is the harmoic distortio i the output waveform Recetly may modulatio techiques such as SPWM, SVPWM, SHEPWM, etc [] have bee used to address this problem SHEPWM techique ca lower the harmoic cotet of the output curret as well as resoat harmoic I the same maer differet types of multilevel are used for the purpose of reductio i harmoics ad improvemet i power quality [] Cascaded five level multilevel iverter usig DSTATCOM implemeted for power improvemet [] Chopper with flyig capacitor used i DCMLI for the reductio of stress ad produces AC voltage [] The paper [] presets voltage sharig for high power factor loads based o DCMLI(-levels) SVPWM based [] -level diode clamped multilevel level iverter is preseted for leakage curret i PV system -level DCMLI with ANPC, ZCT used for sustaiable eergy [7] Buildig H-Bridge for AC to DC coversio with the use of capacitors ad 7

2 Emergig Treds i Electrical, Electroics & Istrumetatio Egieerig: A iteratioal Joural (EEIEJ), Vol, No, August sigle DC source with less harmoics [] Usig differet voltage balacig equatios ad techiques to form a flyig capacitor H-Bridge multilevel iverter [9] Cascaded iverters with particle swarm optimizatio techique to improve power quality ad reduce total harmoics [] Cascaded iverter usig SVPWM to miimize harmoics ad switchig frequecy [] May multi -level iverters are used but diode clamped multi-level iverter (DCMLI) is employed for may applicatios like power drives & utility system [] I this proposed method diode clamped level iverter is implemeted usig selective harmoic elimiatio pulse width modulatio techique (SHEPWM) to reduce the total harmoic distortio of the output wave form ad improve quality of power Optimizatio techique dog leg is used for switchig agles of IGBTs employed i the system ad the switchig agles are solved by o-liear trascedetal equatios which cotai trigoometric terms Newto- Repsha is used to solve thesetrascedetal equatios II WORKING PRINCIPLE The basic workig priciple block diagram of SHE was show i Figure Table showsthe umber of o ad off switches for differet levels of output voltage i a half cycle (to9 o ) for levels DCMLI s At ay level umber of o switches = (m/)- while each switch is tured o oce at a time DC Supply Three Phase VSI Load Siusoidal PWM Techiques Selective Harmoic Elimiatio Figure Block Diagram of Selective Harmoic Elimiatio The output of DCMLI is a stepped waveforms show i Figure for each step IGBT is switched at a agle such that the total harmoic distortio is reduced To get a desired value of fudametal compoet of voltage ad reduced THD, Selective harmoic elimiatio PWM method is used Selective Harmoic elimiatio (SHEPWM) is used for low switchig frequecy ad removig lower order odd harmoics such as rd, th, 7 th, th ad th This method further uses of iterative optimizatio techique trust regio dogleg algorithms to compute switchig agles ()

3 Emergig Treds i Electrical, Electroics & Istrumetatio Egieerig: A iteratioal Joural (EEIEJ), Vol, No, August Table IGBTs Switchig Patter for DCMLI Stepped Voltages Coductig Switches Vdc Vdc Vdc Vdc No Coductig Switches Figure : Stepped Diode Clamped Multi Level Iverter Output III CALCULATION FOR DOG LEG ALGORITHM Equatios of the output voltage of DCMLI, peak values of harmoics for the calculatio of THD ad the system of o- liear equatios for switchig agles calculatio are derivedd from Fourier series Fourier series for a periodic fuctio is expressed i () f = a + a cos( πf t) + b si( f t) t v o = o () Here a v, a ad b are the Fourier series coefficiets ad f o is the fudametal frequecy (), () & () shows relatioships to determie the values of these coefficiets a v t + T o = T to f ( t) dt () 9

4 Emergig Treds i Electrical, Electroics & Istrumetatio Egieerig: A iteratioal Joural (EEIEJ), Vol, No, August t + T o a = f ( t)cos( fot) dt T () to t + T o b = f ( t)si( fot) dt T () to Where t o = Chose time referece, T = Fudametal period For a sigal havig odd quarter wave Symmetry, Fourier series coefficiets are give as a = a = for all b = v for eve Ad T b = f ( t)si( fot) dt for odd T () The Multilevel iverter has odd quarter wave symmetry Usig Fourier coefficiet equatios of a quarter waves, Fourier coefficiets for a DCMLI output are derived i terms of switchig agles Five agles are cosidered here oly for mathematical calculatios π t b = ω f ( )si( ωt) d( ωt) for odd π π f () o b = ( vdc )si( ωt ) d( ωt) + ( vdc )si( ωt) d( ωt) ( vdc )si( ωt ) d( ωt) ( vdc )si( ωt ) d( ωt) π + + π π π π + ( vdc )si( ωt ) d ( ωt ) (7) π where,,, ad are the switchig agles Solvig Itegratio results π ωt b = f ( )si( ωt) d( ωt) for odd π π f o [ ] [ ] b = vdc cos( ωt) ( v ) cos( ) dc ωt [ ] [ ] ( vdc ) cos( ωt) ( v ) cos( ) dc ωt π ( vdc )[ cos( ωt) ] ( v )[ cos( )] dc ωt ()

5 Emergig Treds i Electrical, Electroics & Istrumetatio Egieerig: A iteratioal Joural (EEIEJ), Vol, No, August = vdc [ cos( ) cos( )] ( vdc )[ cos( ) cos( ) ] + + ( vdc )[ cos( ) cos( )] ( vdc )[ cos( ) cos( ) ] + (9) Where is a odd iteger cos π =, b = v [ cos( ) + cos( ) + cos( ) + cos( ) + cos( )] dc () ()provides peak values of odd harmoics i a DCMLI which ca be used to calculate total harmoic distortio (THD) usig() T H D = v + v + v v v v, v, v v are the peak values of harmoics () Usig resultat theory, a set of o- liear equatios is derived from()which ca is solved for the values of agles I case of twety fourlevelsdcmli, followig set of equatios is obtaied to elimiate odd harmoics upto eleveth level cos( ) + cos( ) + cos( ) + cos( ) = () cos(7 ) + cos(7 ) + cos(7 ) + cos(7 ) = () cos(9 ) + cos(9 ) + cos(9 ) + cos( ) = () cos( ) + cos( ) + cos( ) + cos( ) = () mmπ cos( ) + cos( ) + cos( ) + cos( ) = () M v = (7) v m=(umber of levels/)- Switchig agles are calculated with the help of MATLAB program usig trust regio dogleg algorithm (show i fig) for a rage of modulatio idexes Table agles are calculated usig () is satisfied ( 7 9 ) () Whereisa array cotaiigiitialguessfor + +

6 Emergig Treds i Electrical, Electroics & Istrumetatio Egieerig: A iteratioal Joural (EEIEJ), Vol, No, August Iitial Guess Evaluate F i ( ) Calculate S from Newto & Steepest Decet method such that S r Calculate F i (+S) & revise r No F i (+S) < F(S) Yes is replaced by +S Figure : Proposed Dog Leg Algorithm i= F( ) = [ F ( )] (9) i S is correctio step ad r is radius of trust regio Figure shows the proposed flow chart of trust regio dogleg method for computig + + from set of fuctios f, f, f f I first step, a correctio step is calculated which is added to the iitial guess Dogleg utilizes Newto ad steepest descet methods The combiatio of these two methods esures a fast covergece ad a solutio of fuctio i the steepest descet directio The secod step ivolves fidig the value of trust regio radius to estimate legth of step for the curret iteratio such that the followig coditio is obeyed F ( + s) < F( ) () Third step performs a check the ew values of fuctio Has the fuctio miimized

7 Emergig Treds i Electrical, Electroics & Istrumetatio Egieerig: A iteratioal Joural (EEIEJ), Vol, No, August M Table : Optimized switchig agles i radias for level DCMLI IV IMPLEMENTATION OF LEVEL DCMLI USING SHEPWM level diode clamped multilevel iverter (DCMLI) with four sub-systems coected to DC batteries sources ad switches state cotroller (SSC) is show i figit cosists of specific umber of diodes, switches (IGBT s) ad DC sources The compoets required are calculated usig equatios,, Number of IGBTs = ( ) m / () Number of IGBTs = Number of clampig diodes= {( m / ) }*{( m / ) } () Number of clampig diodes = Number of batteries=( m / ) () Number of batteries =

8 Emergig Treds i Electrical, Electroics & Istrumetatio Egieerig: A iteratioal Joural (EEIEJ), Vol, No, August Figure : Levels DCMLI Figure shows the overall system of DCMLI I figure, & shows the first leg of positive termial of output DC similarly & shows the d leg of egative termial of output DC geerates the cotrol sigals to legs ad cotais the umber of capacitors for multilevel arragemet Figure shows Leg a of levels DCMLI which is coected i series with legb to complete first leg as there are two legs i this system Secod leg is similar to first leg Both first ad secod legs are coected to form a full H-Bridge DCMLI V SIMULATION RESULTS Experimetal results are obtaied for optimized switchig agles usig dog leg method ad for o-optimized IGBTs switchig agles Experimetal results iclude shows

9 Emergig Treds i Electrical, Electroics & Istrumetatio Egieerig: A iteratioal Joural (EEIEJ), Vol, No, August Values of total harmoic distortio Harmoic order of harmoics with referece to fudametal compoet Effect of modulatio idex o THD Figure : THD ad Frequecy spectrum of Level DCMLI o- optimized ad m=9 Figure 7: Voltage Waveform of levels DCMLI with o-optimized agles Figure : THD ad Frequecy spectrum of level DCMLI with optimized agles Figure 9: Voltage Waveform of Level DCMLI levels optimized ad m =7 Figure: THD ad Frequecy spectrum of level DCMLI DCMLI with optimized agles (m=9) Figure :Voltage Waveform of Level optimized ad m =9

10 Emergig Treds i Electrical, Electroics & Istrumetatio Egieerig: A iteratioal Joural (EEIEJ), Vol, No, August Figure : THD ad Frequecy spectrum of Figure :Voltage Waveform of - Level DCMLI -levels DCMLI with optimized agles (m=9) optimized ad m=9 Table shows the THD at differet modulatio idexes ad Figure show that the THD will decrease as modulatio idex icreases 7 M THD Modulatio Idex (M) THD (%age) Table :THD at differet Modulatio idex Figure :Compariso of THD vs Modulatio Idex Table shows a compariso of various techiques employed for -level diode clamped iverter to reduce total harmoic distortio(thd)modulatio techiques like POD-PWM, SPWM, Third harmoic ijectio, offset voltage ad trapezoidal are used but proposed techiquee i this paper improves output voltage waveform with lowest THD value ad power factor value ear to No Modulatio Techique %THD POD-PWM [ ] Trapezoidal [ ] 9 Three harmoic Ijectio [] 77 Third harmoic ijectio [] 7 SPWM [] 97 SPWM [] 7 Offset voltage Proposed Techique (SHEPWM)With Dog Leg Method 97 Table : THD values of -level multilevel diode clamped iverters usig differet modulatios techiques VI CONCLUSION I this paper, SHEPWM strategy is take uder cosideratio for elimiatio of desired low order harmoics The correspodig switches agles for DCMLI is calculated usig dog leg

11 Emergig Treds i Electrical, Electroics & Istrumetatio Egieerig: A iteratioal Joural (EEIEJ), Vol, No, August optimizatio algorithm Udesired harmoics are elimiated to possible maximum limits ad the fudametal voltage is maitaied at desired level, thus resultig the miimum THD The proposed techique ca be applied to ay multilevel iverter cofiguratios ad we ca geeralize this method to ay higher order iverters REFERENCES [] PeddapeliSK, () Recet Advaces i Pulse Width Modulatio Techiques admultilevel Iverters Iteratioal Joural of Electrical, Electroic Sciece ad EgieerigVol No, pp-- 7 [] Hussei H, () Harmoics Elimiatio PWM (HEPWM) Iteratioal Joural of Egieerig Research ad Geeral Sciece Vol, No, pp-7- [] Satyaarayaa, G V R, & Gaesh, S N V, (April ) Cascaded -level iverter typedstatcom for power quality improvemet IStudets' Techology Symposium (TechSym), IEEE (pp -7) [] Shukla, A, Ghosh, A, & Joshi, A, () Flyig-capacitor-based chopper circuit for dc capacitor voltage balacig i diode-clamped multilevel iverter Idustrial Electroics, IEEE Trasactios o, 7(7), pp9- [] Boora, A A, Nami, A, Zare, F, Ghosh, A, &Blaabjerg, F, () Voltage-sharig coverter to supply sigle-phase asymmetrical four-level diode-clamped iverter with high power factor loads Power Electroics, IEEE Trasactios o, (), pp7- [] Cavalcati, M C, Farias, A M, Oliveira, K C, Neves, F A, &Afoso, J L, () Elimiatig leakage currets i eutral poit clamped iverters for photovoltaic systems Idustrial Electroics, IEEE Trasactios o, 9(), pp- [7] Li, J, Liu, J, Boroyevich, D, Mattavelli, P, &Xue, Y, (May, ) Comparative aalysis of threelevel diode eural-poit-clamped ad active eural-poit-clamped zero-curret-trasitio iverters I Power Electroics ad ECCE Asia (ICPE & ECCE), IEEE th Iteratioal Coferece (pp 9-9) [] Du, Z, Tolbert, L M, Ozpieci, B, &Chiasso, J N, (9) Fudametal frequecy switchig strategies of a seve-level hybrid cascaded H-bridge multilevel iverter Power Electroics, IEEE Trasactios o, (), pp- [9] Khazraei, M, Sepahvad, H, Corzie, K A, &Ferdowsi, M, () Active capacitor voltage balacig i sigle-phase flyig-capacitor multilevel power coverters Idustrial Electroics, IEEE Trasactios o, 9(), pp79-77 [] Rodriguez, J C, & P Mora, L, () A vector cotrol techique for medium voltage multilevel iverters Applied Power Electroics Coferece ad Expositio, APEC [] J Rodriguez, J S Lai, ad F Z Peg, () Multilevel iverters: A survey of topologies, cotrols, ad applicatios IEEE Tras Id Electro, Vol9, o, pp 7 7 [] Chaturvedi R,() A Sigle Phase Diode Clamped Multilevel Iverter ad its Switchig Fuctio Joural of Iovative treds i Sciece, Pharmacy & Techology Vol-(),pp- [] Haskar Reddy, V N,Babu, C S & Suresh, K, () Advaced Modulatig Techiques for Diode Clamped Multilevel Iverter Fed Iductio Motor Vol, No,pp 9-99 [] Zheg, X, Sog, L, & Hogyig, P, Study of Five-level diodes-clamped Iverter Modulatio Techology Based o Three-harmoic Ijectio Method d Iteratioal Coferece o Electroic & Mechaical Egieerig ad Iformatio Techology [] KedareswarM, () Reductio of THD i Diode Clamped Multilevel Iverter employig SPWM techique Iteratioal Joural of Scietific ad Research Publicatios, Vol, No, pp- 7

Emergig Treds i Electrical, Electroics & Istrumetatio Egieerig: A iteratioal Joural (EEIEJ), Vol, No, August AUTHORS Tariq Kamal, received his BSc degree i Electroic Egieerig from Uiversity of

a Lecturer i Uiversity of Egieerig ad Techology (UET) Abbottabad Campus His mai research is i the area of power system stability, applicatio of adaptive itelliget cotrols, power electroics ad

of KPK Curretly his MSc (Electrical Egieerig Power & Cotrol) is likely to be completed from Comsats Istitute of Iformatio Techology, Abbottabad Campus ad recetly also performig the duties of Lecturer

12 Emergig Treds i Electrical, Electroics & Istrumetatio Egieerig: A iteratioal Joural (EEIEJ), Vol, No, August AUTHORS Tariq Kamal, received his BSc degree i Electroic Egieerig from Uiversity of Egieerig ad Techology (UET) Peshawar, Pakista i He is curretly i Comsats istitute of iformatio Techology Abbottabad Campus pursuig his Master degree i Electrical Power ad Cotrol Egieerig ad actig as a Lecturer i Uiversity of Egieerig ad Techology (UET) Abbottabad Campus His mai research is i the area of power system stability, applicatio of adaptive itelliget cotrols, power electroics ad electrical Machie drives Syed Zulqadar Hassa, has received his BSc (Electroics Egieerig) from Uiversity of Egieerig ad Techology, Peshawar i with securig a Gold Medal ad also got award from Goveror of KPK Curretly his MSc (Electrical Egieerig Power & Cotrol) is likely to be completed from Comsats Istitute of Iformatio Techology, Abbottabad Campus ad recetly also performig the duties of Lecturer i Uiversity of Egieerig ad Techology (UET) Abbottabad Campus His mai research focuses o the area of Fuzzy Based Cotroller Desig ad Power Electroics Cotrol Syeda Zahra Naqvi, received her BSc (Electroics Egieerig) from Uiversity of Egieerig ad Techology, Peshawar i Curretly she is egaged i doig MSc (Electrical Egieerig Power & Cotrol) form Comsats Istitute of Iformatio Techology, Abbottabad Campus Her mai research is i the area of Power System ad Power Electroics Cotrol Imraullah, received his BSc degree i Electroic Egieerig from Uiversity of Egieerig ad Techology (UET) Peshawar, Pakista i He is curretly i Uiversity of Egieerig & Techology Taxila pursuig his Master degree i Cotrol Egieerig His mai research is i the area of Cotrol stability, Power electroic Cotrol system

SEVEN-LEVEL THREE PHASE CASCADED H-BRIDGE INVERTER WITH A SINGLE DC SOURCE

SEVEN-LEVEL THREE PHASE CASCADED H-BRIDGE INVERTER WITH A SINGLE DC SOURCE T. Porselvi 1 ad Ragaath Muthu 1 Sri Sairam Egieerig College, Cheai, Idia SSN College of Egieerig, Cheai, Idia E-Mail: tporselvi@yahoo.com