A Synchronization Method for Single-Phase Grid-Tied Inverters Hadjidemetriou, Lenos; Kyriakides, Elias; Yang, Yongheng; Blaabjerg, Frede

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1 Aalborg Uiversitet A Sychroizatio Method for Sigle-Phase Grid-ied Iverters Hadjidemetriou, Leos; Kyriakides, Elias; Yag, Yogheg; Blaabjerg, Frede Published i: IEEE rasactios o Power Electroics DOI (lik to publicatio from Publisher):.9/PEL Publicatio date: 6 Documet ersio Early versio, also kow as pre-prit Lik to publicatio from Aalborg Uiversity Citatio for published versio (APA): Hadjidemetriou, L., Kyriakides, E., Yag, Y., & Blaabjerg, F. (6). A Sychroizatio Method for Sigle-Phase Grid-ied Iverters. IEEE rasactios o Power Electroics, 3(3), Geeral rights Copyright ad moral rights for the publicatios made accessible i the public portal are retaied by the authors ad/or other copyright owers ad it is a coditio of accessig publicatios that users recogise ad abide by the legal requiremets associated with these rights.? Users may dowload ad prit oe copy of ay publicatio from the public portal for the purpose of private study or research.? You may ot further distribute the material or use it for ay profit-makig activity or commercial gai? You may freely distribute the URL idetifyig the publicatio i the public portal? ake dow policy If you believe that this documet breaches copyright please cotact us at vb@aub.aau.dk providig details, ad we will remove access to the work immediately ad ivestigate your claim. Dowloaded from vb.aau.dk o: ovember 5, 8

2 his article has bee accepted for publicatio i a future issue of this joural, but has ot bee fully edited. Cotet may chage prior to fial publicatio. Citatio iformatio: DOI.9/PEL , IEEE rasactios o Power Electroics IEEE RANSACIONS ON POWER ELECRONICS A Sychroizatio Method for Sigle-Phase Grid-ied Iverters Leos Hadjidemetriou, Graduate Studet Member, IEEE, Elias Kyriakides, Seior Member, IEEE, Yogheg Yag, Member, IEEE ad Frede Blaabjerg, Fellow, IEEE Abstract he cotrollers of sigle-phase grid-tied iverters require improvemets to eable distributio geeratio systems to meet the grid codes/stadards with respect to power quality ad the fault ride through capability. I that case, the respose of the selected sychroizatio techique is crucial for the performace of the etire grid-tied iverter. I this paper, a ew sychroizatio method with good dyamics ad high accuracy uder a highly distorted voltage is proposed. his method uses a Multi-Harmoic Decouplig Cell (MHDC), which thus ca cacel out the oscillatios o the sychroizatio sigals due to the harmoic voltage distortio while maitaiig the dyamic respose of the sychroizatio. herefore, the accurate ad dyamic respose of the proposed MHDC-PLL ca be beeficial for the performace of the whole sigle-phase grid-tied iverter. Idex erms Harmoic distortio, iverters, phase-locked loops, photovoltaic systems, power system faults, power quality. I. INRODUCION INGLE-phase iverters are used for covertig direct Scurret (DC) ito alteratig curret (AC). Several gridtied applicatios require the coversio of DC power ito AC, such as battery storage systems, uiterruptible power supply systems, distributed geeratio (DG) uits, ad photovoltaic systems. Sigle-phase iverters are widely used as Grid Side Coverters (GSC) that covert the power from the DC-bus ad properly iject this power ito the grid, with which the ijected curret has to be sychroized. I additio, the itegratio of DG eergy ito the power grid has to follow the moder grid codes []-[5], which require a ijectio of high quality power i the ormal operatio mode []-[6]. Furthermore, the Fault Ride hrough (FR) capability by the GSC is becomig ecessary, eve i small sigle-phase systems, as it is observed i recet studies i Japa [3] ad the Italia techical rules issued i [4]. Hece, the GSC should achieve a accurate ad fast respose to iject sychroized grid currets of high power quality, ad also provide voltage ad frequecy support immediately whe a grid fault occurs. Cosequetly, the sychroizatio method ad cotrol Mauscript received July, 4; revised November 8, 4 ad February 8, 5; accepted April 7, 5. Date of curret versio April 3, 5. his work was supported by the Research Promotio Foudatio (RPF, Cyprus, Project KOINA/SOLAR-ERA.NE/4/), by Eergiet.dk (ForskEL, Demark) ad the SOLAR-ERA.NE (Europea Uio s Seveth Framework Programme). L. Hadjidemetriou ad E. Kyriakides are with the KIOS Research Ceter for Itelliget Systems ad Networks ad the Departmet of Electrical ad Computer Egieerig, Uiversity of Cyprus, 678 Nicosia, Cyprus ( hadjidemetriou.leos@ucy.ac.cy; kyriakides@ieee.org). Y. Yag ad F. Blaabjerg is with the Departmet of Eergy echology, Aalborg Uiversity, DK-9 Aalborg, Demark ( yoy@et.aau.dk; fbl@et.aau.dk). techiques for sigle-phase GSCs should be ehaced to meet these striget but essetial demads. A typical sigle-stage sigle-phase iverter is show i Fig.. For this system, the cotrol of the GSC is based o the PQ cotroller which geerates the referece currets, ad the curret cotroller which holds the resposibility for a appropriate curret ijectio as described i [5], [7]-[]. he PQ cotroller ca be implemeted i the statioary or sychroous referece frame as a closed-loop or a ope-loop cotroller. hus, a Proportioal-Resoat (PR) cotroller i the statioary referece frame or a Proportioal-Itegral (PI) cotroller i the sychroous referece frame ca be adopted as the curret cotroller. Sice the ijected curret has to be sychroized with the grid voltage, the respose of both cotrollers will be affected by the performace of the sychroizatio method. Amog a large umber of reported sychroizatio techiques, Phase-Locked Loop (PLL) algorithms have become the most widely used solutios. Hece, PLL based sychroizatio methods i sigle-phase P systems require further improvemet as depicted i [3]-[5] to esure a proper operatio of the P systems as aforemetioed. With respect to the PLL sychroizatio, a commo PLL based techique to estimate the phase agle (θ) of the grid voltage (v s ) i sigle-phase systems is eabled by geeratig a quadrature voltage vector i the statioary referece frame (v ). he, this vector is trasformed ito the sychroous referece frame (v ), where a simple PI cotroller regulates the voltage v q to zero ad therefore the phase agle is extracted [5]-[6]. I each PLL techique, a differet Quadrature Sigal Geerator (QSG) is used to geerate the Power from DC-Bus DC-bus P * Q * DC GSC AC PWM modulatio s ref Curret Cotroller (PR + aβ-frame) or (PI + -frame) I * PQ Cotroller Geeratio of Referece Currets LCL Filter I s s PCC Low oltage Fault L grid Sychroizatio Uit (MHDC-PLL) θ, v Fig.. Cotrol structure of a sigle-phase grid-tied iverter. L if L gf C f Power Grid grid with harmoic distortio (c) 5 IEEE. Persoal use is permitted, but republicatio/redistributio requires IEEE permissio. See for more iformatio.

3 his article has bee accepted for publicatio i a future issue of this joural, but has ot bee fully edited. Cotet may chage prior to fial publicatio. Citatio iformatio: DOI.9/PEL , IEEE rasactios o Power Electroics IEEE RANSACIONS ON POWER ELECRONICS vector v. A straightforward /4 delay trasport techique is used i [5], [5]-[6] as a QSG, where is the fudametal period of the grid voltage. Iaccuracy i the case of low or high order harmoics is the mai drawback of this PLL system due to the lack of filterig. I cotrast, the Iverse Park rasform (IP) based PLL method [6]-[7] ca filter high frequecy harmoics. Moreover, some iterestig techiques based o adaptive filterig ad geeralized itegrators, such as the ehaced PLL ad a Secod Order Geeralized Itegrator (SOGI) based PLL are preseted i [5]-[6], [8]-[], which preset similar filterig respose with the IP-PLL, where, however, the low frequecy harmoics are ot elimiated. Fially, [] preset a Hilbert based PLL techique. he harmoics effect is elimiated by this method, but ufortuately, it has practical implemetatio problems i the case of a real-time applicatio with time-depedet sigals. More advaced PLL techiques have bee preseted i the recet literature, which eable the robustess of the sychroizatio agaist low-order harmoics. hose techiques are based o adaptive or otch filters []-[3], or applied repetitive ad multi resoat cotrollers o the PLL ad/or the curret cotroller [4]-[5] of the P system. Although these techiques achieve to overcome the harmoics effect, the dyamic respose of the sychroizatio is slightly affected. herefore, the harmoic robustess comes at the expese of performace deceleratio of the P system, which is udesired, especially i the case of grid faults. I light of the above issues, this paper presets a ovel PLL-based sychroizatio method, which ca achieve accurate ad dyamic sychroizatio performace uder several grid voltage disturbaces ad also whe the distributio grid cotais both low- ad high-order harmoics. he QSG of the proposed method is preseted i Sectio II.A ad it is based o a combiatio of a IP ad a /4 delay trasportatio to atteuate the high-order harmoics. he, a ew Multi-Harmoic Decouplig Cell (MHDC) is proposed i Sectio II.B, which is desiged i multiple sychroous referece frames to dyamically cacel out the oscillatios due to low-order harmoics of the grid voltage. A thorough theoretical aalysis of the proposed MHDC has bee performed i Sectio II.C, provig its immuity to low-order harmoics while maitaiig fast dyamics. he desiged MHDC has a recursive filterig characteristic with a fast dyamic respose similar to the decouplig etworks preseted i [6]-[3] for three-phase systems ad thus, the proposed MHDC-PLL, as preseted i Sectio II.D, ca eable a fast cacellatio of both low- ad high-order harmoic oscillatios. he accurate ad dyamic respose of the proposed MHDC-PLL has bee verified through simulatio ad experimets i Sectio III. he performace of the proposed sychroizatio has bee tested uder several grid coditios ad uder several grid disturbaces. he proposed MHDC-PLL is a ideal sychroizatio method for grid-tied iverter applicatios due to the high immuity agaist voltage harmoic distortio ad the fast dyamic respose uder grid disturbaces. II. PROPOSED SYNCHRONIZAION MEHOD he proposed sychroizatio is based o three modules: v s Quadrature Sigal Geerator (QSG) Iverse Park rasformatio ( d order BPF to atteuates high-order harmoics) vβ vα vβ θ θ v d v q v d v q LPF LPF the QSG, the MHDC ad the -PLL algorithm. he QSG geerates the quadrature voltage vector (v ) ad filters the high-order harmoics of the voltage. he MHDC module achieves the fast ad accurate decouplig of the fudametal voltage vector from the oscillatios caused by the low-order harmoics. Fially, the almost harmoic-free voltage sigal is used by the -PLL techique to extract the voltage phase. A. Quadrature Sigal Geerator (QSG) he QSG used i the proposed sychroizatio is a combiatio of a IP [5], [6]-[7], which ca be cosidered as a bad pass filter, ad a /4 delay trasportatio [5]-[6] as it is show i Fig.. he voltage (v α ) is produced by usig oe forward ad oe iverse Park trasformatio ad two first-order Low Pass Filters (LPFs), as show i Fig.. he forward ad iverse Park trasformatio ca be achieved by settig the -m equal to + ad - respectively i () ad the trasfer fuctio of the LPFs is preseted i (). cos( m) ω t si( m) ω t m () si( m) ω t cos( m) ω t ωf v v s ω () f Delay /4 /4 Delay Sigal ω is the estimated frequecy by the PLL ad ω f is the cutoff frequecy of the LPF. I order to derive the trasfer fuctio of the IP, it is ecessary to express () i terms of the Euler formula as show below. j( m) ω t j( m) ω t j( m) ω t j( m) ω t e e je e ( ) ( ) ( ) ( ) je e e e m j m ω t j m ω t j m ω t j m ω t (3) Now, by usig the Laplace property for frequecy shiftig (e at = F(s a)), the voltage vectors v ad v ca be expressed i the complex-frequecy domai as show i (4) ad (5), respectively. vs( s jω ) vs( s jω ) j vβ ( s jω ) vβ ( s jω ) s s β β vd vq j v ( s jω ) v ( s jω ) v ( s jω ) v ( s jω ) (4) v ( ) ( ) ( ) ( ) α vd s jω vd s jω j vq s jω vq s jω vβ jvd ( s jω ) vd ( s jω ) vq ( s jω ) vq ( s jω ) (5) he trasfer fuctios v a /v s ad v β /v s ca be derived as show i (6) ad (7) respectively, by substitutig (4) ito () ad the () ito (5). v a v v β a jv Fig.. he structure of the quadrature sigal geerator (QSG) that is used i the proposed MHDC-PLL. a v aβ (c) 5 IEEE. Persoal use is permitted, but republicatio/redistributio requires IEEE permissio. See for more iformatio.

4 his article has bee accepted for publicatio i a future issue of this joural, but has ot bee fully edited. Cotet may chage prior to fial publicatio. Citatio iformatio: DOI.9/PEL , IEEE rasactios o Power Electroics IEEE RANSACIONS ON POWER ELECRONICS 3 va skω v s s k ω ω s v β ω ; f k k ω ; ω ω k ω (7) vs s s k ω ω he secod-order trasfer fuctios of (6) ad (7) represet a bad-pass ad a low-pass filter respectively. herefore, for optimally damped secod-order filters, the factor k is set to ad therefore, ω f is set to π f N rad/s sice ω represets the estimatio of the operatig agular frequecy of the grid (ormally at π f N rad/s). f N is the omial system frequecy (5 or 6 Hz). he trasfer fuctio i (6) is actually a secodorder bad pass filter, which atteuates the zero-frequecy (DC offset) ad the high-order frequecy harmoics without affectig the amplitude ad phase agle of the fudametal voltage at the omial frequecy, as it ca be observed by the Bode diagram show i Fig. 4 of sectio II.C. he geerated voltage v β is a 9 o -shifted voltage with respect to the measured voltage v s accordig to (7), but v α ad v β preset differet harmoic atteuatio to the grid voltage due to the differet filterig capability of (6) ad (7). Distiguished from the IP-PLL, the use of v β is avoided i the proposed PLL, sice the differet harmoic filterig effects of v α ad v β require a more complicated desig for the MHDC. Istead, i the proposed QSG, the geeratio of the quadrature sigal v is obtaied by the /4 delay trasportatio of the filtered v α as show i Fig., which makes the voltages v α ad v β to preset idetical low order harmoic distortios. herefore, the trasfer fuctio of the proposed QSG is give by cosiderig that v α =v α ad v β =-jv α i (6). B. Multi Harmoic Decouplig Cell (MHDC) he voltage vector v =[v α v β ] is free of ay zero or high frequecy oscillatios due to the QSG. he QSG acts as a secod-order low-pass filter, but the low-order harmoics remai i the i-quadrature voltages. I order to cacel out the oscillatios caused by the low-order harmoic through the proposed MHDC, a comprehesive aalysis of the iquadrature voltages is coducted as followig. Sice the v β is /4 delayed from v α, the v ca be expressed as a summatio of the fudametal compoet (=) ad the low-order odd harmoics (=3, 5, 7, 9,...), cos( ωt θ cos( ) ) ωt θ v Τ Τ cos( ω( t ) θ) 3,5, 7,9,... cos ω( t ) θ 4 4 cos( ωt θ) cos( ωt θ) v π π cos( ωt θ) 3,5, 7,9,... cos( ωt θ) (8) where ad θ represet the amplitude ad the iitial phase agle respectively of the correspodig voltage compoet. he voltage vector of (8) ca be rewritte as show i (9), where the summatio of the harmoics ca be divided ito two groups accordig to the harmoic-order (i.e., 4l- ad 4l+ with l beig,, 3, ). f (6) cos( ωt θ ) vα cos( ωt θ ) v 3π vβ siωt θ 3,7,.. cos ωt θ (9) cos( ωt θ) π 5,9,3.. cos ωt θ Usig basic trigoometric idetities, (9) ca be expressed as (), where it is clear that the sig of the agular speed of each compoet depeds o the harmoic order (i.e., 4l ± ). cos( ωt θ) cos( ωt θ) v si ωt θ 3,7,.. siωt θ () cos( ωt θ) 5,9,3.. siωt θ herefore, the voltage vector v ca be expressed by (), i which sg() defies the speed directio of each harmoic compoet. v cos (sg( ) α cos( ωt θ) ωt θ vβ si ωt θ 3,5, si (sg( ) ωt θ 7,9,.. () π for,5,9,... where sg( ) si for 3,7,,... he voltage vector v ca the be traslated ito ay th sychroous referece frame ( sg() -frame) with a rotatig speed equal to. sg(). ω, where ω is the fudametal agular frequecy. he voltage vector expressed to the sg() -frame (v sg()) ca be calculated by multiplyig the v with the trasformatio matrix [ sg()] of () as show i (). he voltage vector v sg() i () cotais a oscillatio-free term, which is actually the voltage compoet sg() rotatig at the correspodig sychroous sg().. ω speed. m Furthermore, it cotais some oscillatio terms ( sg() = m [ sg()-m sg(m)] m sg(m) ) based o the effect of the rest of the voltage compoets. v d cossg( ) θ v sg( ) sg( ) v v q sisg( ) θ m sg( ) sg( ) sg( ) msg( m) msg( m) m Oscilatios Oscilatio erms free term m cos( θm) sg( ) msg( m) m s i( θm) v () o eable the desig of the proposed MHDC, the voltage vector should be expressed i all referece frames of the existig frequecy compoets. Sice the QSG has elimiated the effect of high frequecy harmoics (as it behaves like a secod-order low-pass filter), the proposed method oly deals with the effect of the four most sigificat low-order harmoics. herefore, the voltage vector should be expressed i the fudametal (+) ad the most sigificat harmoics (+3, +5, +7, +9) referece frames as show i (3), where Z represets a x zero matrix (c) 5 IEEE. Persoal use is permitted, but republicatio/redistributio requires IEEE permissio. See for more iformatio.

5 his article has bee accepted for publicatio i a future issue of this joural, but has ot bee fully edited. Cotet may chage prior to fial publicatio. Citatio iformatio: DOI.9/PEL , IEEE rasactios o Power Electroics IEEE RANSACIONS ON POWER ELECRONICS 4 v v 3 v v ( 3) ( 9) Z ( ) Z 3 ( + 9) (3) ( ) 9 ( 3) Z Now, the estimatio of the oscillatio-free terms of each harmoic compoet sg() is achieved, by subtractig all m the oscillatio terms [ sg()-m sg(m)] m sg(m) from each voltage vector v as show i (4). A LPF [F(s)] (as defied i (6)) is the used to elimiate ay remaiig oscillatios. * * 3 * [ F( s)] v v 3 v 9 * Z ( 3) ( + 9) * 3 3 ( ) 3 ( + 9) (4) 3 9 ( ) 9 ( 3) Z * 9 9 Fially, (4) ca be rewritte as (5), which is the mai equatio of the proposed MHDC. sg( ) * ( ) *( ) sg( ) [ ( )] [ ( )] sg( ) F s F s v *( m) sg( ) msg( m) msg( m) m aβ (5) ω f s ωf where [ Fs ( )] ω (6) f s ωf he desig parameter ω f is defied i Sectio II.C as a result of the theoretical aalysis of the MHDC. he block diagram of the proposed MHDC is represeted i Fig. 3. he multiple uses of (5) as a cross-feedback etwork i the MHDC (oce for fudametal ad each harmoic compoet) ca elimiate the cross-couplig effects ad ca achieve a geeratio of the oscillatio-free sigal *+, which the ca be used for a accurate sychroizatio. MHDC-PLL v s Delay /4 QSG Iverse Park rasformatio v a v β v θ * -PLL v d = + s Multi-Harmoic Decouplig Cell (MHDC) ω om v q Δω PI + + ω θ mod π s * ( ) sg( ) [ ( )] sg( ) F s v Multiple use of equatio (5) aβ *( m) sg( ) msg( m) msg( m) m Fig. 3. Block diagram of the proposed MHDC-PLL. π Fudametal * * Fs () *( m) msg( m) Fs () Low-order Harmoics f C. heoretical Aalysis of the Proposed MHDC Α extesive theoretical aalysis is required to defie the trasfer fuctio, the expected respose, ad the optimal desig parameters of the proposed MHDC. he estimated vector + + is cosidered as the output of the MHDC ad ca be fed ito ay covetioal PLL to accurately estimate the phase agle of the fudametal voltage. herefore, accordig to (5) ad the block diagram of the MHDC as preseted i Fig. 3, + + ca be expressed as, * () *( m) vaβ sg( ) m sg( m ) m sg( m ) m (7) A expasio of (7) cosiderig the odd harmoics up to order ie is give by, * () *(3) *(5) *(7) *(9) v *() *(5) v 3 4 [ ( )] F s 8 5 v 4 [ ( )] F s *(7) *(9) *() *(3) v 5 4 [ F( s)] [ F( s)] *(7) *(9) *() *(3) v 7 8 [ F( s)] [ F( s)] *(5) *(9) *() *(3) v 9 8 [ F( s)] 3 8 [ F( s)] *(5) *(7) (8) For expressig the last three terms i each parethesis of (8) i terms of + +, three or more filters [F(s)] are required due to the recursive character of the MHDC. hus, due to their slower dyamics, these terms ca be igored for simplicity i the further aalysis. Moreover, for a better observatio of the (+) MHDC respose, the fudametal term + should be expressed i the equivalet statioary referece frame (frame) as + by multiplyig both sides of (8) with -. he, the remaiig terms i the parethesis ca be expressed i terms of + ad v by usig the Park s trasformatio of (). herefore, (8) ca be expressed as show below. * () *() * () 3 [ ( )] 3 3 [ ( )] * () 5 [ ( )] 5 5 [ ( )] F s v F s * () 7 [ F( s)] 7 v 7 [ F( s)] * () 9 [ F( s)] 7 9 [ ( )] v F s v F s v F s (9) Now, the trasfer fuctio of -h [F(s)] +h, where h is the correspodig harmoic order, ca be defied i the (c) 5 IEEE. Persoal use is permitted, but republicatio/redistributio requires IEEE permissio. See for more iformatio.

6 his article has bee accepted for publicatio i a future issue of this joural, but has ot bee fully edited. Cotet may chage prior to fial publicatio. Citatio iformatio: DOI.9/PEL , IEEE rasactios o Power Electroics IEEE RANSACIONS ON POWER ELECRONICS 5 Gai (db) Phase (º) complex-frequecy domai as show i (), by usig a legthy mathematical aalysis (similar to the oe preseted i Sectio II.A). his aalysis is based o the Park s rasformatios i terms of the Euler formula as defied i (3), o the Laplace property for frequecy shiftig (e at = F(s a)), ad o the fact that v b =-j. v a as show i Sectio II.A. herefore, the aalysis cocludes ito the complex firstorder trasfer fuctio: ωf for h 3, 7 s ( ωf j h ω ) Fh h [ F( s)] h ωf for h, 5,9 s ( ωf j h ω ) () hus, substitutig F h = -h [F(s)] +h of () ito (9) yields, * () * () v F F F F v F () Fially, the trasfer fuctio of the MHDC ca be derived as, * () F 3 F 5 F 7 F 9 () v F F F F F If the correspodig F h terms of () are substituted accordig to (), the the eleveth-order complex trasfer fuctio of the proposed MHDC ca be extracted. he v cosists of the iput voltage vector of the MHDC (as is calculated from the QSG) ad *(+) = - is the + equivalet output of the MHDC expressed i the statioary referece frame. For developig the proposed MHDC-PLL, the QSG proposed i Sectio II.A will be coected i series with the proposed MHDC i order to dyamically extract the fudametal compoet of the grid voltage as show i Fig. 3 ad the a simple PLL algorithm will be used i order to extract the phase agle. hus, the trasfer fuctio of QSG i series with the MHDC ca be defied as the multiplicatio of the trasfer fuctio of (6) ad (): *() *() *() *() α v α α β vβ β, v s v s v α v s v (3) s v β herefore, i order to ivestigate the respose of the proposed PLL ad also to desig the parameter ω f of the proposed MHDC, the Bode diagrams i terms of voltage v a of the QSG, the proposed MHDC, ad the series combiatio of the two are preseted i Fig. 4. he results for v β are similar with a 9 o -delay o the output sigal. he results of Fig. 4 verify that the proposed MHDC accordig to () does ot affect the dyamic estimatio of the amplitude ad the phase agle of the fudametal voltage compoet at 5 Hz. Furthermore, the MHDC ca effectively elimiate the loworder harmoic compoets cosidered i the decouplig etwork, but it caot affect the high order harmoics. he third ad seveth harmoics are preseted as egative frequecy harmoics i the Bode diagram accordig to the costructio of the voltage vector v as explaied i Sectio II.B. he Bode diagram regardig the QSG is actually a bad (+) MHDC+QSG QSG MHDC Frequecy (Hz) Fig. 4. Bode diagram of the proposed QSG, MHDC, ad the series combiatio of the two. pass secod-order filter accordig to (6) as metioed i Sectio II.A, which ca elimiate the effect of the zero- ad high-order harmoics. he series combiatio of the proposed QSG ad MHDC (QSG+MHDC) represet the respose of the proposed PLL accordig to (3). As it ca be observed i the Bode diagram, the QSG+MHDC iherits the beefits of both uits ad therefore, the desired accurate respose ca be achieved sice the low-order harmoics are completely elimiated by the MHDC ad the zero- ad high-order harmoics are miimized by the QSG. Furthermore, a dyamic respose ca be guarateed sice the MHDC decouples the effect of the low-order harmoics without affectig the dyamics of the estimatio. he desig parameter ω f ca affect the quality factor of the filter, the oscillatio dampig, ad the time performace of the proposed MHDC. herefore, a ivestigatio through simulatio results shows that a reasoable trade-off ca be achieved by settig ω f = ω 3.where ω is the omial agular frequecy of the grid at π 5 rad/s. For ω f <ω 3 the respose of the MHDC ca preset some uwated oscillatios ad for ω f >ω 3 the respose of the MHDC is overdamped. he step respose regardig the estimatio of the iput voltage accordig to QSG + MHDC of the proposed PLL is preseted i Fig. 5. he respose of QSG+MHDC is preseted i Fig. 5(a) for a step siusoidal iput i the fudametal frequecy. he results verify the fast dyamic respose of the proposed PLL sice the iput voltage is estimated with a settlig time less tha.4 s. Fig. 5(b) presets the step respose for a siusoidal step iput with a 5% amplitude i the frequecy of the fifth harmoic. he results show a immediate ad complete elimiatio of the harmoic. D. PLL Algorithm Desiged i the Sychroous Referece Frame (-PLL) he produced voltage vector *+ + by the MHDC is free of ay harmoic oscillatios as discussed i Sectio II.C ad ca be cosidered as a good approximatio of the fudametal (c) 5 IEEE. Persoal use is permitted, but republicatio/redistributio requires IEEE permissio. See for more iformatio.

7 his article has bee accepted for publicatio i a future issue of this joural, but has ot bee fully edited. Cotet may chage prior to fial publicatio. Citatio iformatio: DOI.9/PEL , IEEE rasactios o Power Electroics IEEE RANSACIONS ON POWER ELECRONICS 6 (pu) (pu) (a) Step respose for a siusoidal iput i the fudametal frequecy (b) Step respose for a siusoidal iput i the fifth harmoic frequecy * v v.5 =u(t)cos(5t) time (s) Fig. 5. he step respose of the series combiatio of the QSG ad the MHDC. compoet of the grid voltage expressed i the + -frame as show below, θ v * cosθ siθ cosθ cos( θ θ ) siθ cosθ cos( θ Τ 4) si( θ θ ) Δθ (4) where θ is the estimated phase agle by the proposed PLL ad θ is the real phase agle of the fudametal compoet of the grid voltage. Sice the error Δθ=θ-θ is very small i steady state, the *+ q + ca be assumed as a liearized approximatio of Δθ as show i (4). herefore, the estimated *+ d + represets the amplitude of the grid voltage ad the *+ q + ca be cosidered by a simple PLL algorithm, such as the -PLL, i order to lock the phase agle of the grid voltage as show i Fig. 3. he structure of the -PLL is preseted i Fig. 3, where a PI cotroller is used i the sychroous referece frame to extract the phase agle of the fudametal voltage. he tuig process of such a PLL is based o the liearized small sigal aalysis of the PLL as preseted i [5], [6]-[3]. I the case that the trasfer fuctio of the PI cotroller is give by K p +/(. i s), the closed-loop trasfer fuctio of the PLL ca be simplified to the secod order trasfer fuctio of (5) whe the PLL is desiged for a per uit voltage. he tuig parameters k p ad i ca be calculated accordig to (6), where ζ should be set to for a optimally damped PLL respose ad the Settlig ime (S) for the MHDC-PLL has bee set to ms. k p s θ i θ s k (5) p s 9. where k p ad i.47 ζ S (6) S o sum up, the proposed MHDC-PLL cosists of three mai modules: the proposed QSG i Sectio II.A, the MHDC as proposed i Sectio II.B, ad the PLL algorithm of Sectio II.D. he structure of the ew MHDC-PLL with all the v * i v =u(t)cos(t) ABLE I PARAMEERS FOR HE EXPERIMENAL SEUP Nomial coditios N=3 rms, f N=5 Hz, S N= ka, P=4 Samplig ad PWM f SAMPLING = f PWM = khz Desig guidelies for the MHDC-PLL k P=9, I=.35 ω f=π5 rad/s, ω f=π5/3 rad/s LCL filter L if =3.6 mh, C f =.35 μf, L gf = 4 mh Hardware i the loop DS3 dspace DC Source Delta Elektroika SM 6- AC Source Califoria Istrumet MX-3 Iverter Semikro SEMIeach (B6CI) modules is preseted i Fig. 3 ad the desiged parameters for the MHDC-PLL are preseted i able I. he proposed sychroizatio techique ca achieve a accurate ad dyamic respose uder distorted voltage ad uder ay grid disturbaces as demostrated i Sectio III. he accuracy ad the fast performace of the proposed PLL ca potetially affect the respose of the GSC cotroller ad as a result, the performace of the whole grid-tied iverter i terms of power quality ad i terms of fast FR operatios. III. SIMULAION AND EXPERIMENAL RESULS he performace of the proposed PLL requires verificatio through simulatio ad experimetal results. herefore, a experimetal setup ad a idetical simulatio model (i MALAB/Simulik) have bee implemeted accordig to the structure of the sigle-phase grid-tied iverter as preseted i Fig.. All the parameters of the implemeted experimetal setup are listed i able I. he proposed sychroizatio method claims a outstadig performace i terms of accuracy uder harmoic distorted grid voltage. herefore, the proper respose of the MHDC-PLL should be tested uder harmoic distorted voltage ad uder other several grid voltage disturbaces, such as phase jump, voltage sag, ad frequecy variatio. he simulatio results for the respose of the two PLLs (SOGI-PLL [5]-[6] ad proposed MHDC-PLL with the same tuig parameters accordig to able I) are preseted i Fig. 6 uder several voltage coditios. he voltage at the begiig of the simulatio is purely siusoidal. A sigificat low-order voltage harmoic distortio (HD =.93%) is ijected by the grid at t =.3 s with 5 =% ad 7 =% relative to the fudametal ad.75% of high-order harmoics. It is clearly observed i Fig. 6 that, for low-order harmoic distorted voltage (t >.3 s) the SOGI-PLL presets sigificat oscillatios due to the harmoics effect, while the proposed MHDC-PLL achieves a very accurate respose ad is robust agaist harmoics due to the multi-frequecy otch filterig character of the MHDC o the selected harmoics (as preseted i Fig. 4). he PLLs are also tested uder several voltage disturbaces. For example, the MHDC-PLL presets a very accurate ad dyamic respose whe subjected uder the followig sequece of evets: a -3 o phase chage at.4 s, a 5% voltage sag at.6 s, ad a.8 Hz frequecy step at.8 s, despite the voltage harmoic distortio. A higher overshoot o the sychroizatio sigals is preseted by the proposed PLL due to the fast dyamic respose of the MHDC regardig the fudametal frequecy voltage compoet. Some very small but egligible oscillatios o the proposed PLL are preseted (c) 5 IEEE. Persoal use is permitted, but republicatio/redistributio requires IEEE permissio. See for more iformatio.

8 his article has bee accepted for publicatio i a future issue of this joural, but has ot bee fully edited. Cotet may chage prior to fial publicatio. Citatio iformatio: DOI.9/PEL , IEEE rasactios o Power Electroics IEEE RANSACIONS ON POWER ELECRONICS 7 s (pu) f (Hz) oltage Harmoic Distortio -3 o Phase Chage 5% oltage Sag -.8Hz Frequecy Chage SOGI-PLL MHDC-PLL (rad) + () d+ + () q SOGI-PLL time (sec) MHDC-PLL (a) (b) (c) (f -5) [.5 Hz/div] (v d -) [.5 pu/div] v q [.5 pu/div] Harmoic Distortio (f -5) [.5 Hz/div] (v d -) [.5 pu/div] v q [.5 pu/div] (f -5) [.5 Hz/div] (v d -) [. pu/div] v q [.5pu/div] 5% oltage Sag (f -5) [.5 Hz/div] (v d -) [.5 pu/div] v q [.5 pu/div] Harmoic Distortio (f -5) [.5 Hz/div] (v d -) [.5 pu/div] v q [.5 pu/div] 5% oltage Sag (f -5) [.5Hz/div] (v d -) [.pu/div] v q [.5pu/div] Fig. 6. Simulatio results for the respose of SOGI-PLL ad the proposed MHDC-PLL uder harmoic distorted voltage ad phase step chage, voltage sag, ad frequecy step chage. for t >.8 s due to the imperfect respose of the /4 delay compoet used i QSG uder frequecies which are differet from the omial oe. he robust performace of the proposed PLL is also validated accordig to the experimetal results of Fig. 7. he experimetal sychroizatio sigals are depicted i the chaels -4 of the oscilloscope by usig the Digital to Aalogue Coverter (DAC) of the dspace board. he moitorig sigals θ, f, v q ad v d of Fig. 7 represet the sychroizatio sigals that are estimated by the two PLLs. he resposes of the SOGI-PLL (left side) ad the proposed MHDC-PLL (right side) are preseted i Fig. 7 uder several grid coditios: (a) uder ormal operatig coditios, (b) whe a harmoic distortio ( 5 =% ad 7 =% relative to the fudametal ad.% of high-order harmoics) is applied o the grid voltage, (c) uder a 5% voltage sag, (d) uder a -3 o phase jump, ad (e) uder a -.8Hz frequecy step chage. he proposed PLL presets immuity agaist harmoic distortio accordig to Fig. 7(b). Moreover, the MHDC-PLL presets equivalet dyamic respose compared to the SOGI-PLL uder several grid disturbaces (without ay harmoic distortio) as show i Fig. 7(c)-(e). herefore, the harmoic robustess ad a fast dyamic respose is achieved by the proposed sychroizatio method. he oly disadvatage of the proposed PLL is demostrated i Fig. 7(e), where the MHDC-PLL presets some small oscillatio o the sychroizatio sigals uder a o-omial frequecy due to the imperfect respose of the discrete implemeted /4 (d) (e) -3 o Phase Jump -3 o Phase Jump (f -5) [5 Hz/div] (f -5) [5 Hz/div] (v d -) [.4 pu/div] v q [.4pu /div] (f -5) [.5 Hz/div] (v d -) [.5 pu/div] v q [.5 pu/div] -.8Hz Frequecy Chage (v d -) [.4 pu/div] v q [.4 pu/div] -.8Hz Frequecy Chage (f -5) [.5 Hz/div] (v d -) [.5 pu/div] v q [.5 pu/div] Fig. 7. Experimetal results for the sychroizatio respose of the SOGI- PLL (left had side) ad of the MHDC-PLL (right had side). he performace of PLLs are preseted (a) uder ormal grid coditios, (b) whe harmoic distortio is applied o grid voltage, (c) uder a voltage sag, (d) uder a phase jump ad (e) uder a frequecy step chage. delay compoet. It should be oted that these oscillatios ca be miimized by roudig the umber of samples cosidered i the /4 delay compoet to the earest iteger or ca be completely elimiated by usig a variable samplig rate (if this is ot restricted by the rest of the cotrol algorithm of the GSC) similar to the methods described i [3]. Furthermore, the oscillatios uder o-omial frequecy ca completely be elimiated if the /4 delay compoet is developed (c) 5 IEEE. Persoal use is permitted, but republicatio/redistributio requires IEEE permissio. See for more iformatio.

9 his article has bee accepted for publicatio i a future issue of this joural, but has ot bee fully edited. Cotet may chage prior to fial publicatio. Citatio iformatio: DOI.9/PEL , IEEE rasactios o Power Electroics IEEE RANSACIONS ON POWER ELECRONICS 8 s (pu) error (deg) SOGI-PLL MHDC-PLL time (s) Fig. 8. Simulatio results for the respose of the SOGI-PLL ad the proposed MHDC-PLL uder the worst-case harmoic distortio ad uder a worst-case voltage sag (9%). accordig to the fractioal-order delay method of [3]. It is to be oted that the disturbaces durig the experimetal tests were maually recreated by a programmable AC source. herefore, the same disturbace was recreated for each PLL as show i Fig. 7, but the momet of fault was ot a cotrollable variable ad thus, the voltage phase at the istat of fault (ad the iitial disturbace) is differet for each PLL. o further verify the performace of the proposed PLL i terms of a high harmoic immuity, the proposed PLL eeds to be tested uder the worst-case harmoic distortio. herefore, the simulatio results i Fig. 8 demostrate the resposes of SOGI-PLL ad MHDC-PLL uder several harmoic distorted grid voltages. For t <.3 s, the grid voltage is a purely siusoidal voltage (with a voltage HD v equal to.75% due to high order harmoics). For.3 s< t <.4 s, the voltage harmoic distortio icludes oly 3 rd, 5 th, 7 th ad 9 th harmoics ( 3 =5%, 5 =6%, 7 =5%, 9 =.5% relative to the fudametal ad the same high-order harmoics). For t >.4 s, the harmoic distortio of the grid voltage is accordig to the worst-case sceario as defied by the Stadard EN56 [6] ( 3 =5%, 5 =6%, 7 =5%, 9 =.5%, =3.5%, 3 =3%, 5 =.5%, 7 =, 9 =.5%, =.5%, 3 =.5%, 5 =.5% relative to the fudametal ad icludig multiple zero-crossigs). he results of Fig. 8 show that whe the harmoic compoets are cosidered i the decouplig etwork, the the proposed PLL achieves a accurate respose. However, uder the worst-case harmoic distortio some small oscillatios are preset o the phase agle estimatio of the MHDC-PLL due to harmoics that are ot cosidered by the MHDC ad are ot completely elimiated by the QSG of the proposed PLL. Nevertheless, the estimatio error of the proposed PLL is sigificatly miimized to.3 o compared with the 3.5 o of the SOGI-PLL ad is withi the acceptable accuracy. he proposed PLL ca ehace its accuracy if the proposed decouplig etwork (MHDC) is expaded i order to cosider the th ad 3 th harmoic orders too. I such a case, the phase estimatio error ca be miimized to.7 o uder the worst case harmoic distortio. Furthermore, the performace of the two PLLs uder the worst-case voltage sag is also preseted i Fig. 8, where a 9% voltage sag occurs at t=.5 s. Both sychroizatio methods preset a similar dyamic performace sice they require the same settlig time for trackig the phase agle of the grid voltage uder the worstcase voltage sag. herefore, the proposed MHDC-PLL presets a accurate ad fast respose uder ay grid disturbaces with immuity agaist harmoics distortio. his outstadig respose of the sychroizatio method ca be beeficial for sigle-phase grid-tied iverter systems sice a accurate sychroizatio ca ehace its dyamic respose uder ormal ad FR operatio, ad ca improve the power quality of the ijected curret to the grid as has bee show i [3]. I. CONCLUSIONS his paper has proposed a ovel sigle-phase MHDC-PLL, which ca achieve a fast ad accurate sychroizatio uder a distorted grid voltage. he estimatio accuracy of the sychroizatio sigals is eabled by the proposed MHDC, which ca cacel out the oscillatios iduced by low-order harmoics, but without affectig the trasiet respose of the PLL. Simulatio ad experimetal results have verified the accurate ad dyamic respose of the proposed PLL uder highly distorted grid voltages ad uder several grid disturbaces (e.g., voltage sag, phase jump). he oly disadvatages of the proposed PLL are the small oscillatio o the sychroizatio sigals uder o-omial frequecy, which ca be overcome usig a advaced fractioal-order delay method, ad the icreased implemetatio complexity. hus, the dyamic respose ad the immuity agaist voltage harmoic distortio of the proposed sychroizatio method ca beeficially affect the performace of grid-tied iverters, especially i terms of power quality improvemet. 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10 his article has bee accepted for publicatio i a future issue of this joural, but has ot bee fully edited. Cotet may chage prior to fial publicatio. Citatio iformatio: DOI.9/PEL , IEEE rasactios o Power Electroics IEEE RANSACIONS ON POWER ELECRONICS 9 [] L. Zhag, K. Su, H. Hu, ad Y. Xig, A system-level cotrol strategy of photovoltaic grid-tied geeratio systems for Europea efficiecy ehacemet, IEEE ras. Power Electroics, vol. 9, o. 7, pp , July 4. [] L. Hadjidemetriou, E. Kyriakides, ad F. Blaabjerg, A grid side coverter curret cotroller for accurate curret ijectio uder ormal ad fault ride through operatio, i Proc. IEEE IECON, 3, pp [3] A. Nicastri ad A. Nagliero, Compariso ad evaluatio of the PLL techiques for the desig of the grid-coected iverter systems, i Proc. IEEE ISIE,, pp [4] S. Golesta,M.Mofared, F. D. Freijedo, ad J.M. Guerrero, Desig ad tuig of a modified power-based PLL for sigle-phase gridcoected power coditioig systems, IEEE ras. Power Electro., vol. 7, o. 8, pp , Aug.. [5] Y. Yag, F. Blaabjerg, ad Z. Zou, Bechmarkig of grid fault modes i sigle-phase grid-coected photovoltaic systems, IEEE ras. Idustry Applicatios, vol. 49, o. 5, pp , Sep.-Oct. 3. [6] Y. Yag ad F. Blaabjerg, Sychroizatio i sigle-phase gridcoected photovoltaic systems uder grid faults, i Proc. IEEE PEDG,, pp [7] L. N. Arruda, S. M. Silva, ad B. J. C. Filho, PLL structures for utility coected systems, i Proc. IEEE IAS Aual Meetig,,, vol. 4, pp [8] P. Rodriguez, A. Lua, R. Muoz-Aguilar, I. Etxeberria-Otadui, R. eodorescu, ad F. Blaabjerg, A statioary referece frame gridsychroizatio system for three-phase grid-coected power coverters uder adverse grid coditios," IEEE ras. Power Electroics, vol.7, o., pp.99-, Ja. [9] M. K. Ghartemai, S. A. Khajehoddi, P. K. Jai, ad A. Bakhshai, Problems of startup ad phase jumps i PLL systems, IEEE ras. Power Electroics, vol. 7, o. 4, pp , Apr.. [] M. Ciobotaru, R. eodorescu, ad F. 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Wag, Multirate Repetitive Cotrol for PWM DC/AC Coverters, IEEE ras. Idustrial Electroics, vol. 6, o. 6, pp , Jue 4. [6] L. Hadjidemetriou, F. Blaabjerg, ad E. Kyriakides, A ew hybrid PLL for itercoectig reewable eergy systems to the grid, IEEE ras. Idustry Applicatios, vol. 49, o. 6, pp , Nov. 3. [7] L. Hadjidemetriou, F. Blaabjerg, ad E. Kyriakides, A adaptive tuig mechaism for phase-locked loop algorithms for faster time performace of itercoected reewable eergy sources, IEEE ras. Idustry Applicatios, vol. 5, o., pp , Apr. 5. [8] P. Rodriguez, J. Pou, J. Bergas, J. I. Cadela, R. P. Burgos, ad D. Boroyevich, Decoupled double sychroous referece frame PLL for power coverters cotrol, IEEE ras. Power Electroics, vol., o., pp , Mar. 7. [9] L. Hadjidemetriou, E. Kyriakides, ad F. Blaabjerg, Sychroizatio of grid-coected reewable eergy sources uder highly distorted voltages ad ubalaced grid faults, i Proc. IEEE IECON, 3, pp [3] L. Hadjidemetriou, E. Kyriakides, ad F. Blaabjerg, A Robust sychroizatio to ehace the power quality of reewable eergy systems, IEEE ras. Idustrial Electroics, vol. 6, pp. -, 5. [3] S. Golesta, M. Ramezai, J.M. Guerrero, F.D. Freijedo, ad M. Mofared, Movig average filter based phase-locked loops: Performace aalysis ad desig guidelies, IEEE ras. Power Electroics, vol.9, o.6, pp , Jue 4. [3] Y. Yag, K. Zhou, H. Wag, F. Blaabjerg, D. Wag, ad B. Zhag, Frequecy adaptive selective harmoic cotrol for grid-coected iverters, IEEE ras. Power Electroics, vol. 3, o. 7, pp , July 5. Leos Hadjidemetriou (S ) received the Diploma i Electrical ad Computer Egieerig from the Natioal echical Uiversity of Athes, Athes, Greece, i. He is curretly workig toward the Ph.D. degree i the Departmet of Electrical ad Computer Egieerig, Uiversity of Cyprus, Nicosia. Sice, he has also bee a Researcher with the KIOS Research Ceter for Itelliget Systems ad Networks, Uiversity of Cyprus. His research iterests iclude reewable eergy systems, grid sychroizatio methods, fault ride through cotrol, cotrol of wid ad solar systems. Mr. Hadjidemetriou is a member of the Cyprus echical Chamber. He voluteered as a reviewer to several IEEE trasactios ad cofereces ad received the best paper award i the power quality sessio at IEEE IECON3. Elias Kyriakides (S M 4 SM 9) received the B.Sc. degree i Electrical Egieerig from the Illiois Istitute of echology, Chicago, IL, USA, i ad the M.Sc. ad Ph.D. degrees i Electrical Egieerig from Arizoa State Uiversity, empe, AZ, USA, i ad 3, respectively. He is curretly a Associate Professor with the Departmet of Electrical ad Computer Egieerig, Uiversity of Cyprus, Nicosia. He is also a Foudig Member of the KIOS Research Ceter for Itelliget Systems ad Networks. His research iterests iclude modelig of electric machies, sychroized measuremets i power systems, security ad reliability of the power system etworks, optimizatio of power system operatio techiques, ad the itegratio of reewable eergy sources. Yogheg Yag (S -M 5) received his B.Eg. degree i 9 from Northwester Polytechical Uiversity, Chia, ad the Ph.D. degree from Aalborg Uiversity, Demark, i 4. Durig 9, he was with Southeast Uiversity, Najig, Chia as a postgraduate, where he was workig o modelig ad cotrol of sigle-phase grid-coected photovoltaic systems. From March to May 3, he was a isitig Scholar at the Departmet of Electrical ad Computer Egieerig at exas A&M Uiversity, USA. Curretly, Dr. Yag is with the Departmet of Eergy echology at Aalborg Uiversity as a Postdoc Researcher workig o the harmoics i motor drive systems. He is also ivolved i the IEEE Idustry Applicatios Society studet activities, ad the IEEE Power Electroics Society Youg Professioals activities. His research iterests iclude grid itegratio ad cotrol of photovoltaic systems, ad harmoics i adjustable speed drives ad grid-coected power coverters. He is also workig o the reliability of power electroics coverters. Frede Blaabjerg (S 86 M 88 SM 97 F 3) received Ph.D. degrees from Aalborg Uiversity i 99. He is a Full Professor of power electroics ad drives at Aalborg Uiversity, Aalborg, Demark sice 998. His curret research iterests iclude power electroics ad its applicatios i wid turbies, P systems, reliability, harmoics ad adjustable speed drives. He has received 5 IEEE Prize Paper Awards, the IEEE PELS Distiguished Service Award i 9, the EPE-PEMC Coucil Award i, the IEEE William E. Newell Power Electroics Award 4 ad the illum Ka Rasmusse Research Award 4. He was a Editor-i-Chief of the IEEE rasactios o Power Electroics from 6 to. He has bee Distiguished Lecturer for the IEEE Power Electroics Society from 5 to 7 ad for the IEEE Idustry Applicatios Society from to. He was omiated i 4 by homso Reuters to be betwee the most 5 cited researchers i Egieerig i the world (c) 5 IEEE. Persoal use is permitted, but republicatio/redistributio requires IEEE permissio. See for more iformatio.